JP2000031280A - 集積回路のためのメタライゼ―ション装置 - Google Patents
集積回路のためのメタライゼ―ション装置Info
- Publication number
- JP2000031280A JP2000031280A JP11171020A JP17102099A JP2000031280A JP 2000031280 A JP2000031280 A JP 2000031280A JP 11171020 A JP11171020 A JP 11171020A JP 17102099 A JP17102099 A JP 17102099A JP 2000031280 A JP2000031280 A JP 2000031280A
- Authority
- JP
- Japan
- Prior art keywords
- dielectric layer
- metallization
- layer
- substrate
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/099,093 US6137178A (en) | 1998-06-17 | 1998-06-17 | Semiconductor metalization system and method |
| US09/099093 | 1998-06-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000031280A true JP2000031280A (ja) | 2000-01-28 |
| JP2000031280A5 JP2000031280A5 (enExample) | 2006-06-01 |
Family
ID=22272661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11171020A Withdrawn JP2000031280A (ja) | 1998-06-17 | 1999-06-17 | 集積回路のためのメタライゼ―ション装置 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US6137178A (enExample) |
| EP (1) | EP0966035B1 (enExample) |
| JP (1) | JP2000031280A (enExample) |
| KR (1) | KR100598256B1 (enExample) |
| CN (1) | CN1139112C (enExample) |
| DE (1) | DE69930027T2 (enExample) |
| TW (1) | TW417204B (enExample) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6849923B2 (en) | 1999-03-12 | 2005-02-01 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method of the same |
| JP2011527830A (ja) * | 2008-07-09 | 2011-11-04 | テセラ・インターコネクト・マテリアルズ,インコーポレイテッド | 導体間隙が縮小された超小型電子相互接続素子 |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2786609B1 (fr) * | 1998-11-26 | 2003-10-17 | St Microelectronics Sa | Circuit integre a capacite interlignes reduite et procede de fabrication associe |
| US20060017162A1 (en) * | 1999-03-12 | 2006-01-26 | Shoji Seta | Semiconductor device and manufacturing method of the same |
| US6420252B1 (en) * | 2000-05-10 | 2002-07-16 | Emcore Corporation | Methods of forming robust metal contacts on compound semiconductors |
| US7892962B2 (en) * | 2007-09-05 | 2011-02-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nail-shaped pillar for wafer-level chip-scale packaging |
| US8309446B2 (en) | 2008-07-16 | 2012-11-13 | Applied Materials, Inc. | Hybrid heterojunction solar cell fabrication using a doping layer mask |
| EP2359410A4 (en) | 2008-12-10 | 2014-09-24 | Applied Materials Inc | IMPROVED VISIBILITY SYSTEM FOR ALIGNMENT OF SCREEN PRINT PATTERNS |
| US9064968B2 (en) * | 2013-08-19 | 2015-06-23 | Phison Electronics Corp. | Non-volatile memory device and operation and fabricating methods thereof |
| US8772951B1 (en) | 2013-08-29 | 2014-07-08 | Qualcomm Incorporated | Ultra fine pitch and spacing interconnects for substrate |
| US9159670B2 (en) | 2013-08-29 | 2015-10-13 | Qualcomm Incorporated | Ultra fine pitch and spacing interconnects for substrate |
| KR102377372B1 (ko) * | 2014-04-02 | 2022-03-21 | 어플라이드 머티어리얼스, 인코포레이티드 | 인터커넥트들을 형성하기 위한 방법 |
| US20190067178A1 (en) * | 2017-08-30 | 2019-02-28 | Qualcomm Incorporated | Fine pitch and spacing interconnects with reserve interconnect portion |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3057975B2 (ja) * | 1993-09-27 | 2000-07-04 | 日本電気株式会社 | 集積回路の配線 |
| US5471093A (en) * | 1994-10-28 | 1995-11-28 | Advanced Micro Devices, Inc. | Pseudo-low dielectric constant technology |
| JPH08293523A (ja) * | 1995-02-21 | 1996-11-05 | Seiko Epson Corp | 半導体装置およびその製造方法 |
| US5702982A (en) * | 1996-03-28 | 1997-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits |
| US5846876A (en) * | 1996-06-05 | 1998-12-08 | Advanced Micro Devices, Inc. | Integrated circuit which uses a damascene process for producing staggered interconnect lines |
| US5753976A (en) * | 1996-06-14 | 1998-05-19 | Minnesota Mining And Manufacturing Company | Multi-layer circuit having a via matrix interlayer connection |
| KR100219508B1 (ko) * | 1996-12-30 | 1999-09-01 | 윤종용 | 반도체장치의 금속배선층 형성방법 |
-
1998
- 1998-06-17 US US09/099,093 patent/US6137178A/en not_active Expired - Lifetime
-
1999
- 1999-05-31 DE DE69930027T patent/DE69930027T2/de not_active Expired - Lifetime
- 1999-05-31 EP EP99110469A patent/EP0966035B1/en not_active Expired - Lifetime
- 1999-06-08 TW TW088109515A patent/TW417204B/zh not_active IP Right Cessation
- 1999-06-17 KR KR1019990022670A patent/KR100598256B1/ko not_active Expired - Fee Related
- 1999-06-17 CN CNB991086899A patent/CN1139112C/zh not_active Expired - Fee Related
- 1999-06-17 JP JP11171020A patent/JP2000031280A/ja not_active Withdrawn
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6849923B2 (en) | 1999-03-12 | 2005-02-01 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method of the same |
| US7169697B2 (en) | 1999-03-12 | 2007-01-30 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method of the same |
| JP2011527830A (ja) * | 2008-07-09 | 2011-11-04 | テセラ・インターコネクト・マテリアルズ,インコーポレイテッド | 導体間隙が縮小された超小型電子相互接続素子 |
| US8900464B2 (en) | 2008-07-09 | 2014-12-02 | Invensas Corporation | Method of making a microelectronic interconnect element with decreased conductor spacing |
| US9524947B2 (en) | 2008-07-09 | 2016-12-20 | Invensas Corporation | Microelectronic interconnect element with decreased conductor spacing |
| US9856135B2 (en) | 2008-07-09 | 2018-01-02 | Invensas Corporation | Microelectronic interconnect element with decreased conductor spacing |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0966035A1 (en) | 1999-12-22 |
| KR100598256B1 (ko) | 2006-07-07 |
| DE69930027D1 (de) | 2006-04-27 |
| DE69930027T2 (de) | 2006-09-14 |
| CN1254949A (zh) | 2000-05-31 |
| EP0966035B1 (en) | 2006-03-01 |
| US6137178A (en) | 2000-10-24 |
| KR20000006238A (ko) | 2000-01-25 |
| CN1139112C (zh) | 2004-02-18 |
| TW417204B (en) | 2001-01-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6100177A (en) | Grooved wiring structure in semiconductor device and method for forming the same | |
| KR100446293B1 (ko) | 저항체를 포함하는 반도체 소자 제조 방법 | |
| JP2000031280A (ja) | 集積回路のためのメタライゼ―ション装置 | |
| US6919265B2 (en) | Semiconductor device with elongated interconnecting member and fabrication method thereof | |
| JP2022520702A (ja) | 積層された導体ライン及び空隙を有する半導体チップ | |
| US7087350B2 (en) | Method for combining via patterns into a single mask | |
| JPH10209273A (ja) | 半導体装置の製造方法 | |
| US5924006A (en) | Trench surrounded metal pattern | |
| KR100338850B1 (ko) | 매입배선구조 및 그 형성방법 | |
| US7528069B2 (en) | Fine pitch interconnect and method of making | |
| US5792704A (en) | Method for fabricating wiring in semiconductor device | |
| US6107204A (en) | Method to manufacture multiple damascene by utilizing etch selectivity | |
| JPS62229959A (ja) | 超大規模集積回路の多層金属被膜構造物における層間絶縁体中の通路または接触穴の充填方法 | |
| KR102818332B1 (ko) | 자기-정렬된 상단 비아 | |
| KR100591236B1 (ko) | 상호 접속 도전 경로에 대한 선택적 성능 향상 | |
| US6001743A (en) | Method for fabricating a self-aligned contact | |
| HK1022047A (en) | Semiconductor metallization system and method | |
| US8120182B2 (en) | Integrated circuit comprising conductive lines and contact structures and method of manufacturing an integrated circuit | |
| KR100302596B1 (ko) | 반도체장치의금속배선형성방법 | |
| JP2879755B2 (ja) | 半導体装置の製造方法 | |
| JPH0936222A (ja) | 半導体装置及びその製造方法 | |
| JPH0917868A (ja) | 半導体集積回路装置の配線接続構造及びその製造方法 | |
| JP2010087202A (ja) | 半導体装置の製造方法 | |
| JPH05206288A (ja) | 多層配線の形成方法 | |
| JPH10284703A (ja) | 半導体記憶装置及びその製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060407 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060407 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20081008 |
|
| A761 | Written withdrawal of application |
Free format text: JAPANESE INTERMEDIATE CODE: A761 Effective date: 20081225 |