JP2000030456A - メモリデバイス - Google Patents

メモリデバイス

Info

Publication number
JP2000030456A
JP2000030456A JP10198590A JP19859098A JP2000030456A JP 2000030456 A JP2000030456 A JP 2000030456A JP 10198590 A JP10198590 A JP 10198590A JP 19859098 A JP19859098 A JP 19859098A JP 2000030456 A JP2000030456 A JP 2000030456A
Authority
JP
Japan
Prior art keywords
clock
read
circuit
data
clock supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10198590A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000030456A5 (https=
Inventor
Kazuyuki Kanezashi
和幸 金指
Toshiya Uchida
敏也 内田
Masaki Okuda
正樹 奥田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10198590A priority Critical patent/JP2000030456A/ja
Priority to US09/346,919 priority patent/US6337833B1/en
Priority to KR1019990028147A priority patent/KR100573534B1/ko
Publication of JP2000030456A publication Critical patent/JP2000030456A/ja
Publication of JP2000030456A5 publication Critical patent/JP2000030456A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/225—Clock input buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
JP10198590A 1998-07-14 1998-07-14 メモリデバイス Pending JP2000030456A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP10198590A JP2000030456A (ja) 1998-07-14 1998-07-14 メモリデバイス
US09/346,919 US6337833B1 (en) 1998-07-14 1999-07-02 Memory device
KR1019990028147A KR100573534B1 (ko) 1998-07-14 1999-07-13 메모리 디바이스

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10198590A JP2000030456A (ja) 1998-07-14 1998-07-14 メモリデバイス

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2007069871A Division JP2007149341A (ja) 2007-03-19 2007-03-19 メモリデバイス

Publications (2)

Publication Number Publication Date
JP2000030456A true JP2000030456A (ja) 2000-01-28
JP2000030456A5 JP2000030456A5 (https=) 2005-01-13

Family

ID=16393729

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10198590A Pending JP2000030456A (ja) 1998-07-14 1998-07-14 メモリデバイス

Country Status (3)

Country Link
US (1) US6337833B1 (https=)
JP (1) JP2000030456A (https=)
KR (1) KR100573534B1 (https=)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100354468B1 (ko) * 1999-06-30 2002-09-30 가부시끼가이샤 도시바 클럭 동기 회로
KR100426557B1 (ko) * 2000-09-28 2004-04-08 가부시끼가이샤 도시바 클럭 동기 회로 및 반도체 메모리
US6768698B2 (en) 2002-03-29 2004-07-27 Renesas Technology Corp. Semiconductor memory device with internal clock generation circuit
JP2006190434A (ja) * 2004-12-28 2006-07-20 Hynix Semiconductor Inc 半導体記憶素子のクロック生成装置およびクロック生成方法
JP2007095257A (ja) * 2005-09-28 2007-04-12 Hynix Semiconductor Inc 半導体メモリ素子の内部アドレス生成装置
JP2007095267A (ja) * 2005-09-29 2007-04-12 Hynix Semiconductor Inc 遅延固定ループのクロックドライバー制御装置
US7609584B2 (en) 2005-11-19 2009-10-27 Samsung Electronics Co., Ltd. Latency control circuit and method thereof and an auto-precharge control circuit and method thereof
US8358546B2 (en) 2009-11-13 2013-01-22 Samsung Electronics Co., Ltd. Semiconductor device having additive latency

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3535788B2 (ja) * 1999-12-27 2004-06-07 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置
KR20020014563A (ko) * 2000-08-18 2002-02-25 윤종용 반도체 메모리 장치
US6898683B2 (en) * 2000-12-19 2005-05-24 Fujitsu Limited Clock synchronized dynamic memory and clock synchronized integrated circuit
JP3552213B2 (ja) * 2001-08-31 2004-08-11 株式会社東芝 Ｓｄメモリカードホストコントローラ及びクロック制御方法
US6981169B2 (en) * 2002-02-26 2005-12-27 Sun Microsystems, Inc. Modified glitch latch for use with power saving dynamic register file structures
US20070291572A1 (en) * 2006-06-20 2007-12-20 Josef Schnell Clock circuit for semiconductor memory
KR100902048B1 (ko) * 2007-05-14 2009-06-15 주식회사 하이닉스반도체 반도체 장치의 어드레스 수신회로
KR20100115613A (ko) * 2009-04-20 2010-10-28 삼성전자주식회사 레이턴시 전류 소모를 줄일 수 있는 반도체 메모리 장치
WO2011056729A2 (en) 2009-11-05 2011-05-12 Rambus Inc. Interface clock management
US10437514B2 (en) 2017-10-02 2019-10-08 Micron Technology, Inc. Apparatuses and methods including memory commands for semiconductor memories
US10467158B2 (en) 2017-11-29 2019-11-05 Micron Technology, Inc. Apparatuses and methods including memory commands for semiconductor memories

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0142968B1 (ko) * 1995-06-30 1998-08-17 김광호 반도체 메모리 장치의 클럭 발생 장치
KR0164807B1 (ko) * 1995-12-22 1999-02-01 김광호 반도체 메모리 장치의 데이타 출력버퍼 제어회로
JP3759645B2 (ja) * 1995-12-25 2006-03-29 三菱電機株式会社 同期型半導体記憶装置
KR980004976A (ko) * 1996-06-07 1998-03-30 김광호 반도체 메모리 장치의 클럭 발생 제어기 및 클럭 발생 제어 방법
JP3183184B2 (ja) * 1996-08-09 2001-07-03 日本電気株式会社 クロック同期型半導体記憶装置
EP0929075B1 (en) * 1996-09-26 2003-08-20 Mitsubishi Denki Kabushiki Kaisha Synchronous type semiconductor memory device
US5923611A (en) * 1996-12-20 1999-07-13 Micron Technology, Inc. Memory having a plurality of external clock signal inputs
JPH10208470A (ja) * 1997-01-17 1998-08-07 Nec Corp 同期型半導体記憶装置
KR100240419B1 (ko) * 1997-03-18 2000-01-15 윤종용 반도체 메모리 장치 및 그것의 데이터 독출 방법
JP3504104B2 (ja) * 1997-04-03 2004-03-08 富士通株式会社 シンクロナスｄｒａｍ
KR100258859B1 (ko) * 1997-04-30 2000-06-15 김영환 메모리의 데이터 출력 버퍼

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100354468B1 (ko) * 1999-06-30 2002-09-30 가부시끼가이샤 도시바 클럭 동기 회로
KR100426557B1 (ko) * 2000-09-28 2004-04-08 가부시끼가이샤 도시바 클럭 동기 회로 및 반도체 메모리
US6768698B2 (en) 2002-03-29 2004-07-27 Renesas Technology Corp. Semiconductor memory device with internal clock generation circuit
JP2006190434A (ja) * 2004-12-28 2006-07-20 Hynix Semiconductor Inc 半導体記憶素子のクロック生成装置およびクロック生成方法
JP2007095257A (ja) * 2005-09-28 2007-04-12 Hynix Semiconductor Inc 半導体メモリ素子の内部アドレス生成装置
JP2007095267A (ja) * 2005-09-29 2007-04-12 Hynix Semiconductor Inc 遅延固定ループのクロックドライバー制御装置
US7609584B2 (en) 2005-11-19 2009-10-27 Samsung Electronics Co., Ltd. Latency control circuit and method thereof and an auto-precharge control circuit and method thereof
US7911862B2 (en) 2005-11-19 2011-03-22 Samsung Electronics Co., Ltd. Latency control circuit and method thereof and an auto-precharge control circuit and method thereof
US8358546B2 (en) 2009-11-13 2013-01-22 Samsung Electronics Co., Ltd. Semiconductor device having additive latency

Also Published As

Publication number Publication date
KR20000011667A (ko) 2000-02-25
KR100573534B1 (ko) 2006-04-26
US6337833B1 (en) 2002-01-08

Similar Documents

Publication Publication Date Title
JP3695902B2 (ja) 半導体記憶装置
JP2000030456A (ja) メモリデバイス
KR100233973B1 (ko) 동기형 반도체 기억 장치
JP2003249077A (ja) 半導体記憶装置及びその制御方法
JP2000311485A (ja) 選択されるメモリモジュールのみをデータラインに連結するメモリモジュールシステム及びこれを利用したデータ入出力方法
KR20020050086A (ko) 클록 동기형 다이나믹 메모리 및 클록 동기형 집적 회로
JP2000163956A (ja) 半導体記憶装置
JPH08102188A (ja) 同期型半導体記憶装置
US6208582B1 (en) Memory device including a double-rate input/output circuit
JP3177094B2 (ja) 半導体記憶装置
JP2001189077A (ja) 半導体記憶装置及びそのデータ読み出し方法
JPH0969285A (ja) 同期型半導体装置
US6166973A (en) Memory device with multiple-bit data pre-fetch function
JPH1040678A (ja) 半導体記憶装置
JP2002074952A (ja) 同期型半導体記憶装置及びその入力回路の制御方法
JPH09231767A (ja) スタティック型半導体記憶装置
US6636443B2 (en) Semiconductor memory device having row buffers
JP2832693B2 (ja) 出力制御回路を備えたｄｒａｍ
EP0962937B1 (en) Semiconductor intergrated circuit memory and bus control method
JP2003059267A (ja) 半導体記憶装置
JPH11306758A (ja) 半導体記憶装置
JP3693201B2 (ja) 内部動作周波数設定可能なｄｒａｍ
JPH10162576A (ja) 半導体メモリ装置のカラム選択ラインイネーブル回路
US20020001254A1 (en) Synchronous semiconductor memory device
JPH10208468A (ja) 半導体記憶装置並びに同期型半導体記憶装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040218

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040218

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060502

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060703

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20070116

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070319

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20070423

A912 Re-examination (zenchi) completed and case transferred to appeal board

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20070615

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20080731