KR100573534B1 - 메모리 디바이스 - Google Patents
메모리 디바이스 Download PDFInfo
- Publication number
- KR100573534B1 KR100573534B1 KR1019990028147A KR19990028147A KR100573534B1 KR 100573534 B1 KR100573534 B1 KR 100573534B1 KR 1019990028147 A KR1019990028147 A KR 1019990028147A KR 19990028147 A KR19990028147 A KR 19990028147A KR 100573534 B1 KR100573534 B1 KR 100573534B1
- Authority
- KR
- South Korea
- Prior art keywords
- clock
- clock signal
- read
- signal
- supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/225—Clock input buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10198590A JP2000030456A (ja) | 1998-07-14 | 1998-07-14 | メモリデバイス |
| JP98-198590 | 1998-07-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000011667A KR20000011667A (ko) | 2000-02-25 |
| KR100573534B1 true KR100573534B1 (ko) | 2006-04-26 |
Family
ID=16393729
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990028147A Expired - Fee Related KR100573534B1 (ko) | 1998-07-14 | 1999-07-13 | 메모리 디바이스 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6337833B1 (https=) |
| JP (1) | JP2000030456A (https=) |
| KR (1) | KR100573534B1 (https=) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001014847A (ja) * | 1999-06-30 | 2001-01-19 | Toshiba Corp | クロック同期回路 |
| JP3535788B2 (ja) * | 1999-12-27 | 2004-06-07 | Necエレクトロニクス株式会社 | 半導体記憶装置 |
| KR20020014563A (ko) * | 2000-08-18 | 2002-02-25 | 윤종용 | 반도체 메모리 장치 |
| JP2002109880A (ja) * | 2000-09-28 | 2002-04-12 | Toshiba Corp | クロック同期回路 |
| US6898683B2 (en) * | 2000-12-19 | 2005-05-24 | Fujitsu Limited | Clock synchronized dynamic memory and clock synchronized integrated circuit |
| JP3552213B2 (ja) * | 2001-08-31 | 2004-08-11 | 株式会社東芝 | Sdメモリカードホストコントローラ及びクロック制御方法 |
| US6981169B2 (en) * | 2002-02-26 | 2005-12-27 | Sun Microsystems, Inc. | Modified glitch latch for use with power saving dynamic register file structures |
| JP2003297083A (ja) | 2002-03-29 | 2003-10-17 | Mitsubishi Electric Corp | 半導体記憶装置 |
| KR100638747B1 (ko) * | 2004-12-28 | 2006-10-30 | 주식회사 하이닉스반도체 | 반도체 기억 소자의 클럭 생성 장치 및 방법 |
| KR100744042B1 (ko) * | 2005-09-28 | 2007-07-30 | 주식회사 하이닉스반도체 | 반도체메모리소자의 내부 어드레스 생성장치 |
| US7489172B2 (en) * | 2005-09-29 | 2009-02-10 | Hynix Semiconductor Inc. | DLL driver control circuit |
| US7609584B2 (en) | 2005-11-19 | 2009-10-27 | Samsung Electronics Co., Ltd. | Latency control circuit and method thereof and an auto-precharge control circuit and method thereof |
| US20070291572A1 (en) * | 2006-06-20 | 2007-12-20 | Josef Schnell | Clock circuit for semiconductor memory |
| KR100902048B1 (ko) * | 2007-05-14 | 2009-06-15 | 주식회사 하이닉스반도체 | 반도체 장치의 어드레스 수신회로 |
| KR20100115613A (ko) * | 2009-04-20 | 2010-10-28 | 삼성전자주식회사 | 레이턴시 전류 소모를 줄일 수 있는 반도체 메모리 장치 |
| WO2011056729A2 (en) | 2009-11-05 | 2011-05-12 | Rambus Inc. | Interface clock management |
| KR20110052941A (ko) | 2009-11-13 | 2011-05-19 | 삼성전자주식회사 | 어디티브 레이턴시를 가지는 반도체 장치 |
| US10437514B2 (en) | 2017-10-02 | 2019-10-08 | Micron Technology, Inc. | Apparatuses and methods including memory commands for semiconductor memories |
| US10467158B2 (en) | 2017-11-29 | 2019-11-05 | Micron Technology, Inc. | Apparatuses and methods including memory commands for semiconductor memories |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970051227A (ko) * | 1995-12-22 | 1997-07-29 | 김광호 | 반도체 메모리 장치의 데이타 출력버퍼 제어회로 |
| KR980004976A (ko) * | 1996-06-07 | 1998-03-30 | 김광호 | 반도체 메모리 장치의 클럭 발생 제어기 및 클럭 발생 제어 방법 |
| JPH10208470A (ja) * | 1997-01-17 | 1998-08-07 | Nec Corp | 同期型半導体記憶装置 |
| KR19980073725A (ko) * | 1997-03-18 | 1998-11-05 | 윤종용 | 독출 동작시 소모되는 전류를 줄이기 위한 반도체 메모리 장치와 이의 데이터 독출방법 |
| KR19980079350A (ko) * | 1997-04-03 | 1998-11-25 | 세키자와다다시 | 전력 소비를 최소화한 동기 dram |
| KR19980078944A (ko) * | 1997-04-30 | 1998-11-25 | 문정환 | 메모리의 데이터 출력버퍼 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0142968B1 (ko) * | 1995-06-30 | 1998-08-17 | 김광호 | 반도체 메모리 장치의 클럭 발생 장치 |
| JP3759645B2 (ja) * | 1995-12-25 | 2006-03-29 | 三菱電機株式会社 | 同期型半導体記憶装置 |
| JP3183184B2 (ja) * | 1996-08-09 | 2001-07-03 | 日本電気株式会社 | クロック同期型半導体記憶装置 |
| EP0929075B1 (en) * | 1996-09-26 | 2003-08-20 | Mitsubishi Denki Kabushiki Kaisha | Synchronous type semiconductor memory device |
| US5923611A (en) * | 1996-12-20 | 1999-07-13 | Micron Technology, Inc. | Memory having a plurality of external clock signal inputs |
-
1998
- 1998-07-14 JP JP10198590A patent/JP2000030456A/ja active Pending
-
1999
- 1999-07-02 US US09/346,919 patent/US6337833B1/en not_active Expired - Lifetime
- 1999-07-13 KR KR1019990028147A patent/KR100573534B1/ko not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970051227A (ko) * | 1995-12-22 | 1997-07-29 | 김광호 | 반도체 메모리 장치의 데이타 출력버퍼 제어회로 |
| KR980004976A (ko) * | 1996-06-07 | 1998-03-30 | 김광호 | 반도체 메모리 장치의 클럭 발생 제어기 및 클럭 발생 제어 방법 |
| JPH10208470A (ja) * | 1997-01-17 | 1998-08-07 | Nec Corp | 同期型半導体記憶装置 |
| KR19980073725A (ko) * | 1997-03-18 | 1998-11-05 | 윤종용 | 독출 동작시 소모되는 전류를 줄이기 위한 반도체 메모리 장치와 이의 데이터 독출방법 |
| KR19980079350A (ko) * | 1997-04-03 | 1998-11-25 | 세키자와다다시 | 전력 소비를 최소화한 동기 dram |
| KR19980078944A (ko) * | 1997-04-30 | 1998-11-25 | 문정환 | 메모리의 데이터 출력버퍼 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000030456A (ja) | 2000-01-28 |
| KR20000011667A (ko) | 2000-02-25 |
| US6337833B1 (en) | 2002-01-08 |
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