JP2000013206A5 - - Google Patents

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Publication number
JP2000013206A5
JP2000013206A5 JP1998273615A JP27361598A JP2000013206A5 JP 2000013206 A5 JP2000013206 A5 JP 2000013206A5 JP 1998273615 A JP1998273615 A JP 1998273615A JP 27361598 A JP27361598 A JP 27361598A JP 2000013206 A5 JP2000013206 A5 JP 2000013206A5
Authority
JP
Japan
Prior art keywords
clock signal
delay
delayed
predetermined time
logical sum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1998273615A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000013206A (ja
Filing date
Publication date
Priority claimed from KR1019980019831A external-priority patent/KR100286099B1/ko
Application filed filed Critical
Publication of JP2000013206A publication Critical patent/JP2000013206A/ja
Publication of JP2000013206A5 publication Critical patent/JP2000013206A5/ja
Pending legal-status Critical Current

Links

JP10273615A 1998-05-29 1998-09-28 クロックモニタ回路及び同期式半導体メモリ装置 Pending JP2000013206A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR98-19831 1998-05-29
KR1019980019831A KR100286099B1 (ko) 1998-05-29 1998-05-29 클럭모니터회로및이를이용한동기식반도체메모리장치

Publications (2)

Publication Number Publication Date
JP2000013206A JP2000013206A (ja) 2000-01-14
JP2000013206A5 true JP2000013206A5 (enExample) 2005-10-27

Family

ID=19537913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10273615A Pending JP2000013206A (ja) 1998-05-29 1998-09-28 クロックモニタ回路及び同期式半導体メモリ装置

Country Status (4)

Country Link
US (1) US6307412B1 (enExample)
JP (1) JP2000013206A (enExample)
KR (1) KR100286099B1 (enExample)
TW (1) TW420905B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6552578B1 (en) 2002-06-10 2003-04-22 Pericom Semiconductor Corp. Power down circuit detecting duty cycle of input signal
EP1538752A1 (en) * 2003-11-28 2005-06-08 Freescale Semiconductor, Inc. Clock pulse generator apparatus with reduced jitter clock phase
US7417482B2 (en) * 2005-10-31 2008-08-26 Qualcomm Incorporated Adaptive voltage scaling for an electronics device
KR100917619B1 (ko) 2007-11-09 2009-09-17 주식회사 하이닉스반도체 반도체 소자와 그의 구동 방법
WO2010082954A1 (en) * 2009-01-15 2010-07-22 Linear Technology Corporation Pulse-width modulation (pwm) with independently adjustable duty cycle and frequency using two adjustable delays
US10453414B2 (en) * 2017-08-16 2019-10-22 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd GOA circuit and LCD device
US10587253B1 (en) 2018-11-29 2020-03-10 Qualcomm Incorporated Ring oscillator-based programmable delay line
KR102833955B1 (ko) 2020-01-10 2025-07-15 삼성전자주식회사 호스트 장치로부터의 레퍼런스 클럭에 기반하여 전력 상태를 변경하도록 구성되는 스토리지 장치 및 그 동작 방법
CN112466357A (zh) * 2020-12-07 2021-03-09 普冉半导体(上海)股份有限公司 存储器数据读取系统

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62173692A (ja) * 1986-01-28 1987-07-30 Fujitsu Ltd 半導体集積回路
US4988901A (en) * 1988-04-15 1991-01-29 Sharp Kabushiki Kaisha Pulse detecting device for detecting and outputting a pulse signal related to the slower frequency input pulse
KR920005672Y1 (ko) * 1990-04-17 1992-08-18 삼성전자 주식회사 숄더노이즈 제거회로
US5184032A (en) * 1991-04-25 1993-02-02 Texas Instruments Incorporated Glitch reduction in integrated circuits, systems and methods
US5146110A (en) * 1991-05-22 1992-09-08 Samsung Electronics Co., Ltd. Semiconductor memory with substrate voltage generating circuit for removing unwanted substrate current during precharge cycle memory mode of operation
KR950004855B1 (ko) * 1992-10-30 1995-05-15 현대전자산업 주식회사 반도체 메모리 소자의 어드레스 전이 검출 회로
US6078193A (en) * 1998-04-06 2000-06-20 Graychip, Inc. Apparatus and method for providing a static mode for dynamic logic circuits

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