JP2000013206A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2000013206A5 JP2000013206A5 JP1998273615A JP27361598A JP2000013206A5 JP 2000013206 A5 JP2000013206 A5 JP 2000013206A5 JP 1998273615 A JP1998273615 A JP 1998273615A JP 27361598 A JP27361598 A JP 27361598A JP 2000013206 A5 JP2000013206 A5 JP 2000013206A5
- Authority
- JP
- Japan
- Prior art keywords
- clock signal
- delay
- delayed
- predetermined time
- logical sum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed Effects 0.000 claims 3
Claims (1)
- 前記第1遅延及びクロック信号発生手段は、
前記クロック信号がローレベルからハイレベルに遷移する時は、前記クロック信号を第1所定時間だけ遅延させ、前記クロック信号がハイレベルからローレベルに遷移する時は、前記クロック信号を第1所定時間よりも長い第2所定時間だけ遅延させた第1遅延パルスを発生する第1遅延手段と、
前記クロック信号と前記第2遅延手段の出力信号とを論理和を演算する第1論理和手段と、
を具備することを特徴とする請求項1に記載のクロックモニタ回路。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019980019831A KR100286099B1 (ko) | 1998-05-29 | 1998-05-29 | 클럭모니터회로및이를이용한동기식반도체메모리장치 |
KR98-19831 | 1998-05-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2000013206A JP2000013206A (ja) | 2000-01-14 |
JP2000013206A5 true JP2000013206A5 (ja) | 2005-10-27 |
Family
ID=19537913
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10273615A Pending JP2000013206A (ja) | 1998-05-29 | 1998-09-28 | クロックモニタ回路及び同期式半導体メモリ装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US6307412B1 (ja) |
JP (1) | JP2000013206A (ja) |
KR (1) | KR100286099B1 (ja) |
TW (1) | TW420905B (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6552578B1 (en) | 2002-06-10 | 2003-04-22 | Pericom Semiconductor Corp. | Power down circuit detecting duty cycle of input signal |
EP1538752A1 (en) * | 2003-11-28 | 2005-06-08 | Freescale Semiconductor, Inc. | Clock pulse generator apparatus with reduced jitter clock phase |
US7417482B2 (en) * | 2005-10-31 | 2008-08-26 | Qualcomm Incorporated | Adaptive voltage scaling for an electronics device |
KR100917619B1 (ko) | 2007-11-09 | 2009-09-17 | 주식회사 하이닉스반도체 | 반도체 소자와 그의 구동 방법 |
US8207773B2 (en) * | 2009-01-15 | 2012-06-26 | Linear Technology Corporation | Pulse-width modulation (PWM) with independently adjustable duty cycle and frequency using two adjustable delays |
US10453414B2 (en) * | 2017-08-16 | 2019-10-22 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd | GOA circuit and LCD device |
US10587253B1 (en) | 2018-11-29 | 2020-03-10 | Qualcomm Incorporated | Ring oscillator-based programmable delay line |
KR20210090774A (ko) | 2020-01-10 | 2021-07-21 | 삼성전자주식회사 | 호스트 장치로부터의 레퍼런스 클럭에 기반하여 전력 상태를 변경하도록 구성되는 스토리지 장치 및 그 동작 방법 |
CN112466357A (zh) * | 2020-12-07 | 2021-03-09 | 普冉半导体(上海)股份有限公司 | 存储器数据读取系统 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62173692A (ja) * | 1986-01-28 | 1987-07-30 | Fujitsu Ltd | 半導体集積回路 |
US4988901A (en) * | 1988-04-15 | 1991-01-29 | Sharp Kabushiki Kaisha | Pulse detecting device for detecting and outputting a pulse signal related to the slower frequency input pulse |
KR920005672Y1 (ko) * | 1990-04-17 | 1992-08-18 | 삼성전자 주식회사 | 숄더노이즈 제거회로 |
US5184032A (en) * | 1991-04-25 | 1993-02-02 | Texas Instruments Incorporated | Glitch reduction in integrated circuits, systems and methods |
US5146110A (en) * | 1991-05-22 | 1992-09-08 | Samsung Electronics Co., Ltd. | Semiconductor memory with substrate voltage generating circuit for removing unwanted substrate current during precharge cycle memory mode of operation |
KR950004855B1 (ko) * | 1992-10-30 | 1995-05-15 | 현대전자산업 주식회사 | 반도체 메모리 소자의 어드레스 전이 검출 회로 |
US6078193A (en) * | 1998-04-06 | 2000-06-20 | Graychip, Inc. | Apparatus and method for providing a static mode for dynamic logic circuits |
-
1998
- 1998-05-29 KR KR1019980019831A patent/KR100286099B1/ko not_active IP Right Cessation
- 1998-09-28 JP JP10273615A patent/JP2000013206A/ja active Pending
- 1998-11-19 TW TW087119178A patent/TW420905B/zh not_active IP Right Cessation
-
1999
- 1999-06-01 US US09/323,590 patent/US6307412B1/en not_active Expired - Lifetime
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1333361A3 (en) | Computing device having programmable state transitions | |
AU2003265818A1 (en) | Synchronous mirror delay (smd) circuit and method including a ring oscillator for timing coarse and fine delay intervals | |
JP2000013206A5 (ja) | ||
JP2000030448A5 (ja) | ||
EP1163569A4 (en) | METHOD AND CIRCUIT TO RECEIVE DATA CLOCKED AT TWO ENDS | |
JP2000339959A5 (ja) | ||
TWI263898B (en) | Dynamic logic register | |
JPH0540469Y2 (ja) | ||
WO2006004705A3 (en) | Dynamic-to-static logic converter | |
CA2092845A1 (en) | Trigger signal generating circuit | |
JPS57179979A (en) | Clock signal generating circuit | |
JPH02241220A (ja) | パルス列発生装置 | |
JP3211283B2 (ja) | フィルター回路 | |
KR0154730B1 (ko) | 비동기 램용 클럭펄스 발생기 | |
JPH06132791A (ja) | ノイズ除去回路 | |
JPH08195654A (ja) | クロック再生回路 | |
JPS6347083Y2 (ja) | ||
JPH0224279Y2 (ja) | ||
JPH03104317A (ja) | パルス波形変換型d/a変換回路 | |
JPH0256853B2 (ja) | ||
JPH0147065B2 (ja) | ||
JPS58108616A (ja) | 押下げスイツチ回路 | |
JPS61230514A (ja) | パルス除去回路 | |
JP2550999B2 (ja) | 同期パルス発生回路 | |
JPS62184373A (ja) | 試験信号発生回路 |