JP2000339959A5 - - Google Patents

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Publication number
JP2000339959A5
JP2000339959A5 JP1999151913A JP15191399A JP2000339959A5 JP 2000339959 A5 JP2000339959 A5 JP 2000339959A5 JP 1999151913 A JP1999151913 A JP 1999151913A JP 15191399 A JP15191399 A JP 15191399A JP 2000339959 A5 JP2000339959 A5 JP 2000339959A5
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JP
Japan
Prior art keywords
clock signal
circuit
sel
clock
lck
Prior art date
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Application number
JP1999151913A
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English (en)
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JP4268726B2 (ja
JP2000339959A (ja
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Publication date
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Priority to JP15191399A priority Critical patent/JP4268726B2/ja
Priority claimed from JP15191399A external-priority patent/JP4268726B2/ja
Priority to US09/437,739 priority patent/US6278303B1/en
Publication of JP2000339959A publication Critical patent/JP2000339959A/ja
Publication of JP2000339959A5 publication Critical patent/JP2000339959A5/ja
Application granted granted Critical
Publication of JP4268726B2 publication Critical patent/JP4268726B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

図１８は、特開平７−２０２６８７号公報に記載されたクロック回路４００の構成を示す回路図である。
帰還クロック信号ＦＣＫは、論理回路ＬＤに供給されるローカルクロック信号ＬＣＫが選択回路ＳＥＬを経由して出力された信号である。したがって、選択回路ＳＥＬによる遅延時間分だけのオフセット時間ＴＯＦ分だけ外部クロック信号ＣＬＫに対してローカルクロック信号ＬＣＫは位相が進んだクロック信号となってしまう。
【図１８】 特開平７−２０２６８７号公報に記載されたクロック回路４０
０の構成を示す回路図である。
JP15191399A 1999-05-31 1999-05-31 半導体装置 Expired - Fee Related JP4268726B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP15191399A JP4268726B2 (ja) 1999-05-31 1999-05-31 半導体装置
US09/437,739 US6278303B1 (en) 1999-05-31 1999-11-10 Semiconductor device that can have standby current reduced by ceasing supply of clock signal, and that can maintain status of internal circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15191399A JP4268726B2 (ja) 1999-05-31 1999-05-31 半導体装置

Publications (3)

Publication Number Publication Date
JP2000339959A JP2000339959A (ja) 2000-12-08
JP2000339959A5 true JP2000339959A5 (ja) 2006-06-15
JP4268726B2 JP4268726B2 (ja) 2009-05-27

Family

ID=15528946

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15191399A Expired - Fee Related JP4268726B2 (ja) 1999-05-31 1999-05-31 半導体装置

Country Status (2)

Country Link
US (1) US6278303B1 (ja)
JP (1) JP4268726B2 (ja)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4008583B2 (ja) * 1998-07-22 2007-11-14 株式会社沖データ 電子機器
KR100543934B1 (ko) * 2000-05-31 2006-01-23 주식회사 하이닉스반도체 반도체 메모리 장치에서 어드레스 및 데이터 억세스타임을 고속으로 하는 제어 및 어드레스 장치
JP2002093167A (ja) * 2000-09-08 2002-03-29 Mitsubishi Electric Corp 半導体記憶装置
US7177208B2 (en) * 2005-03-11 2007-02-13 Micron Technology, Inc. Circuit and method for operating a delay-lock loop in a power saving manner
JP4862588B2 (ja) * 2006-09-27 2012-01-25 ソニー株式会社 クロック制御回路および半導体集積回路
KR100917630B1 (ko) * 2008-04-30 2009-09-17 주식회사 하이닉스반도체 지연 고정 루프 회로
KR101027688B1 (ko) 2009-09-30 2011-04-12 주식회사 하이닉스반도체 반도체 장치
KR101253443B1 (ko) * 2011-06-09 2013-04-11 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 동작 방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4025720A (en) * 1975-05-30 1977-05-24 Gte Automatic Electric Laboratories Incorporated Digital bit rate converter
US5339278A (en) * 1993-04-12 1994-08-16 Motorola, Inc. Method and apparatus for standby recovery in a phase locked loop
JP3048495B2 (ja) 1994-01-07 2000-06-05 沖電気工業株式会社 クロック回路
US5703537A (en) * 1996-07-03 1997-12-30 Microclock Incorporated Phase-locked loop clock circuit for generation of audio sampling clock signals from video reference signals
KR100295045B1 (ko) * 1998-06-23 2001-07-12 윤종용 지연동기루프(dll)를구비한반도체메모리장치

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