IT201700108905A1 - Memoria a cambiamento di fase con selettori in tecnologia bjt e relativo metodo di lettura differenziale - Google Patents

Memoria a cambiamento di fase con selettori in tecnologia bjt e relativo metodo di lettura differenziale

Info

Publication number
IT201700108905A1
IT201700108905A1 IT102017000108905A IT201700108905A IT201700108905A1 IT 201700108905 A1 IT201700108905 A1 IT 201700108905A1 IT 102017000108905 A IT102017000108905 A IT 102017000108905A IT 201700108905 A IT201700108905 A IT 201700108905A IT 201700108905 A1 IT201700108905 A1 IT 201700108905A1
Authority
IT
Italy
Prior art keywords
selectors
phase change
change memory
reading method
differential reading
Prior art date
Application number
IT102017000108905A
Other languages
English (en)
Inventor
Antonino Conte
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT102017000108905A priority Critical patent/IT201700108905A1/it
Priority to US16/133,097 priority patent/US10573382B2/en
Priority to CN201811082477.3A priority patent/CN109584931B/zh
Priority to CN201821516478.XU priority patent/CN209183269U/zh
Publication of IT201700108905A1 publication Critical patent/IT201700108905A1/it
Priority to US16/717,652 priority patent/US10720210B2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0028—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0042—Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
IT102017000108905A 2017-09-28 2017-09-28 Memoria a cambiamento di fase con selettori in tecnologia bjt e relativo metodo di lettura differenziale IT201700108905A1 (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT102017000108905A IT201700108905A1 (it) 2017-09-28 2017-09-28 Memoria a cambiamento di fase con selettori in tecnologia bjt e relativo metodo di lettura differenziale
US16/133,097 US10573382B2 (en) 2017-09-28 2018-09-17 Phase-change memory with selectors in BJT technology and differential-reading method thereof
CN201811082477.3A CN109584931B (zh) 2017-09-28 2018-09-17 具有bjt技术中的选择器的相变存储器及其差分读取方法
CN201821516478.XU CN209183269U (zh) 2017-09-28 2018-09-17 相变存储器设备
US16/717,652 US10720210B2 (en) 2017-09-28 2019-12-17 Phase-change memory with selectors in BJT technology and differential-reading method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT102017000108905A IT201700108905A1 (it) 2017-09-28 2017-09-28 Memoria a cambiamento di fase con selettori in tecnologia bjt e relativo metodo di lettura differenziale

Publications (1)

Publication Number Publication Date
IT201700108905A1 true IT201700108905A1 (it) 2019-03-28

Family

ID=61006267

Family Applications (1)

Application Number Title Priority Date Filing Date
IT102017000108905A IT201700108905A1 (it) 2017-09-28 2017-09-28 Memoria a cambiamento di fase con selettori in tecnologia bjt e relativo metodo di lettura differenziale

Country Status (3)

Country Link
US (2) US10573382B2 (it)
CN (2) CN109584931B (it)
IT (1) IT201700108905A1 (it)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT201700108905A1 (it) * 2017-09-28 2019-03-28 St Microelectronics Srl Memoria a cambiamento di fase con selettori in tecnologia bjt e relativo metodo di lettura differenziale
IT201800003796A1 (it) 2018-03-20 2019-09-20 St Microelectronics Srl Dispositivo di memoria non volatile con modalita' di lettura commutabile e relativo metodo di lettura
IT201900011523A1 (it) 2019-07-11 2021-01-11 St Microelectronics Srl Memoria a cambiamento di fase con circuito di regolazione della tensione di alimentazione
US11043276B1 (en) * 2020-02-20 2021-06-22 Sandisk Technologies Llc Sense amplifier architecture providing improved memory performance
IT202100024365A1 (it) * 2021-09-22 2023-03-22 St Microelectronics Srl Procedimento per accedere a celle di memoria, corrispondenti circuito e dispositivo di memorizzazione dati

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120026777A1 (en) * 2010-07-29 2012-02-02 Sony Corporation Variable-resistance memory device
US20150070971A1 (en) * 2013-09-11 2015-03-12 Akira Katayama Resistance change memory
US9646684B1 (en) * 2016-08-02 2017-05-09 Stmicroelectronics S.R.L. PCM memory with margin current addition and related methods

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0782758B2 (ja) * 1987-03-16 1995-09-06 株式会社日立製作所 半導体記憶装置
JPH09275570A (ja) * 1996-04-08 1997-10-21 Sony Corp アナログ遅延回路
JPH1139880A (ja) * 1997-07-16 1999-02-12 Mitsubishi Electric Corp 半導体記憶装置
EP1505605A1 (en) * 2003-08-06 2005-02-09 STMicroelectronics S.r.l. Improved sensing circuit for a semiconductor memory including bit line precharging and discharging functions
JP4381278B2 (ja) * 2004-10-14 2009-12-09 株式会社東芝 不揮発性半導体記憶装置の制御方法
KR100690914B1 (ko) * 2005-08-10 2007-03-09 삼성전자주식회사 상변화 메모리 장치
KR100811278B1 (ko) * 2006-12-29 2008-03-07 주식회사 하이닉스반도체 셀프 부스팅을 이용한 낸드 플래시 메모리소자의 읽기 방법
US7570507B2 (en) * 2007-06-29 2009-08-04 Infineon Technologies North America Corp. Quasi-differential read operation
KR20090110494A (ko) * 2008-04-18 2009-10-22 삼성전자주식회사 반도체 메모리 장치
KR101481401B1 (ko) * 2008-05-19 2015-01-14 삼성전자주식회사 비휘발성 기억 장치
JP2010182353A (ja) * 2009-02-04 2010-08-19 Elpida Memory Inc 半導体記憶装置とその読み出し方法
KR20110025487A (ko) * 2009-09-04 2011-03-10 삼성전자주식회사 반도체 메모리 장치
JP5521612B2 (ja) * 2010-02-15 2014-06-18 ソニー株式会社 不揮発性半導体メモリデバイス
KR101802448B1 (ko) * 2010-10-12 2017-11-28 삼성전자주식회사 상변화 메모리 장치 및 상변화 메모리 장치의 리라이트 동작 방법
US9281061B2 (en) * 2012-09-19 2016-03-08 Micron Technology, Inc. Methods and apparatuses having a voltage generator with an adjustable voltage drop for representing a voltage drop of a memory cell and/or a current mirror circuit and replica circuit
ITUB20155867A1 (it) * 2015-11-24 2017-05-24 St Microelectronics Srl Circuito amplificatore di lettura con compensazione dell'offset per un dispositivo di memoria non volatile
ITUA20161478A1 (it) * 2016-03-09 2017-09-09 St Microelectronics Srl Circuito e metodo di lettura di una cella di memoria di un dispositivo di memoria non volatile
IT201700108905A1 (it) * 2017-09-28 2019-03-28 St Microelectronics Srl Memoria a cambiamento di fase con selettori in tecnologia bjt e relativo metodo di lettura differenziale

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120026777A1 (en) * 2010-07-29 2012-02-02 Sony Corporation Variable-resistance memory device
US20150070971A1 (en) * 2013-09-11 2015-03-12 Akira Katayama Resistance change memory
US9646684B1 (en) * 2016-08-02 2017-05-09 Stmicroelectronics S.R.L. PCM memory with margin current addition and related methods

Also Published As

Publication number Publication date
US10720210B2 (en) 2020-07-21
US20190096480A1 (en) 2019-03-28
CN209183269U (zh) 2019-07-30
US10573382B2 (en) 2020-02-25
US20200126616A1 (en) 2020-04-23
CN109584931A (zh) 2019-04-05
CN109584931B (zh) 2022-12-02

Similar Documents

Publication Publication Date Title
IT201700108905A1 (it) Memoria a cambiamento di fase con selettori in tecnologia bjt e relativo metodo di lettura differenziale
DK3028213T3 (da) Beskyttelse af data i hukommelsen på et forbrugerprodukt
WO2014150791A3 (en) Reading a memory cell using a reference cell and a common sensing path
EP3295310A4 (en) Concurrent read and reconfigured write operations in a memory device
DE112014000254T8 (de) Mehrstufiges Zwischenspeichern und Migrieren in unterschiedlichen Granularitäten
EP3183731A4 (en) Redundant magnetic tunnel junctions in magnetoresistive memory
FR3042634B1 (fr) Point memoire magnetique
FR3031622B1 (fr) Point memoire magnetique
DK3535397T3 (da) Alfa-v-beta-6-integrin-ligander og anvendelser deraf
HUE058193T2 (hu) Memóriabankok és kiválasztási regiszterek elhelyezése
TW201614673A (en) Nonvolatile semiconductor memory device
FR3048810B1 (fr) Cellule memoire cam
GB2555633B (en) Updating data stored in a memory
ITUA20163063A1 (it) Serratura elettronica e relativo metodo di funzionamento
GB2553017B (en) Arrangement for, and method of, reading RFID product tags with improved performance by reading RFID tags of interest in a venue
EP3699955A4 (en) ELEMENT WITH TUNNEL MAGNET RESISTANCE EFFECT, MAGNETIC MEMORY AND BUILT-IN MEMORY
FR3038133B1 (fr) Cellule memoire a changement de phase ayant une structure compacte
IT201700105778A1 (it) Boccola avanzata a gradiente di capacitanza ad alta tensione.
FR3045888B1 (fr) Carte a puce a bords personnalises
IT201700095994A1 (it) Elemento logico a superconduttori
EP3563214A4 (en) ENABLE FUNCTIONS OF A STORAGE DEVICE IN A VARIETY OF PHASES
ES1148159Y (es) Libro con memoria incorporada
FI20165821A (fi) Menetelmä fysikaalisten suureitten mittaamiseksi ja menetelmässä hyödynnettävä mittausjärjestely
FR3042303B1 (fr) Point memoire magnetique
WO2015011059A3 (en) Graphical data representation