IT201700034719A1 - Metodo per controllare le operazioni di verifica di programmazione di una memoria non volatile e relativo circuito - Google Patents

Metodo per controllare le operazioni di verifica di programmazione di una memoria non volatile e relativo circuito

Info

Publication number
IT201700034719A1
IT201700034719A1 IT102017000034719A IT201700034719A IT201700034719A1 IT 201700034719 A1 IT201700034719 A1 IT 201700034719A1 IT 102017000034719 A IT102017000034719 A IT 102017000034719A IT 201700034719 A IT201700034719 A IT 201700034719A IT 201700034719 A1 IT201700034719 A1 IT 201700034719A1
Authority
IT
Italy
Prior art keywords
controlling
volatile memory
verification operations
programming verification
relative circuit
Prior art date
Application number
IT102017000034719A
Other languages
English (en)
Inventor
Alessandro Sanasi
Chiara Missiroli
Stefano Sivero
Original Assignee
Sk Hynix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sk Hynix Inc filed Critical Sk Hynix Inc
Priority to IT102017000034719A priority Critical patent/IT201700034719A1/it
Priority to KR1020180032839A priority patent/KR102496989B1/ko
Priority to US15/937,994 priority patent/US10553297B2/en
Publication of IT201700034719A1 publication Critical patent/IT201700034719A1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification
IT102017000034719A 2017-03-29 2017-03-29 Metodo per controllare le operazioni di verifica di programmazione di una memoria non volatile e relativo circuito IT201700034719A1 (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT102017000034719A IT201700034719A1 (it) 2017-03-29 2017-03-29 Metodo per controllare le operazioni di verifica di programmazione di una memoria non volatile e relativo circuito
KR1020180032839A KR102496989B1 (ko) 2017-03-29 2018-03-21 메모리 장치 및 이의 동작 방법
US15/937,994 US10553297B2 (en) 2017-03-29 2018-03-28 Method for controlling program verify operations of a non-volatile memory and a corresponding circuit thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT102017000034719A IT201700034719A1 (it) 2017-03-29 2017-03-29 Metodo per controllare le operazioni di verifica di programmazione di una memoria non volatile e relativo circuito

Publications (1)

Publication Number Publication Date
IT201700034719A1 true IT201700034719A1 (it) 2018-09-29

Family

ID=59521570

Family Applications (1)

Application Number Title Priority Date Filing Date
IT102017000034719A IT201700034719A1 (it) 2017-03-29 2017-03-29 Metodo per controllare le operazioni di verifica di programmazione di una memoria non volatile e relativo circuito

Country Status (3)

Country Link
US (1) US10553297B2 (it)
KR (1) KR102496989B1 (it)
IT (1) IT201700034719A1 (it)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10522226B2 (en) 2018-05-01 2019-12-31 Silicon Storage Technology, Inc. Method and apparatus for high voltage generation for analog neural memory in deep learning artificial neural network
US10726925B2 (en) * 2018-09-26 2020-07-28 Sandisk Technologies Llc Manage source line bias to account for non-uniform resistance of memory cell source lines
US10910027B2 (en) 2019-04-12 2021-02-02 Micron Technology, Inc. Apparatuses and methods for controlling word line discharge
US10937476B2 (en) * 2019-06-24 2021-03-02 Micron Technology, Inc. Apparatuses and methods for controlling word line discharge
JP2021047960A (ja) * 2019-09-19 2021-03-25 キオクシア株式会社 半導体記憶装置
US11049578B1 (en) * 2020-02-19 2021-06-29 Sandisk Technologies Llc Non-volatile memory with program verify skip
US11205470B2 (en) 2020-04-20 2021-12-21 Micron Technology, Inc. Apparatuses and methods for providing main word line signal with dynamic well
JP2023525118A (ja) 2020-05-13 2023-06-14 マイクロン テクノロジー，インク． メモリセルにアクセスするためのカウンタベースの方法及びシステム
US11664073B2 (en) 2021-04-02 2023-05-30 Micron Technology, Inc. Adaptively programming memory cells in different modes to optimize performance
US11514983B2 (en) 2021-04-02 2022-11-29 Micron Technology, Inc. Identify the programming mode of memory cells based on cell statistics obtained during reading of the memory cells
US11615854B2 (en) 2021-04-02 2023-03-28 Micron Technology, Inc. Identify the programming mode of memory cells during reading of the memory cells

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080247228A1 (en) * 2007-04-05 2008-10-09 Hao Thai Nguyen Non-volatile storage with current sensing of negative threshold voltages
US20170084347A1 (en) * 2015-09-18 2017-03-23 Intel Corporation On demand knockout of coarse sensing based on dynamic source bounce detection

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100788386B1 (ko) * 2001-12-14 2007-12-31 엘지.필립스 엘시디 주식회사 액정표시장치의 공통전압 구동회로
KR101053700B1 (ko) * 2009-05-11 2011-08-02 주식회사 하이닉스반도체 전압 생성 회로 및 이를 구비한 불휘발성 메모리 소자

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080247228A1 (en) * 2007-04-05 2008-10-09 Hao Thai Nguyen Non-volatile storage with current sensing of negative threshold voltages
US20170084347A1 (en) * 2015-09-18 2017-03-23 Intel Corporation On demand knockout of coarse sensing based on dynamic source bounce detection

Also Published As

Publication number Publication date
US20180286488A1 (en) 2018-10-04
KR20180110600A (ko) 2018-10-10
US10553297B2 (en) 2020-02-04
KR102496989B1 (ko) 2023-02-09

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