IT1397222B1 - Metodo per controllare il corretto posizionamento di sonde di test su terminazioni di dispositivi elettronici integrati su semiconduttore e relativo dispositivo elettronico. - Google Patents

Metodo per controllare il corretto posizionamento di sonde di test su terminazioni di dispositivi elettronici integrati su semiconduttore e relativo dispositivo elettronico.

Info

Publication number
IT1397222B1
IT1397222B1 ITMI2009A002332A ITMI20092332A IT1397222B1 IT 1397222 B1 IT1397222 B1 IT 1397222B1 IT MI2009A002332 A ITMI2009A002332 A IT MI2009A002332A IT MI20092332 A ITMI20092332 A IT MI20092332A IT 1397222 B1 IT1397222 B1 IT 1397222B1
Authority
IT
Italy
Prior art keywords
terminations
check
semiconductor
correct position
electronic device
Prior art date
Application number
ITMI2009A002332A
Other languages
English (en)
Inventor
Alberto Pagani
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to ITMI2009A002332A priority Critical patent/IT1397222B1/it
Priority to US12/974,957 priority patent/US9146273B2/en
Publication of ITMI20092332A1 publication Critical patent/ITMI20092332A1/it
Application granted granted Critical
Publication of IT1397222B1 publication Critical patent/IT1397222B1/it
Priority to US14/868,904 priority patent/US9823300B2/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • G01R31/2889—Interfaces, e.g. between probe and tester
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • G01R31/2891—Features relating to contacting the IC under test, e.g. probe heads; chucks related to sensing or controlling of force, position, temperature
ITMI2009A002332A 2009-12-30 2009-12-30 Metodo per controllare il corretto posizionamento di sonde di test su terminazioni di dispositivi elettronici integrati su semiconduttore e relativo dispositivo elettronico. IT1397222B1 (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
ITMI2009A002332A IT1397222B1 (it) 2009-12-30 2009-12-30 Metodo per controllare il corretto posizionamento di sonde di test su terminazioni di dispositivi elettronici integrati su semiconduttore e relativo dispositivo elettronico.
US12/974,957 US9146273B2 (en) 2009-12-30 2010-12-21 Process for controlling the correct positioning of test probes on terminations of electronic devices integrated on a semiconductor and corresponding electronic device
US14/868,904 US9823300B2 (en) 2009-12-30 2015-09-29 Process for controlling the correct positioning of test probes on terminations of electronic devices integrated on a semiconductor and corresponding electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITMI2009A002332A IT1397222B1 (it) 2009-12-30 2009-12-30 Metodo per controllare il corretto posizionamento di sonde di test su terminazioni di dispositivi elettronici integrati su semiconduttore e relativo dispositivo elettronico.

Publications (2)

Publication Number Publication Date
ITMI20092332A1 ITMI20092332A1 (it) 2011-06-30
IT1397222B1 true IT1397222B1 (it) 2013-01-04

Family

ID=42470747

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI2009A002332A IT1397222B1 (it) 2009-12-30 2009-12-30 Metodo per controllare il corretto posizionamento di sonde di test su terminazioni di dispositivi elettronici integrati su semiconduttore e relativo dispositivo elettronico.

Country Status (2)

Country Link
US (2) US9146273B2 (it)
IT (1) IT1397222B1 (it)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1397222B1 (it) * 2009-12-30 2013-01-04 St Microelectronics Srl Metodo per controllare il corretto posizionamento di sonde di test su terminazioni di dispositivi elettronici integrati su semiconduttore e relativo dispositivo elettronico.
JP2012256787A (ja) * 2011-06-10 2012-12-27 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
US9997423B2 (en) * 2014-04-08 2018-06-12 Nxp Usa, Inc. Semiconductor wafer and method of concurrently testing circuits formed thereon
US9716031B2 (en) * 2014-04-08 2017-07-25 Nxp Usa, Inc. Semiconductor wafer and method of concurrently testing circuits formed thereon
KR20160076219A (ko) * 2014-12-22 2016-06-30 에스케이하이닉스 주식회사 얼라인먼트 검사 장치 및 이를 포함하는 반도체 집적 회로 장치
US10180454B2 (en) * 2015-12-01 2019-01-15 Texas Instruments Incorporated Systems and methods of testing multiple dies
DE102020102282B3 (de) 2020-01-30 2021-04-08 Infineon Technologies Ag Halbleitervorrichtung mit ausrichtungspads und verfahren zu deren herstellung
US11412502B2 (en) 2020-03-05 2022-08-09 Cisco Technology, Inc. Cooperative sounding based on coherent subcarrier assignments
US11467207B2 (en) 2020-12-23 2022-10-11 Industrial Technology Research Institute Massive testing of micro integrated circuit

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JPH0645419A (ja) * 1992-07-21 1994-02-18 Hitachi Ltd 半導体装置
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JPH09107011A (ja) * 1995-10-11 1997-04-22 Sharp Corp 半導体装置、およびこの半導体装置の位置合わせ方法
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US6943063B2 (en) * 2001-11-20 2005-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. RF seal ring structure
DE10213609B4 (de) * 2002-03-27 2006-02-09 Infineon Technologies Ag Elektrisches Bauelement mit einer Kontaktierungsfläche und Verfahren zum Ausbilden einer Kontaktierungsfläche auf einem Halbleitermaterial
US6974782B2 (en) * 2002-08-09 2005-12-13 R. Foulke Development Company, Llc Reticle tracking and cleaning
US20050063431A1 (en) * 2003-09-19 2005-03-24 Gallup Kendra J. Integrated optics and electronics
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JP2006038599A (ja) * 2004-07-26 2006-02-09 Nec Electronics Corp 接触抵抗測定方法，接触抵抗測定装置，及び半導体ウェハー
JP4570446B2 (ja) * 2004-11-16 2010-10-27 パナソニック株式会社 半導体ウェハーおよびその検査方法
US20060109120A1 (en) * 2004-11-19 2006-05-25 Jeremy Burr RFID tag in a substrate
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KR100739629B1 (ko) * 2005-12-02 2007-07-16 삼성전자주식회사 프로브 센싱용 패드 및 이를 이용한 프로브 니들 접촉 위치검사 방법.
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JP2007335550A (ja) * 2006-06-14 2007-12-27 Seiko Instruments Inc 半導体装置
KR100843227B1 (ko) * 2007-01-08 2008-07-02 삼성전자주식회사 프로브를 이용한 반도체 메모리 장치의 테스트 방법 및 그방법을 사용하는 반도체 메모리 장치
US7893459B2 (en) * 2007-04-10 2011-02-22 Taiwan Semiconductor Manufacturing Company, Ltd. Seal ring structures with reduced moisture-induced reliability degradation
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US7759955B2 (en) * 2007-12-21 2010-07-20 Infineon Technologies Ag Method and device for position detection using connection pads
JP4484934B2 (ja) * 2008-02-26 2010-06-16 富士通メディアデバイス株式会社 電子部品及びその製造方法
JP2010153753A (ja) * 2008-12-26 2010-07-08 Renesas Electronics Corp 半導体装置
JP5535490B2 (ja) * 2009-01-30 2014-07-02 住友電工デバイス・イノベーション株式会社 半導体装置
IT1397222B1 (it) * 2009-12-30 2013-01-04 St Microelectronics Srl Metodo per controllare il corretto posizionamento di sonde di test su terminazioni di dispositivi elettronici integrati su semiconduttore e relativo dispositivo elettronico.
US9716031B2 (en) * 2014-04-08 2017-07-25 Nxp Usa, Inc. Semiconductor wafer and method of concurrently testing circuits formed thereon

Also Published As

Publication number Publication date
US9146273B2 (en) 2015-09-29
ITMI20092332A1 (it) 2011-06-30
US9823300B2 (en) 2017-11-21
US20160018461A1 (en) 2016-01-21
US20110156732A1 (en) 2011-06-30

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