IT1313873B1 - Architettura per la gestione delle tensioni interne in una memoria nonvolatile, in particolare di tipo flash dual-work a singola tensione di - Google Patents

Architettura per la gestione delle tensioni interne in una memoria nonvolatile, in particolare di tipo flash dual-work a singola tensione di

Info

Publication number
IT1313873B1
IT1313873B1 IT1999MI002372A ITMI992372A IT1313873B1 IT 1313873 B1 IT1313873 B1 IT 1313873B1 IT 1999MI002372 A IT1999MI002372 A IT 1999MI002372A IT MI992372 A ITMI992372 A IT MI992372A IT 1313873 B1 IT1313873 B1 IT 1313873B1
Authority
IT
Italy
Prior art keywords
architecture
management
volatile memory
single voltage
flash type
Prior art date
Application number
IT1999MI002372A
Other languages
English (en)
Inventor
Simone Bartoli
Lorenzo Bedarida
Mauro Sali
Antonio Russo
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT1999MI002372A priority Critical patent/IT1313873B1/it
Publication of ITMI992372A0 publication Critical patent/ITMI992372A0/it
Priority to US09/710,067 priority patent/US6385107B1/en
Publication of ITMI992372A1 publication Critical patent/ITMI992372A1/it
Application granted granted Critical
Publication of IT1313873B1 publication Critical patent/IT1313873B1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Static Random-Access Memory (AREA)
IT1999MI002372A 1999-11-12 1999-11-12 Architettura per la gestione delle tensioni interne in una memoria nonvolatile, in particolare di tipo flash dual-work a singola tensione di IT1313873B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT1999MI002372A IT1313873B1 (it) 1999-11-12 1999-11-12 Architettura per la gestione delle tensioni interne in una memoria nonvolatile, in particolare di tipo flash dual-work a singola tensione di
US09/710,067 US6385107B1 (en) 1999-11-12 2000-11-09 Architecture for handling internal voltages in a non-volatile memory, particularly in a single-voltage supply type of dual-work flash memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT1999MI002372A IT1313873B1 (it) 1999-11-12 1999-11-12 Architettura per la gestione delle tensioni interne in una memoria nonvolatile, in particolare di tipo flash dual-work a singola tensione di

Publications (3)

Publication Number Publication Date
ITMI992372A0 ITMI992372A0 (it) 1999-11-12
ITMI992372A1 ITMI992372A1 (it) 2001-05-12
IT1313873B1 true IT1313873B1 (it) 2002-09-24

Family

ID=11383949

Family Applications (1)

Application Number Title Priority Date Filing Date
IT1999MI002372A IT1313873B1 (it) 1999-11-12 1999-11-12 Architettura per la gestione delle tensioni interne in una memoria nonvolatile, in particolare di tipo flash dual-work a singola tensione di

Country Status (2)

Country Link
US (1) US6385107B1 (it)
IT (1) IT1313873B1 (it)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6611463B1 (en) * 2001-11-14 2003-08-26 Lattice Semiconductor Corporation Zero-power programmable memory cell
US20040257882A1 (en) * 2003-06-20 2004-12-23 Blaine Stackhouse Bias generation having adjustable range and resolution through metal programming
KR100609039B1 (ko) * 2004-06-30 2006-08-10 주식회사 하이닉스반도체 입출력 라인 회로
US7414891B2 (en) * 2007-01-04 2008-08-19 Atmel Corporation Erase verify method for NAND-type flash memories
JP4996277B2 (ja) 2007-02-09 2012-08-08 株式会社東芝 半導体記憶システム
US7613051B2 (en) * 2007-03-14 2009-11-03 Apple Inc. Interleaving charge pumps for programmable memories
US8064274B2 (en) * 2007-05-30 2011-11-22 Micron Technology, Inc. Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same
US8710907B2 (en) * 2008-06-24 2014-04-29 Sandisk Technologies Inc. Clock generator circuit for a charge pump
US8054694B2 (en) * 2009-03-24 2011-11-08 Atmel Corporation Voltage generator for memory array
US20110133820A1 (en) * 2009-12-09 2011-06-09 Feng Pan Multi-Stage Charge Pump with Variable Number of Boosting Stages
US8339185B2 (en) 2010-12-20 2012-12-25 Sandisk 3D Llc Charge pump system that dynamically selects number of active stages
US8514628B2 (en) * 2011-09-22 2013-08-20 Sandisk Technologies Inc. Dynamic switching approach to reduce area and power consumption of high voltage charge pumps
US8710909B2 (en) 2012-09-14 2014-04-29 Sandisk Technologies Inc. Circuits for prevention of reverse leakage in Vth-cancellation charge pumps
US8836412B2 (en) 2013-02-11 2014-09-16 Sandisk 3D Llc Charge pump with a power-controlled clock buffer to reduce power consumption and output voltage ripple
US8981835B2 (en) 2013-06-18 2015-03-17 Sandisk Technologies Inc. Efficient voltage doubler
US9024680B2 (en) 2013-06-24 2015-05-05 Sandisk Technologies Inc. Efficiency for charge pumps with low supply voltages
US9077238B2 (en) 2013-06-25 2015-07-07 SanDisk Technologies, Inc. Capacitive regulation of charge pumps without refresh operation interruption
US9007046B2 (en) 2013-06-27 2015-04-14 Sandisk Technologies Inc. Efficient high voltage bias regulation circuit
US9083231B2 (en) 2013-09-30 2015-07-14 Sandisk Technologies Inc. Amplitude modulation for pass gate to improve charge pump efficiency
US9154027B2 (en) 2013-12-09 2015-10-06 Sandisk Technologies Inc. Dynamic load matching charge pump for reduced current consumption
US9917507B2 (en) 2015-05-28 2018-03-13 Sandisk Technologies Llc Dynamic clock period modulation scheme for variable charge pump load currents
US9647536B2 (en) 2015-07-28 2017-05-09 Sandisk Technologies Llc High voltage generation using low voltage devices
US9520776B1 (en) 2015-09-18 2016-12-13 Sandisk Technologies Llc Selective body bias for charge pump transfer switches

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5381366A (en) * 1989-04-11 1995-01-10 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor memory device with timer controlled re-write inhibit means
US5075890A (en) * 1989-05-02 1991-12-24 Kabushiki Kaisha Toshiba Electrically erasable programmable read-only memory with nand cell
JP2709751B2 (ja) * 1990-06-15 1998-02-04 三菱電機株式会社 不揮発性半導体記憶装置およびそのデータ消去方法
JP2917924B2 (ja) * 1996-07-30 1999-07-12 日本電気株式会社 不揮発性半導体記憶装置
US5729493A (en) * 1996-08-23 1998-03-17 Motorola Inc. Memory suitable for operation at low power supply voltages and sense amplifier therefor
KR100258575B1 (ko) * 1997-12-30 2000-06-15 윤종용 노어형 반도체 메모리 장치 및 그 장치의 데이터 독출 방법

Also Published As

Publication number Publication date
US6385107B1 (en) 2002-05-07
ITMI992372A1 (it) 2001-05-12
ITMI992372A0 (it) 1999-11-12

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