IT1268123B1 - Fetta di materiale semiconduttore per la fabbricazione di dispositivi integrati e procedimento per la sua fabbricazione. - Google Patents

Fetta di materiale semiconduttore per la fabbricazione di dispositivi integrati e procedimento per la sua fabbricazione.

Info

Publication number
IT1268123B1
IT1268123B1 IT94TO000818A ITTO940818A IT1268123B1 IT 1268123 B1 IT1268123 B1 IT 1268123B1 IT 94TO000818 A IT94TO000818 A IT 94TO000818A IT TO940818 A ITTO940818 A IT TO940818A IT 1268123 B1 IT1268123 B1 IT 1268123B1
Authority
IT
Italy
Prior art keywords
slice
procedure
manufacture
manufacturing
semiconductor material
Prior art date
Application number
IT94TO000818A
Other languages
English (en)
Italian (it)
Inventor
Bruno Murari
Flavio Villa
Ubaldo Mastromatteo
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT94TO000818A priority Critical patent/IT1268123B1/it
Publication of ITTO940818A0 publication Critical patent/ITTO940818A0/it
Priority to EP94830577A priority patent/EP0707338A2/en
Priority to US08/571,806 priority patent/US5855693A/en
Priority to JP7327021A priority patent/JP2680801B2/ja
Publication of ITTO940818A1 publication Critical patent/ITTO940818A1/it
Application granted granted Critical
Publication of IT1268123B1 publication Critical patent/IT1268123B1/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
IT94TO000818A 1994-10-13 1994-10-13 Fetta di materiale semiconduttore per la fabbricazione di dispositivi integrati e procedimento per la sua fabbricazione. IT1268123B1 (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT94TO000818A IT1268123B1 (it) 1994-10-13 1994-10-13 Fetta di materiale semiconduttore per la fabbricazione di dispositivi integrati e procedimento per la sua fabbricazione.
EP94830577A EP0707338A2 (en) 1994-10-13 1994-12-15 Wafer of semiconductor material for fabricating integrated semiconductor devices, and process for its fabrication
US08/571,806 US5855693A (en) 1994-10-13 1995-12-13 Wafer of semiconductor material for fabricating integrated devices, and process for its fabrication
JP7327021A JP2680801B2 (ja) 1994-10-13 1995-12-15 集積装置を製造するための半導体材料のウェハ、およびその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT94TO000818A IT1268123B1 (it) 1994-10-13 1994-10-13 Fetta di materiale semiconduttore per la fabbricazione di dispositivi integrati e procedimento per la sua fabbricazione.

Publications (3)

Publication Number Publication Date
ITTO940818A0 ITTO940818A0 (it) 1994-10-13
ITTO940818A1 ITTO940818A1 (it) 1996-04-13
IT1268123B1 true IT1268123B1 (it) 1997-02-20

Family

ID=11412833

Family Applications (1)

Application Number Title Priority Date Filing Date
IT94TO000818A IT1268123B1 (it) 1994-10-13 1994-10-13 Fetta di materiale semiconduttore per la fabbricazione di dispositivi integrati e procedimento per la sua fabbricazione.

Country Status (4)

Country Link
US (1) US5855693A (https=)
EP (1) EP0707338A2 (https=)
JP (1) JP2680801B2 (https=)
IT (1) IT1268123B1 (https=)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0720223B1 (en) * 1994-12-30 2003-03-26 STMicroelectronics S.r.l. Process for the production of a semiconductor device having better interface adhesion between dielectric layers
US6045625A (en) * 1996-12-06 2000-04-04 Texas Instruments Incorporated Buried oxide with a thermal expansion matching layer for SOI
FR2767605B1 (fr) * 1997-08-25 2001-05-11 Gec Alsthom Transport Sa Circuit integre de puissance, procede de fabrication d'un tel circuit et convertisseur incluant un tel circuit
US6194290B1 (en) * 1998-03-09 2001-02-27 Intersil Corporation Methods for making semiconductor devices by low temperature direct bonding
FR2781082B1 (fr) * 1998-07-10 2002-09-20 Commissariat Energie Atomique Structure semiconductrice en couche mince comportant une couche de repartition de chaleur
US20020089016A1 (en) 1998-07-10 2002-07-11 Jean-Pierre Joly Thin layer semi-conductor structure comprising a heat distribution layer
US6320206B1 (en) * 1999-02-05 2001-11-20 Lumileds Lighting, U.S., Llc Light emitting devices having wafer bonded aluminum gallium indium nitride structures and mirror stacks
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6500694B1 (en) * 2000-03-22 2002-12-31 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6166411A (en) * 1999-10-25 2000-12-26 Advanced Micro Devices, Inc. Heat removal from SOI devices by using metal substrates
US6476446B2 (en) 2000-01-03 2002-11-05 Advanced Micro Devices, Inc. Heat removal by removal of buried oxide in isolation areas
US6552395B1 (en) * 2000-01-03 2003-04-22 Advanced Micro Devices, Inc. Higher thermal conductivity glass for SOI heat removal
US6613643B1 (en) 2000-01-28 2003-09-02 Advanced Micro Devices, Inc. Structure, and a method of realizing, for efficient heat removal on SOI
US6635552B1 (en) 2000-06-12 2003-10-21 Micron Technology, Inc. Methods of forming semiconductor constructions
WO2002015244A2 (en) * 2000-08-16 2002-02-21 Massachusetts Institute Of Technology Process for producing semiconductor article using graded expitaxial growth
US6429070B1 (en) 2000-08-30 2002-08-06 Micron Technology, Inc. DRAM cell constructions, and methods of forming DRAM cells
US6940089B2 (en) * 2001-04-04 2005-09-06 Massachusetts Institute Of Technology Semiconductor device structure
US6717212B2 (en) * 2001-06-12 2004-04-06 Advanced Micro Devices, Inc. Leaky, thermally conductive insulator material (LTCIM) in semiconductor-on-insulator (SOI) structure
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US20030227057A1 (en) * 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US7608927B2 (en) * 2002-08-29 2009-10-27 Micron Technology, Inc. Localized biasing for silicon on insulator structures
US6989314B2 (en) * 2003-02-12 2006-01-24 S.O.I.Tec Silicon On Insulator Technologies S.A. Semiconductor structure and method of making same
FR2851079B1 (fr) * 2003-02-12 2005-08-26 Soitec Silicon On Insulator Structure semi-conductrice sur substrat a forte rugosite
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
DE10326578B4 (de) 2003-06-12 2006-01-19 Siltronic Ag Verfahren zur Herstellung einer SOI-Scheibe
DE102004053016A1 (de) * 2004-11-03 2006-05-04 Atmel Germany Gmbh Halbleiteranordnung und Verfahren zur Herstellung einer Halbleiteranordnung
JP2006173349A (ja) * 2004-12-15 2006-06-29 Sony Corp 固体撮像素子の製造方法及び固体撮像素子
JP2007012897A (ja) * 2005-06-30 2007-01-18 Nec Electronics Corp 半導体装置およびその製造方法
WO2008078132A1 (en) * 2006-12-26 2008-07-03 S.O.I.Tec Silicon On Insulator Technologies Method for producing a semiconductor-on-insulator structure
US7781256B2 (en) * 2007-05-31 2010-08-24 Chien-Min Sung Semiconductor-on-diamond devices and associated methods
US9390974B2 (en) 2012-12-21 2016-07-12 Qualcomm Incorporated Back-to-back stacked integrated circuit assembly and method of making
US9466719B2 (en) 2009-07-15 2016-10-11 Qualcomm Incorporated Semiconductor-on-insulator with back side strain topology
CN105097712A (zh) * 2009-07-15 2015-11-25 斯兰纳半导体美国股份有限公司 具有背侧散热的绝缘体上半导体
GB2483702A (en) * 2010-09-17 2012-03-21 Ge Aviat Systems Ltd Method for the manufacture of a Silicon Carbide, Silicon Oxide interface having reduced interfacial carbon gettering
FR2967812B1 (fr) * 2010-11-19 2016-06-10 S O I Tec Silicon On Insulator Tech Dispositif electronique pour applications radiofrequence ou de puissance et procede de fabrication d'un tel dispositif
KR20140118984A (ko) * 2011-11-04 2014-10-08 더 실라나 그룹 피티와이 리미티드 실리콘-온-인슐레이터 물품 제조방법
US20140319612A1 (en) * 2011-11-07 2014-10-30 The Silanna Group Pty Ltd Semiconductor-on-insulator structure and process for producing same
WO2013094665A1 (ja) 2011-12-22 2013-06-27 信越化学工業株式会社 複合基板
US8741739B2 (en) 2012-01-03 2014-06-03 International Business Machines Corporation High resistivity silicon-on-insulator substrate and method of forming
US9231063B2 (en) 2014-02-24 2016-01-05 International Business Machines Corporation Boron rich nitride cap for total ionizing dose mitigation in SOI devices
CN106489187B (zh) * 2014-07-10 2019-10-25 株式会社希克斯 半导体基板和半导体基板的制造方法
US20180026102A1 (en) * 2015-02-18 2018-01-25 The University Of Warwick Power semiconductor device
FR3079662B1 (fr) * 2018-03-30 2020-02-28 Soitec Substrat pour applications radiofrequences et procede de fabrication associe
WO2022094587A1 (en) 2020-10-29 2022-05-05 Invensas Bonding Technologies, Inc. Direct bonding methods and structures

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0665210B2 (ja) * 1985-04-17 1994-08-22 日本電気株式会社 基板の製造方法
SE465492B (sv) * 1990-01-24 1991-09-16 Asea Brown Boveri Halvledarkomponent innehaallande ett diamantskikt som aer anordnat mellan ett substrat och ett aktivt skikt och foerfarande foer dess framstaellning
WO1993001617A1 (en) * 1991-07-08 1993-01-21 Asea Brown Boveri Ab Method for the manufacture of a semiconductor component
US5276338A (en) * 1992-05-15 1994-01-04 International Business Machines Corporation Bonded wafer structure having a buried insulation layer
US5413952A (en) * 1994-02-02 1995-05-09 Motorola, Inc. Direct wafer bonded structure method of making

Also Published As

Publication number Publication date
EP0707338A3 (https=) 1996-05-15
JP2680801B2 (ja) 1997-11-19
JPH0927604A (ja) 1997-01-28
EP0707338A2 (en) 1996-04-17
ITTO940818A0 (it) 1994-10-13
US5855693A (en) 1999-01-05
ITTO940818A1 (it) 1996-04-13

Similar Documents

Publication Publication Date Title
IT1268123B1 (it) Fetta di materiale semiconduttore per la fabbricazione di dispositivi integrati e procedimento per la sua fabbricazione.
EP1039556A4 (en) THERMOELECTRIC TRANSMISSION MATERIAL AND ITS MANUFACTURE
KR950034612A (ko) 반도체 구조물 및 그 제조 방법
IT1243393B (it) Materiale stratificato per elementi di scorrimento e procedimento per la sua fabbricazione.
EP0676814A3 (en) Semiconductor device with a groove and manufacturing method.
DE69429668D1 (de) Poröses halbleitermaterial
DE69526543D1 (de) Harzvergossenes Halbleiterbauteil und dessen Herstellungsverfahren
DE69009409D1 (de) Halbleiter-Heterostrukturen.
DE69920640D1 (de) Nitrid-Halbleiterlaser und dessen Herstellungsverfahren
DE69504262D1 (de) Halbleiterlaser und dessen Herstellungsverfahren
DE69801342D1 (de) Halbleiterlaser und dazugehöriges Herstellungsverfahren
IT1297302B1 (it) Procedimento per la realizzazione di calzature e calzatura ottenuta con detto procedimento
ITRM940285A0 (it) "procedimento e dispositivo per la frantumazione di materiale semiconduttore".
FR2708789B1 (fr) Matériau semi-conducteur thermoélectrique.
IT1290599B1 (it) Procedimento per il trattamento di un materiale semiconduttore
DE69500392D1 (de) Halbleiterlasergerät und dessen Herstellungsverfahren
ITMI981992A0 (it) Materiale e procedimento per la sua fabbricazione
DE69511921D1 (de) Thermoelektrisches Halbleitermaterial
KR960025445U (ko) 반도체 제조용 언로더
DE59900014D1 (de) Klassieren von Halbleitermaterial
SK1835U (sk) Oblátkový ovocný rez
KR970046769U (ko) 반도체 제조장비의 몰딩 및 성형장치
KR960025515U (ko) 반도체 제조용 리드프레임
KR960003105U (ko) 반도체금형의 펀치
IT9083355A0 (it) Materiale abrasivo e metodo di realizzazione

Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19971030