IT1250406B - Circuito logico cmos per alta tensione con porte logiche configurate nand e ridotto numero di transistori n-mos richiedenti una diffusione graduata limitatamente al solo drain - Google Patents
Circuito logico cmos per alta tensione con porte logiche configurate nand e ridotto numero di transistori n-mos richiedenti una diffusione graduata limitatamente al solo drainInfo
- Publication number
- IT1250406B IT1250406B ITVA910006A ITVA910006A IT1250406B IT 1250406 B IT1250406 B IT 1250406B IT VA910006 A ITVA910006 A IT VA910006A IT VA910006 A ITVA910006 A IT VA910006A IT 1250406 B IT1250406 B IT 1250406B
- Authority
- IT
- Italy
- Prior art keywords
- mos transistors
- drain
- logic circuit
- graduated
- high voltage
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
- H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/0033—Radiation hardening
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
In un circuito logico CMOS destinato ad operare ad una tensione di alimentazione tale da richiedere la formazione di diffusioni graduate nei transistori N-MOS viene adottata una configurazione NAND comprendente due transistori N-MOS collegati in cascata tra loro. In questo modo è possibile ridurre il numero di diffusioni graduate da realizzare nelle strutture N-MOS alle sole giunzioni di drain direttamente collegate al nodo di uscita di ciascuna porta del circuito. In logiche CMOS sincronizzate, impieganti transistori di trasferimento tra porta e porta, i vantaggi che si ottengono sono ragguardevoli, in termini di velocizzazione del circuito ed in termini di maggiore compattabilità del circuito logico in virtù dell'eliminazione di un gran numero di strutture N-MOS necessariamente fornite di Drain Extension.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ITVA910006A IT1250406B (it) | 1991-02-07 | 1991-02-07 | Circuito logico cmos per alta tensione con porte logiche configurate nand e ridotto numero di transistori n-mos richiedenti una diffusione graduata limitatamente al solo drain |
EP92830071A EP0501929B1 (en) | 1991-02-07 | 1992-02-20 | High voltage CMOS circuit with nand configurated logic gates and a reduced number of N-MOS transistors requiring drain extension |
DE69215928T DE69215928T2 (de) | 1991-02-07 | 1992-02-20 | CMOS-Schaltung für hohe Spannungen mit NAND-Logik-Gattern und einer reduzierten Anzahl von N-MOS-Transistoren die eine Drain-Ausdehnung benötigen |
US07/841,621 US5311073A (en) | 1991-02-07 | 1992-02-25 | High voltage CMOS circuit with NAND configured logic gates and a reduced number of N-MOS transistors requiring drain extension |
JP4073485A JPH07169847A (ja) | 1991-02-07 | 1992-02-25 | Nandコンフィギュレーションの論理ゲート、及びドレンエクステンションを必要とする少数のnmosトランジスタを有する高電圧cmos回路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ITVA910006A IT1250406B (it) | 1991-02-07 | 1991-02-07 | Circuito logico cmos per alta tensione con porte logiche configurate nand e ridotto numero di transistori n-mos richiedenti una diffusione graduata limitatamente al solo drain |
Publications (3)
Publication Number | Publication Date |
---|---|
ITVA910006A0 ITVA910006A0 (it) | 1991-02-07 |
ITVA910006A1 ITVA910006A1 (it) | 1992-08-08 |
IT1250406B true IT1250406B (it) | 1995-04-07 |
Family
ID=11423113
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ITVA910006A IT1250406B (it) | 1991-02-07 | 1991-02-07 | Circuito logico cmos per alta tensione con porte logiche configurate nand e ridotto numero di transistori n-mos richiedenti una diffusione graduata limitatamente al solo drain |
Country Status (5)
Country | Link |
---|---|
US (1) | US5311073A (it) |
EP (1) | EP0501929B1 (it) |
JP (1) | JPH07169847A (it) |
DE (1) | DE69215928T2 (it) |
IT (1) | IT1250406B (it) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6023186A (en) * | 1996-04-30 | 2000-02-08 | Kabushiki Kaisha Toshiba | CMOS integrated circuit device and inspection method thereof |
US7504861B2 (en) * | 2003-11-20 | 2009-03-17 | Transpacific Ip, Ltd. | Input stage for mixed-voltage-tolerant buffer with reduced leakage |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4429237A (en) * | 1981-03-20 | 1984-01-31 | International Business Machines Corp. | High voltage on chip FET driver |
JPS60169219A (ja) * | 1984-02-13 | 1985-09-02 | Oki Electric Ind Co Ltd | 三状態出力回路 |
FR2571178B1 (fr) * | 1984-09-28 | 1986-11-21 | Thomson Csf | Structure de circuit integre comportant des transistors cmos a tenue en tension elevee, et son procede de fabrication |
JPH0738417B2 (ja) * | 1986-06-05 | 1995-04-26 | 株式会社東芝 | 絶縁ゲ−ト型半導体装置およびその製造方法 |
US5016077A (en) * | 1985-08-26 | 1991-05-14 | Kabushiki Kaisha Toshiba | Insulated gate type semiconductor device and method of manufacturing the same |
DE3821644A1 (de) * | 1987-12-23 | 1989-12-28 | Siemens Ag | Integrierte schaltung mit "latch-up"-schutzschaltung in komplementaerer mos-schaltungstechnik |
US4922327A (en) * | 1987-12-24 | 1990-05-01 | University Of Toronto Innovations Foundation | Semiconductor LDMOS device with upper and lower passages |
DE4020478C2 (de) * | 1989-07-04 | 2001-03-29 | Fuji Electric Co Ltd | Mos Halbleitervorrichtung |
JPH03104169A (ja) * | 1989-09-18 | 1991-05-01 | Mitsubishi Electric Corp | 半導体装置 |
DE69118214T2 (de) * | 1990-01-23 | 1996-10-31 | Nec Corp | Digitaler Halbleiterschaltkreis |
US5170078A (en) * | 1990-10-22 | 1992-12-08 | Gould Inc. | Highly stable high-voltage output buffer using CMOS technology |
-
1991
- 1991-02-07 IT ITVA910006A patent/IT1250406B/it active IP Right Grant
-
1992
- 1992-02-20 EP EP92830071A patent/EP0501929B1/en not_active Expired - Lifetime
- 1992-02-20 DE DE69215928T patent/DE69215928T2/de not_active Expired - Fee Related
- 1992-02-25 US US07/841,621 patent/US5311073A/en not_active Expired - Lifetime
- 1992-02-25 JP JP4073485A patent/JPH07169847A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
US5311073A (en) | 1994-05-10 |
EP0501929B1 (en) | 1996-12-18 |
EP0501929A2 (en) | 1992-09-02 |
JPH07169847A (ja) | 1995-07-04 |
DE69215928D1 (de) | 1997-01-30 |
ITVA910006A1 (it) | 1992-08-08 |
EP0501929A3 (en) | 1993-02-24 |
ITVA910006A0 (it) | 1991-02-07 |
DE69215928T2 (de) | 1997-06-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
0001 | Granted | ||
TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970227 |