GB1341334A - Static bipolar to mos interface circuit - Google Patents

Static bipolar to mos interface circuit

Info

Publication number
GB1341334A
GB1341334A GB2131872A GB2131872A GB1341334A GB 1341334 A GB1341334 A GB 1341334A GB 2131872 A GB2131872 A GB 2131872A GB 2131872 A GB2131872 A GB 2131872A GB 1341334 A GB1341334 A GB 1341334A
Authority
GB
United Kingdom
Prior art keywords
diffusions
interface circuit
mos interface
static bipolar
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2131872A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsystems International Ltd
Original Assignee
Microsystems International Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CA116959A external-priority patent/CA918757A/en
Application filed by Microsystems International Ltd filed Critical Microsystems International Ltd
Publication of GB1341334A publication Critical patent/GB1341334A/en
Priority claimed from CA218,493A external-priority patent/CA1057331A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

1341334 Integrated circuits MICROSYSTEMS INTERNATIONAL Ltd 8 May 1972 [21 July 1971 17 Jan 1972] 21318/72 Heading H1K [Also in Division H3] Two F.E.T.'s T1, T2, have drain impedances which may be further F.E.T.'s T3, T4. In the integrated circuit F.E.T.'s T1, T2 have drain and source regions D1, S1, D2, S2 formed of P-diffusions, and gate regions G1, G2 of polysilicon deposited over the P-diffusions. Metallization forms interconnections. T3, T4 consist of P-diffusions 12, 13 extending between supply line metallization V DD , V SS , and their gates G3, G4 are polysilicon deposits.
GB2131872A 1971-06-29 1972-05-08 Static bipolar to mos interface circuit Expired GB1341334A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CA116959A CA918757A (en) 1972-01-17 1971-06-29 Bipolar to mos interface circuit
US21849472A 1972-01-17 1972-01-17
CA218,493A CA1057331A (en) 1974-02-07 1975-01-23 Aspirated vehicle occupant restraint system

Publications (1)

Publication Number Publication Date
GB1341334A true GB1341334A (en) 1973-12-19

Family

ID=27161283

Family Applications (2)

Application Number Title Priority Date Filing Date
GB2131972A Expired GB1388629A (en) 1971-06-29 1972-05-08 Bipolar to mos interface circuit
GB2131872A Expired GB1341334A (en) 1971-06-29 1972-05-08 Static bipolar to mos interface circuit

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GB2131972A Expired GB1388629A (en) 1971-06-29 1972-05-08 Bipolar to mos interface circuit

Country Status (3)

Country Link
DE (1) DE2231203A1 (en)
FR (1) FR2144361A5 (en)
GB (2) GB1388629A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0043489A1 (en) * 1980-07-09 1982-01-13 Siemens Aktiengesellschaft Switch with series-connected MOSFETs

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5759689B2 (en) * 1974-09-30 1982-12-16 Citizen Watch Co Ltd

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0043489A1 (en) * 1980-07-09 1982-01-13 Siemens Aktiengesellschaft Switch with series-connected MOSFETs

Also Published As

Publication number Publication date
FR2144361A5 (en) 1973-02-09
GB1388629A (en) 1975-03-26
DE2231203A1 (en) 1973-01-25

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees