IT1237894B - Processo per la fabbricazione di circuiti integrati comprendenti componenti elettronici di due tipi diversi aventi ciascuno coppie di elettrodi ricavati dagli stessi strati di silicio policristallino e separati da dielettrici diversi - Google Patents

Processo per la fabbricazione di circuiti integrati comprendenti componenti elettronici di due tipi diversi aventi ciascuno coppie di elettrodi ricavati dagli stessi strati di silicio policristallino e separati da dielettrici diversi

Info

Publication number
IT1237894B
IT1237894B IT02268389A IT2268389A IT1237894B IT 1237894 B IT1237894 B IT 1237894B IT 02268389 A IT02268389 A IT 02268389A IT 2268389 A IT2268389 A IT 2268389A IT 1237894 B IT1237894 B IT 1237894B
Authority
IT
Italy
Prior art keywords
manufacture
pair
separated
electronic components
integrated circuits
Prior art date
Application number
IT02268389A
Other languages
English (en)
Other versions
IT8922683A0 (it
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT02268389A priority Critical patent/IT1237894B/it
Publication of IT8922683A0 publication Critical patent/IT8922683A0/it
Priority to JP40965490A priority patent/JP3199388B2/ja
Priority to KR1019900020410A priority patent/KR0179360B1/ko
Priority to US07/625,764 priority patent/US5075246A/en
Priority to DE69023469T priority patent/DE69023469T2/de
Priority to EP90313667A priority patent/EP0435534B1/en
Application granted granted Critical
Publication of IT1237894B publication Critical patent/IT1237894B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/014—Capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Non-Volatile Memory (AREA)
IT02268389A 1989-12-14 1989-12-14 Processo per la fabbricazione di circuiti integrati comprendenti componenti elettronici di due tipi diversi aventi ciascuno coppie di elettrodi ricavati dagli stessi strati di silicio policristallino e separati da dielettrici diversi IT1237894B (it)

Priority Applications (6)

Application Number Priority Date Filing Date Title
IT02268389A IT1237894B (it) 1989-12-14 1989-12-14 Processo per la fabbricazione di circuiti integrati comprendenti componenti elettronici di due tipi diversi aventi ciascuno coppie di elettrodi ricavati dagli stessi strati di silicio policristallino e separati da dielettrici diversi
JP40965490A JP3199388B2 (ja) 1989-12-14 1990-12-11 集積回路の製造方法
KR1019900020410A KR0179360B1 (ko) 1989-12-14 1990-12-12 유전물질에 의해 분리되어 있는 전극쌍이 포함된 다양한 소자를 구비한 집적회로의 제조방법
US07/625,764 US5075246A (en) 1989-12-14 1990-12-13 Method of manufacturing integrated circuits having electronic components of two different types each having pairs of electrodes obtained from the same polycrystalline silicon layers and separated by different dielectric materials
DE69023469T DE69023469T2 (de) 1989-12-14 1990-12-14 Integrierte Schaltung und Herstellungsverfahren dafür.
EP90313667A EP0435534B1 (en) 1989-12-14 1990-12-14 Method of manufacturing integrated circuit and integrated circuit made thereby

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT02268389A IT1237894B (it) 1989-12-14 1989-12-14 Processo per la fabbricazione di circuiti integrati comprendenti componenti elettronici di due tipi diversi aventi ciascuno coppie di elettrodi ricavati dagli stessi strati di silicio policristallino e separati da dielettrici diversi

Publications (2)

Publication Number Publication Date
IT8922683A0 IT8922683A0 (it) 1989-12-14
IT1237894B true IT1237894B (it) 1993-06-18

Family

ID=11199229

Family Applications (1)

Application Number Title Priority Date Filing Date
IT02268389A IT1237894B (it) 1989-12-14 1989-12-14 Processo per la fabbricazione di circuiti integrati comprendenti componenti elettronici di due tipi diversi aventi ciascuno coppie di elettrodi ricavati dagli stessi strati di silicio policristallino e separati da dielettrici diversi

Country Status (6)

Country Link
US (1) US5075246A (it)
EP (1) EP0435534B1 (it)
JP (1) JP3199388B2 (it)
KR (1) KR0179360B1 (it)
DE (1) DE69023469T2 (it)
IT (1) IT1237894B (it)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05283710A (ja) * 1991-12-06 1993-10-29 Intel Corp 高電圧ｍｏｓトランジスタ及びその製造方法
EP0557937A1 (en) * 1992-02-25 1993-09-01 Ramtron International Corporation Ozone gas processing for ferroelectric memory circuits
US5340764A (en) * 1993-02-19 1994-08-23 Atmel Corporation Integration of high performance submicron CMOS and dual-poly non-volatile memory devices using a third polysilicon layer
JPH06252345A (ja) * 1993-03-02 1994-09-09 Nec Corp 半導体集積回路の製造方法
US5550072A (en) * 1994-08-30 1996-08-27 National Semiconductor Corporation Method of fabrication of integrated circuit chip containing EEPROM and capacitor
DE19531629C1 (de) * 1995-08-28 1997-01-09 Siemens Ag Verfahren zur Herstellung einer EEPROM-Halbleiterstruktur
JP3415712B2 (ja) 1995-09-19 2003-06-09 松下電器産業株式会社 半導体装置及びその製造方法
US5731236A (en) * 1997-05-05 1998-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Process to integrate a self-aligned contact structure, with a capacitor structure
JP3556079B2 (ja) * 1997-10-02 2004-08-18 旭化成マイクロシステム株式会社 半導体装置の製造方法
DE19983274B4 (de) 1999-04-01 2004-10-28 Asahi Kasei Microsystems Co., Ltd. Verfahren zum Herstellen eines nichtflüchtigen Halbleiterspeicherbauteils
US8936838B2 (en) 2012-01-16 2015-01-20 Corning Incorporated Method for coating polymers on glass edges
FR3059148B1 (fr) * 2016-11-23 2019-09-06 Commissariat A L'energie Atomique Et Aux Energies Alternatives Realisation d'elements d'interconnexions auto-alignes pour circuit integre 3d

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4441249A (en) * 1982-05-26 1984-04-10 Bell Telephone Laboratories, Incorporated Semiconductor integrated circuit capacitor
US4536947A (en) * 1983-07-14 1985-08-27 Intel Corporation CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors
US4639274A (en) * 1984-11-28 1987-01-27 Fairchild Semiconductor Corporation Method of making precision high-value MOS capacitors
JPS61183952A (ja) * 1985-02-09 1986-08-16 Fujitsu Ltd 半導体記憶装置及びその製造方法
US4971924A (en) * 1985-05-01 1990-11-20 Texas Instruments Incorporated Metal plate capacitor and method for making the same
FR2583920B1 (fr) * 1985-06-21 1987-07-31 Commissariat Energie Atomique Procede de fabrication d'un circuit integre et notamment d'une memoire eprom comportant deux composants distincts isoles electriquement
IT1208646B (it) * 1987-06-11 1989-07-10 Sgs Mocroelettronica S P A Fasi di mascherature. procedimento per la fabbricazione di condensatori in processi cmos e nmos con riduzione del numero di
IT1224656B (it) * 1987-12-23 1990-10-18 Sgs Thomson Microelectronics Procedimento per la fabbricazione di condensatori integrati in tecnologia mos.
FR2642900B1 (fr) * 1989-01-17 1991-05-10 Sgs Thomson Microelectronics Procede de fabrication de circuits integres a transistors de memoire eprom et a transistors logiques

Also Published As

Publication number Publication date
JPH04119666A (ja) 1992-04-21
JP3199388B2 (ja) 2001-08-20
DE69023469D1 (de) 1995-12-14
EP0435534B1 (en) 1995-11-08
KR0179360B1 (ko) 1999-03-20
IT8922683A0 (it) 1989-12-14
EP0435534A3 (en) 1991-11-06
EP0435534A2 (en) 1991-07-03
KR910013571A (ko) 1991-08-08
DE69023469T2 (de) 1996-05-02
US5075246A (en) 1991-12-24

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Effective date: 19961227