IT1208646B - Fasi di mascherature. procedimento per la fabbricazione di condensatori in processi cmos e nmos con riduzione del numero di - Google Patents

Fasi di mascherature. procedimento per la fabbricazione di condensatori in processi cmos e nmos con riduzione del numero di

Info

Publication number
IT1208646B
IT1208646B IT8720879A IT2087987A IT1208646B IT 1208646 B IT1208646 B IT 1208646B IT 8720879 A IT8720879 A IT 8720879A IT 2087987 A IT2087987 A IT 2087987A IT 1208646 B IT1208646 B IT 1208646B
Authority
IT
Italy
Prior art keywords
capacitors
manufacture
cmos
procedure
reduction
Prior art date
Application number
IT8720879A
Other languages
English (en)
Other versions
IT8720879A0 (it
Inventor
Stafano Mazzali
Original Assignee
Sgs Mocroelettronica S P A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Mocroelettronica S P A filed Critical Sgs Mocroelettronica S P A
Priority to IT8720879A priority Critical patent/IT1208646B/it
Publication of IT8720879A0 publication Critical patent/IT8720879A0/it
Priority to DE8888108774T priority patent/DE3874416T2/de
Priority to EP88108774A priority patent/EP0294699B1/en
Priority to JP63144560A priority patent/JPS63318149A/ja
Application granted granted Critical
Publication of IT1208646B publication Critical patent/IT1208646B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
IT8720879A 1987-06-11 1987-06-11 Fasi di mascherature. procedimento per la fabbricazione di condensatori in processi cmos e nmos con riduzione del numero di IT1208646B (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT8720879A IT1208646B (it) 1987-06-11 1987-06-11 Fasi di mascherature. procedimento per la fabbricazione di condensatori in processi cmos e nmos con riduzione del numero di
DE8888108774T DE3874416T2 (de) 1987-06-11 1988-06-01 Verfahren zum herstellen von kondensatoren bei cmos- und nmos-verfahren.
EP88108774A EP0294699B1 (en) 1987-06-11 1988-06-01 Method for making capacitors in cmos and nmos processes
JP63144560A JPS63318149A (ja) 1987-06-11 1988-06-10 Ｃｍｏｓおよびｎｍｏｓプロセスでコンデンサを作るための方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8720879A IT1208646B (it) 1987-06-11 1987-06-11 Fasi di mascherature. procedimento per la fabbricazione di condensatori in processi cmos e nmos con riduzione del numero di

Publications (2)

Publication Number Publication Date
IT8720879A0 IT8720879A0 (it) 1987-06-11
IT1208646B true IT1208646B (it) 1989-07-10

Family

ID=11173449

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8720879A IT1208646B (it) 1987-06-11 1987-06-11 Fasi di mascherature. procedimento per la fabbricazione di condensatori in processi cmos e nmos con riduzione del numero di

Country Status (4)

Country Link
EP (1) EP0294699B1 (it)
JP (1) JPS63318149A (it)
DE (1) DE3874416T2 (it)
IT (1) IT1208646B (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1237894B (it) * 1989-12-14 1993-06-18 Sgs Thomson Microelectronics Processo per la fabbricazione di circuiti integrati comprendenti componenti elettronici di due tipi diversi aventi ciascuno coppie di elettrodi ricavati dagli stessi strati di silicio policristallino e separati da dielettrici diversi
DE19528991C2 (de) 1995-08-07 2002-05-16 Infineon Technologies Ag Herstellungsverfahren für eine nichtflüchtige Speicherzelle
WO2001061644A1 (en) * 2000-02-14 2001-08-23 Koninklijke Philips Electronics N.V. Transponder and appliance

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4577390A (en) * 1983-02-23 1986-03-25 Texas Instruments Incorporated Fabrication of polysilicon to polysilicon capacitors with a composite dielectric layer

Also Published As

Publication number Publication date
EP0294699B1 (en) 1992-09-09
IT8720879A0 (it) 1987-06-11
DE3874416T2 (de) 1993-03-25
JPS63318149A (ja) 1988-12-27
DE3874416D1 (de) 1992-10-15
EP0294699A3 (en) 1989-09-06
EP0294699A2 (en) 1988-12-14

Similar Documents

Publication Publication Date Title
ATE27751T1 (de) Verfahren zum herstellen von hochintegrierten komplementaeren mosfeldeffekttransistorschaltungen.
ATE90477T1 (de) Verfahren zum herstellen von optimierten komplementaeren mos-feldeffekttransistoren in vlsi-technik.
FR2447095B1 (fr) Procede pour la fabrication de transistors mos complementaires a integration poussee pour tensions elevees
DE3175429D1 (en) Process for producing a monolithic integrated circuit having at least one pair of complementary field-effect transistors and at least one bipolar transistor
DE3789350D1 (de) Herstellungsverfahren zur Ausbildung eines MOS-Transistors durch Selbstausrichtung der Source/Drain-Gebiete.
ATE57586T1 (de) Verfahren zur herstellung eines bipolartransistors.
DE68904672D1 (de) Halbleiteranordnung, deren struktur die wirkung des parasitischen transistors erschwert und verfahren zur herstellung.
ATE24070T1 (de) Verfahren zum herstellen von hochintegrierten komplementaeren mosfeldeffekttransistorschaltungen in siliziumgate- technologie.
EP0183204A3 (en) Process for fabricating semiconductor integrated circuit devices
SE8103495L (sv) Framstellning av integrerade kretsar
DE3788438D1 (de) Methode zur Herstellung von integrierten elektronischen Vorrichtungen, insbesondere Hochspannungs-P-Kanal-MOS-Transistoren.
IT1208646B (it) Fasi di mascherature. procedimento per la fabbricazione di condensatori in processi cmos e nmos con riduzione del numero di
EP0301364A3 (en) Process for manufacturing cmos devices
JPS51130183A (en) Semiconductor ic and its process
JPS53112069A (en) Production of mis transistor
ATE150873T1 (de) Verfahren zur herstellung eines eine integrierte halbleiterschaltung und eine selbsttragende mikrostruktur enthaltenden monolithischen chip
EP0381237A3 (en) Integrated semiconductor circuit with p and n channel mos transistors
DE68911067D1 (de) Platin-(II)-diamin-Komplex, Verfahren zur Herstellung dieser Verbindung, Zusammensetzung mit Antitumorwirkung, die mindestens eine Platin-Verbindung enthält, und geformte Zusammensetzung mit Antitumorwirkung.
EP0690513A3 (en) Step-cut insulated gate static induction transistors and method of manufacturing the same
GB2011710A (en) Semiconductor structures
EP0181760A3 (en) A device comprising a pair of cmos fets and a method of making it
JPS55121666A (en) Mos transistor circuit
JPS6484636A (en) Manufacture of mos gate array
JPS6437033A (en) Manufacture of semiconductor integrated circuit device
JPS57149765A (en) Semiconductor integrated circuit device

Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970628