JPS6437033A - Manufacture of semiconductor integrated circuit device - Google Patents

Manufacture of semiconductor integrated circuit device

Info

Publication number
JPS6437033A
JPS6437033A JP19352587A JP19352587A JPS6437033A JP S6437033 A JPS6437033 A JP S6437033A JP 19352587 A JP19352587 A JP 19352587A JP 19352587 A JP19352587 A JP 19352587A JP S6437033 A JPS6437033 A JP S6437033A
Authority
JP
Japan
Prior art keywords
layer
mos transistors
gate
wiring
connecting part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19352587A
Other languages
Japanese (ja)
Inventor
Toshihiro Tsukagoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP19352587A priority Critical patent/JPS6437033A/en
Publication of JPS6437033A publication Critical patent/JPS6437033A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays

Abstract

PURPOSE:To contrive to improve the efficiency of a wiring by a method wherein a gate layer is patterned in a master process in such a way that a plurality of MOS transistors are connected to each other through the gate layer and after the gate layer, which is the unnecessary connecting part between the MOS transistors, is removed in a custom process, a metal wiring is executed. CONSTITUTION:A gate layer 2, which is the same layer as gate electrodes of MOS transistors, is patterned in a master process in such a way that the layer 2 is left at a region other than source and drain regions 8 and 10 and a plurality of the MOS transistors are connected to each other through the layer 2 and a connecting part 6 is left in such a way that the electrodes 4 are connected to each other. Then, after the layer 2, which is the unnecessary connecting part between the MOS transistors, is removed in a custom process, a metal wiring is executed. Therefore, as the form of the layer 2 of the transistors can be modified in the custom process as well, the freedom of a layout is increased and at the same time, the layer 2 can be utilized for the wiring in the interior of a logical gate call as well. Thereby, the efficiency of the wiring of a chip can be improved.
JP19352587A 1987-08-01 1987-08-01 Manufacture of semiconductor integrated circuit device Pending JPS6437033A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19352587A JPS6437033A (en) 1987-08-01 1987-08-01 Manufacture of semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19352587A JPS6437033A (en) 1987-08-01 1987-08-01 Manufacture of semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6437033A true JPS6437033A (en) 1989-02-07

Family

ID=16309523

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19352587A Pending JPS6437033A (en) 1987-08-01 1987-08-01 Manufacture of semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6437033A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0681740A1 (en) * 1993-07-01 1995-11-15 Lsi Logic Corporation Integrated circuit structure with programmable conductive electrode/interconnect material and method of making same
US5917207A (en) * 1993-07-01 1999-06-29 Lsi Logic Corporation Programmable polysilicon gate array base cell architecture

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0681740A1 (en) * 1993-07-01 1995-11-15 Lsi Logic Corporation Integrated circuit structure with programmable conductive electrode/interconnect material and method of making same
US5917207A (en) * 1993-07-01 1999-06-29 Lsi Logic Corporation Programmable polysilicon gate array base cell architecture

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