IT1114777B - Transistore ad effetto di campo perfezionato e processo per la fabbricazione di circuiti integrati contenenti una pluralita' di tali transistori - Google Patents

Transistore ad effetto di campo perfezionato e processo per la fabbricazione di circuiti integrati contenenti una pluralita' di tali transistori

Info

Publication number
IT1114777B
IT1114777B IT22495/77A IT2249577A IT1114777B IT 1114777 B IT1114777 B IT 1114777B IT 22495/77 A IT22495/77 A IT 22495/77A IT 2249577 A IT2249577 A IT 2249577A IT 1114777 B IT1114777 B IT 1114777B
Authority
IT
Italy
Prior art keywords
perfected
transistors
manufacture
field effect
effect transistor
Prior art date
Application number
IT22495/77A
Other languages
English (en)
Italian (it)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT1114777B publication Critical patent/IT1114777B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/671—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor having lateral variation in doping or structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/053—Field effect transistors fets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/103—Mask, dual function, e.g. diffusion and oxidation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/141—Self-alignment coat gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/147—Silicides

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
IT22495/77A 1976-05-14 1977-04-15 Transistore ad effetto di campo perfezionato e processo per la fabbricazione di circuiti integrati contenenti una pluralita' di tali transistori IT1114777B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US68696976A 1976-05-14 1976-05-14

Publications (1)

Publication Number Publication Date
IT1114777B true IT1114777B (it) 1986-01-27

Family

ID=24758498

Family Applications (1)

Application Number Title Priority Date Filing Date
IT22495/77A IT1114777B (it) 1976-05-14 1977-04-15 Transistore ad effetto di campo perfezionato e processo per la fabbricazione di circuiti integrati contenenti una pluralita' di tali transistori

Country Status (8)

Country Link
US (1) US4160987A (enExample)
JP (1) JPS52139389A (enExample)
BE (1) BE853547A (enExample)
CA (1) CA1082371A (enExample)
DE (1) DE2716691A1 (enExample)
FR (1) FR2351502A1 (enExample)
GB (1) GB1574872A (enExample)
IT (1) IT1114777B (enExample)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS583380B2 (ja) * 1977-03-04 1983-01-21 株式会社日立製作所 半導体装置とその製造方法
JPS53124084A (en) * 1977-04-06 1978-10-30 Hitachi Ltd Semiconductor memory device containing floating type poly silicon layer and its manufacture
US4282647A (en) * 1978-04-04 1981-08-11 Standard Microsystems Corporation Method of fabricating high density refractory metal gate MOS integrated circuits utilizing the gate as a selective diffusion and oxidation mask
US4192059A (en) * 1978-06-06 1980-03-11 Rockwell International Corporation Process for and structure of high density VLSI circuits, having inherently self-aligned gates and contacts for FET devices and conducting lines
US4221044A (en) * 1978-06-06 1980-09-09 Rockwell International Corporation Self-alignment of gate contacts at local or remote sites
US4231051A (en) * 1978-06-06 1980-10-28 Rockwell International Corporation Process for producing minimal geometry devices for VSLI applications utilizing self-aligned gates and self-aligned contacts, and resultant structures
US4268951A (en) * 1978-11-13 1981-05-26 Rockwell International Corporation Submicron semiconductor devices
US4304042A (en) * 1978-11-13 1981-12-08 Xerox Corporation Self-aligned MESFETs having reduced series resistance
US4277882A (en) * 1978-12-04 1981-07-14 Fairchild Camera And Instrument Corporation Method of producing a metal-semiconductor field-effect transistor
US4246592A (en) * 1979-01-02 1981-01-20 Texas Instruments Incorporated High density static memory cell
US4246593A (en) * 1979-01-02 1981-01-20 Texas Instruments Incorporated High density static memory cell with polysilicon resistors
US4317690A (en) * 1980-06-18 1982-03-02 Signetics Corporation Self-aligned double polysilicon MOS fabrication
US4397075A (en) * 1980-07-03 1983-08-09 International Business Machines Corporation FET Memory cell structure and process
US4329773A (en) * 1980-12-10 1982-05-18 International Business Machines Corp. Method of making low leakage shallow junction IGFET devices
EP0054102A3 (en) * 1980-12-11 1983-07-27 Rockwell International Corporation Very high density cells comprising a rom and method of manufacturing same
AT387474B (de) * 1980-12-23 1989-01-25 Philips Nv Verfahren zur herstellung einer halbleitervorrichtung
JPH01162351A (ja) * 1987-12-19 1989-06-26 Fujitsu Ltd 半導体装置の製造方法
JPH0448640A (ja) * 1990-06-14 1992-02-18 Oki Electric Ind Co Ltd Ｍｏｓトランジスタの製造方法
JPH06349820A (ja) * 1993-06-11 1994-12-22 Rohm Co Ltd 半導体装置の製造方法
US5543343A (en) * 1993-12-22 1996-08-06 Sgs-Thomson Microelectronics, Inc. Method fabricating an integrated circuit
US5927992A (en) * 1993-12-22 1999-07-27 Stmicroelectronics, Inc. Method of forming a dielectric in an integrated circuit
US5783366A (en) * 1995-12-07 1998-07-21 Taiwan Semiconductor Manufacturing Company Ltd. Method for eliminating charging of photoresist on specimens during scanning electron microscope examination
US5972776A (en) * 1995-12-22 1999-10-26 Stmicroelectronics, Inc. Method of forming a planar isolation structure in an integrated circuit
US5834360A (en) * 1996-07-31 1998-11-10 Stmicroelectronics, Inc. Method of forming an improved planar isolation structure in an integrated circuit
US6221715B1 (en) * 1998-07-28 2001-04-24 Winbond Electronics Corporation Method of making polysilicon self-aligned to field isolation oxide
US6265256B1 (en) * 1998-09-17 2001-07-24 Advanced Micro Devices, Inc. MOS transistor with minimal overlap between gate and source/drain extensions
JP2000223701A (ja) * 1999-01-28 2000-08-11 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP3940560B2 (ja) * 2001-01-25 2007-07-04 独立行政法人産業技術総合研究所 半導体装置の製造方法
US7259053B2 (en) * 2003-09-22 2007-08-21 Dongbu Electronics Co., Ltd. Methods for forming a device isolation structure in a semiconductor device
JP5444694B2 (ja) * 2008-11-12 2014-03-19 ソニー株式会社 固体撮像装置、その製造方法および撮像装置
WO2019161166A1 (en) 2018-02-16 2019-08-22 Avx Corporation Self-aligning capacitor electrode assembly having improved breakdown voltage

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL164424C (nl) * 1970-06-04 1980-12-15 Philips Nv Werkwijze voor het vervaardigen van een veldeffect- transistor met een geisoleerde stuurelektrode, waarbij een door een tegen oxydatie maskerende laag vrijgelaten deel van het oppervlak van een siliciumlichaam aan een oxydatiebehandeling wordt onderworpen ter verkrijging van een althans gedeeltelijk in het siliciumlichaam verzonken siliciumoxydelaag.
US3830657A (en) * 1971-06-30 1974-08-20 Ibm Method for making integrated circuit contact structure
US3811076A (en) * 1973-01-02 1974-05-14 Ibm Field effect transistor integrated circuit and memory
CA1001771A (en) * 1973-01-15 1976-12-14 Fairchild Camera And Instrument Corporation Method of mos transistor manufacture and resulting structure
US3936859A (en) * 1973-08-06 1976-02-03 Rca Corporation Semiconductor device including a conductor surrounded by an insulator
IN140846B (enExample) * 1973-08-06 1976-12-25 Rca Corp
JPS5075775A (enExample) * 1973-11-06 1975-06-21
US3958323A (en) * 1975-04-29 1976-05-25 International Business Machines Corporation Three mask self aligned IGFET fabrication process
JPS51145285A (en) * 1975-06-09 1976-12-14 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPS5291382A (en) * 1976-01-26 1977-08-01 Nec Corp Insulating gate type field effect transistor

Also Published As

Publication number Publication date
CA1082371A (en) 1980-07-22
US4160987A (en) 1979-07-10
GB1574872A (en) 1980-09-10
JPS52139389A (en) 1977-11-21
JPS571145B2 (enExample) 1982-01-09
FR2351502A1 (fr) 1977-12-09
FR2351502B1 (enExample) 1979-03-09
DE2716691A1 (de) 1977-12-01
BE853547A (fr) 1977-08-01

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