IN2014CN03050A - - Google Patents
Info
- Publication number
- IN2014CN03050A IN2014CN03050A IN3050CHN2014A IN2014CN03050A IN 2014CN03050 A IN2014CN03050 A IN 2014CN03050A IN 3050CHN2014 A IN3050CHN2014 A IN 3050CHN2014A IN 2014CN03050 A IN2014CN03050 A IN 2014CN03050A
- Authority
- IN
- India
- Prior art keywords
- optionally
- phase
- delay cells
- controlled oscillator
- voltage controlled
- Prior art date
Links
- 238000005070 sampling Methods 0.000 abstract 3
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
- H04L7/0276—Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
- H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Dc-Dc Converters (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201161560422P | 2011-11-16 | 2011-11-16 | |
| US13/363,410 US8847691B2 (en) | 2011-11-16 | 2012-02-01 | Apparatus and method for recovering burst-mode pulse width modulation (PWM) and non-return-to-zero (NRZ) data |
| PCT/US2012/065649 WO2013075009A2 (en) | 2011-11-16 | 2012-11-16 | Apparatus and method for recovering burst-mode pulse width modulation (pwm) and non-return-to-zero (nrz) data |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IN2014CN03050A true IN2014CN03050A (cg-RX-API-DMAC7.html) | 2015-07-03 |
Family
ID=48279993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IN3050CHN2014 IN2014CN03050A (cg-RX-API-DMAC7.html) | 2011-11-16 | 2012-11-16 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US8847691B2 (cg-RX-API-DMAC7.html) |
| EP (1) | EP2781025B1 (cg-RX-API-DMAC7.html) |
| JP (1) | JP5848460B2 (cg-RX-API-DMAC7.html) |
| KR (1) | KR101696320B1 (cg-RX-API-DMAC7.html) |
| CN (1) | CN103947116B (cg-RX-API-DMAC7.html) |
| IN (1) | IN2014CN03050A (cg-RX-API-DMAC7.html) |
| WO (1) | WO2013075009A2 (cg-RX-API-DMAC7.html) |
Families Citing this family (45)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI469522B (zh) * | 2011-01-06 | 2015-01-11 | Raydium Semiconductor Corp | 訊號電路 |
| JP2013055575A (ja) * | 2011-09-06 | 2013-03-21 | Elpida Memory Inc | 半導体装置及びこれを用いた情報処理システム |
| US8847691B2 (en) | 2011-11-16 | 2014-09-30 | Qualcomm Incorporated | Apparatus and method for recovering burst-mode pulse width modulation (PWM) and non-return-to-zero (NRZ) data |
| US8836390B2 (en) * | 2011-11-30 | 2014-09-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Phase-locked loops that share a loop filter and frequency divider |
| CN104540732B (zh) | 2012-02-09 | 2018-02-06 | 莫戈公司 | 致动器系统和方法 |
| KR101901321B1 (ko) * | 2012-06-01 | 2018-09-21 | 삼성전자주식회사 | 클럭 발생기 및 클럭 발생 방법 |
| US9356649B2 (en) * | 2012-12-14 | 2016-05-31 | Huawei Technologies Co., Ltd. | System and method for low density spreading modulation detection |
| JP6032082B2 (ja) * | 2013-03-25 | 2016-11-24 | 富士通株式会社 | 受信回路及び半導体集積回路 |
| KR102059467B1 (ko) * | 2013-06-28 | 2019-12-27 | 에스케이하이닉스 주식회사 | 반도체 장치 및 이를 포함하는 반도체 시스템 |
| CN104426565B (zh) * | 2013-09-10 | 2017-11-03 | 円星科技股份有限公司 | 数字接收器及其方法 |
| US9660800B2 (en) | 2013-11-06 | 2017-05-23 | Navitas Solutions | Fast data acquisition in digital communication |
| JP6294691B2 (ja) * | 2014-02-07 | 2018-03-14 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US9203391B2 (en) * | 2014-04-22 | 2015-12-01 | Qualcomm Incorporated | Pulse-width modulation data decoder |
| TWI572153B (zh) * | 2014-04-29 | 2017-02-21 | 立錡科技股份有限公司 | 單傳輸線傳輸介面與單傳輸線傳輸方法以及使用單傳輸線傳輸方法之電源供應系統 |
| FR3029661B1 (fr) * | 2014-12-04 | 2016-12-09 | Stmicroelectronics Rousset | Procedes de transmission et de reception d'un signal binaire sur un lien serie, en particulier pour la detection de la vitesse de transmission, et dispositifs correspondants |
| KR102299862B1 (ko) * | 2014-12-23 | 2021-09-08 | 삼성전자주식회사 | 신호 처리 장치 및 방법 |
| US9438255B1 (en) * | 2015-07-31 | 2016-09-06 | Inphi Corporation | High frequency delay lock loop systems |
| KR102295058B1 (ko) | 2015-08-19 | 2021-08-31 | 삼성전자주식회사 | 반도체 메모리 시스템 및 반도체 메모리 장치 및 반도체 메모리 장치의 동작방법 |
| CN105510937B (zh) * | 2015-11-27 | 2017-09-19 | 武汉梦芯科技有限公司 | 一种多模多频基带芯片管脚控制电路和控制方法 |
| CA3011439A1 (en) | 2016-01-13 | 2017-07-20 | Moog Inc. | Summing and fault tolerant rotary actuator assembly |
| CN107317581B (zh) * | 2016-04-26 | 2021-01-12 | 华邦电子股份有限公司 | 具有高分辨率的时间数字转换器 |
| US10158365B2 (en) | 2016-07-29 | 2018-12-18 | Movellus Circuits, Inc. | Digital, reconfigurable frequency and delay generator with phase measurement |
| US10254782B2 (en) * | 2016-08-30 | 2019-04-09 | Micron Technology, Inc. | Apparatuses for reducing clock path power consumption in low power dynamic random access memory |
| US10614182B2 (en) | 2016-10-19 | 2020-04-07 | Movellus Circuits, Inc. | Timing analysis for electronic design automation of parallel multi-state driver circuits |
| US11058889B1 (en) | 2017-04-03 | 2021-07-13 | Xiant Technologies, Inc. | Method of using photon modulation for regulation of hormones in mammals |
| US10498345B1 (en) * | 2017-06-30 | 2019-12-03 | Cadence Design Systems, Inc. | Multiple injection lock ring-based phase interpolator |
| WO2019028740A1 (en) * | 2017-08-10 | 2019-02-14 | Photonic Technologies (Shanghai) Co., Ltd. | CLOCK RECOVERY CIRCUIT AND DATA |
| US10740526B2 (en) | 2017-08-11 | 2020-08-11 | Movellus Circuits, Inc. | Integrated circuit design system with automatic timing margin reduction |
| EP3579219B1 (en) * | 2018-06-05 | 2022-03-16 | IMEC vzw | Data distribution for holographic projection |
| US11070215B2 (en) | 2018-06-13 | 2021-07-20 | Movellus Circuits, Inc. | Locked loop circuit and method with digitally-controlled oscillator (DCO) gain normalization |
| US11493950B2 (en) | 2018-06-13 | 2022-11-08 | Movellus Circuits, Inc. | Frequency counter circuit for detecting timing violations |
| US11496139B2 (en) | 2018-06-13 | 2022-11-08 | Movellus Circuits, Inc. | Frequency measurement circuit with adaptive accuracy |
| US10594323B2 (en) | 2018-06-13 | 2020-03-17 | Movellus Circuits, Inc. | Locked loop circuit and method with digitally-controlled oscillator (DCO) gain normalization |
| US11217298B2 (en) * | 2020-03-12 | 2022-01-04 | Micron Technology, Inc. | Delay-locked loop clock sharing |
| US11239849B2 (en) | 2020-04-06 | 2022-02-01 | Movellus Circuits Inc. | Locked loop circuit and method with multi-phase synchronization |
| JP7631122B2 (ja) * | 2021-06-23 | 2025-02-18 | キオクシア株式会社 | 半導体集積回路、半導体記憶装置、メモリシステム及び周波数発生方法 |
| US11509313B1 (en) * | 2021-12-03 | 2022-11-22 | Fujian Jinhua Integrated Circuit Co., Ltd. | Delay-locked loop circuit with multiple modes |
| US11716169B2 (en) | 2021-12-09 | 2023-08-01 | SK Hynix Inc. | Method for error handling of an interconnection protocol, controller, and storage device |
| CN114422064B (zh) * | 2021-12-15 | 2023-09-12 | 北京罗克维尔斯科技有限公司 | 报文转发方法及其装置 |
| US11831318B1 (en) | 2022-11-17 | 2023-11-28 | Movellus Circuits Inc. | Frequency multiplier system with multi-transition controller |
| US12368447B1 (en) | 2022-11-17 | 2025-07-22 | Movellus Circuits Inc. | Clock generator system with dynamic frequency crossover |
| US11979165B1 (en) | 2022-11-17 | 2024-05-07 | Movellus Circuits Inc. | Frequency multiplier circuit with programmable frequency transition controller |
| US12489447B2 (en) * | 2022-12-31 | 2025-12-02 | Advanced Micro Devices, Inc. | Multi-phase clock gating with phase selection |
| US12549419B2 (en) | 2023-06-14 | 2026-02-10 | Samsung Electronics Co., Ltd. | Methods and circuits for controlling multicycle path in serializer interface |
| CN120880436B (zh) * | 2025-09-28 | 2025-12-05 | 上海韬润半导体有限公司 | 信号处理方法、装置、时钟数据恢复电路、及电子设备 |
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| US8019022B2 (en) * | 2007-03-22 | 2011-09-13 | Mediatek Inc. | Jitter-tolerance-enhanced CDR using a GDCO-based phase detector |
| US8228126B2 (en) | 2007-04-19 | 2012-07-24 | Mediatek Inc. | Multi-band burst-mode clock and data recovery circuit |
| JP5397025B2 (ja) * | 2009-06-02 | 2014-01-22 | ソニー株式会社 | クロック再生装置および電子機器 |
| JP2011061350A (ja) * | 2009-09-08 | 2011-03-24 | Renesas Electronics Corp | 受信装置及びその受信方法 |
| JP2011160369A (ja) * | 2010-02-04 | 2011-08-18 | Sony Corp | 電子回路、電子機器、デジタル信号処理方法 |
| US8643409B2 (en) * | 2011-07-01 | 2014-02-04 | Rambus Inc. | Wide-range clock multiplier |
| US8847691B2 (en) | 2011-11-16 | 2014-09-30 | Qualcomm Incorporated | Apparatus and method for recovering burst-mode pulse width modulation (PWM) and non-return-to-zero (NRZ) data |
-
2012
- 2012-02-01 US US13/363,410 patent/US8847691B2/en active Active
- 2012-11-16 JP JP2014542513A patent/JP5848460B2/ja not_active Expired - Fee Related
- 2012-11-16 IN IN3050CHN2014 patent/IN2014CN03050A/en unknown
- 2012-11-16 CN CN201280056615.5A patent/CN103947116B/zh active Active
- 2012-11-16 WO PCT/US2012/065649 patent/WO2013075009A2/en not_active Ceased
- 2012-11-16 KR KR1020147016349A patent/KR101696320B1/ko not_active Expired - Fee Related
- 2012-11-16 EP EP12798099.3A patent/EP2781025B1/en active Active
-
2014
- 2014-09-19 US US14/490,952 patent/US9270287B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| WO2013075009A3 (en) | 2013-11-28 |
| EP2781025A2 (en) | 2014-09-24 |
| CN103947116A (zh) | 2014-07-23 |
| EP2781025B1 (en) | 2016-08-24 |
| CN103947116B (zh) | 2017-03-01 |
| US20150008967A1 (en) | 2015-01-08 |
| JP2015504635A (ja) | 2015-02-12 |
| US20130120036A1 (en) | 2013-05-16 |
| KR20140101803A (ko) | 2014-08-20 |
| US8847691B2 (en) | 2014-09-30 |
| KR101696320B1 (ko) | 2017-01-13 |
| JP5848460B2 (ja) | 2016-01-27 |
| WO2013075009A2 (en) | 2013-05-23 |
| US9270287B2 (en) | 2016-02-23 |
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