HK1208097A1 - 半導體器件及其製造方法 - Google Patents

半導體器件及其製造方法

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Publication number
HK1208097A1
HK1208097A1 HK15108606.2A HK15108606A HK1208097A1 HK 1208097 A1 HK1208097 A1 HK 1208097A1 HK 15108606 A HK15108606 A HK 15108606A HK 1208097 A1 HK1208097 A1 HK 1208097A1
Authority
HK
Hong Kong
Prior art keywords
manufacturing
same
semiconductor device
semiconductor
Prior art date
Application number
HK15108606.2A
Other languages
English (en)
Inventor
福原和矢
吉富清敬
池上武彥
川副祐二朗
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of HK1208097A1 publication Critical patent/HK1208097A1/zh

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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
HK15108606.2A 2009-11-05 2015-09-02 半導體器件及其製造方法 HK1208097A1 (zh)

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WO2012120568A1 (ja) * 2011-03-09 2012-09-13 パナソニック株式会社 半導体装置
CN102543928A (zh) * 2011-12-27 2012-07-04 上海艾为电子技术有限公司 Qfn封装结构
CN102522377A (zh) * 2011-12-27 2012-06-27 上海艾为电子技术有限公司 Qfn封装结构
JP2013153027A (ja) * 2012-01-24 2013-08-08 Fujitsu Ltd 半導体装置及び電源装置
JP6416291B2 (ja) * 2015-01-22 2018-11-07 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US10325878B2 (en) * 2016-06-30 2019-06-18 Kulicke And Soffa Industries, Inc. Methods for generating wire loop profiles for wire loops, and methods for checking for adequate clearance between adjacent wire loops
JP2018107296A (ja) * 2016-12-27 2018-07-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

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JPH04107940A (ja) * 1990-08-29 1992-04-09 Hitachi Ltd 半導体装置及びその構成部品
JPH08236564A (ja) * 1995-02-28 1996-09-13 Nec Kyushu Ltd 半導体装置
FR2764115B1 (fr) * 1997-06-02 2001-06-08 Sgs Thomson Microelectronics Dispositif semiconducteur et procede de connexion des fils internes de masse d'un tel dispositif
JPH11121683A (ja) * 1997-10-08 1999-04-30 Nissan Motor Co Ltd 半導体集積回路
US7030469B2 (en) * 2003-09-25 2006-04-18 Freescale Semiconductor, Inc. Method of forming a semiconductor package and structure thereof
JP2005191240A (ja) * 2003-12-25 2005-07-14 Renesas Technology Corp 半導体装置及びその製造方法
JP4570868B2 (ja) * 2003-12-26 2010-10-27 ルネサスエレクトロニクス株式会社 半導体装置
JP4489485B2 (ja) * 2004-03-31 2010-06-23 株式会社ルネサステクノロジ 半導体装置
JP4230439B2 (ja) * 2004-09-22 2009-02-25 三菱電機株式会社 半導体応用装置
CN1755929B (zh) * 2004-09-28 2010-08-18 飞思卡尔半导体（中国）有限公司 形成半导体封装及其结构的方法
JP2006309312A (ja) * 2005-04-26 2006-11-09 Sharp Corp レギュレータ
US7791182B2 (en) * 2005-09-27 2010-09-07 Infineon Technologies Ag Semiconductor component having maximized bonding areas of electrically conductive members connected to semiconductor device and connected to leadframe and method of producing
JP2007165368A (ja) 2005-12-09 2007-06-28 Denso Corp ワイヤ検査システム
US8125060B2 (en) * 2006-12-08 2012-02-28 Infineon Technologies Ag Electronic component with layered frame
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