GB2542542A

GB2542542A - Vertical LED chip structure and manufacturing method therefor

Info

Publication number: GB2542542A
Application number: GB1701184.2A
Authority: GB
Inventors: Lv Mengyan; Zhang Qiong; Tong Ling; Zhang Yu; Li Qiming
Original assignee: Enraytek Optoelectronics Co Ltd
Current assignee: Enraytek Optoelectronics Co Ltd
Priority date: 2014-08-08
Filing date: 2015-08-05
Publication date: 2017-03-22
Anticipated expiration: 2035-08-05
Also published as: GB2542542B; CN104134723A; GB201701184D0; WO2016019860A1; DE112015003673T5

Abstract

The present invention provides a vertical LED chip structure and a manufacturing method therefor. A transparent conducting contact layer, a low-refractive index dielectric layer provided with a distribution pattern, and a reflecting layer are sequentially formed on a P-GaN layer to form a composite reflecting mirror. In this way, the low-refractive index dielectric layer can account for a large area of the composite reflecting mirror, and the light absorption ratio of the reflecting mirror can be greatly reduced. Moreover, as the transparent conducting contact layer has high transverse electrical conductivity, current can be uniformly distributed on the whole P-GaN layer, and the comprehensive and effective reflectivity of the composite reflecting mirror can be effectively increased.

Description

VERTICAL LED CHIP STRUCTURE AND MANUFACTURING METHOD

THEREFOR

TECHNICAL FIELD

The present invention relates to the manufacture of light-emitting diode (LED) chips and, in particular to, a vertical LED chip structure and a method of fabricating the structure.

BACKGROUND

In recent years, research on light-emitting diodes (LEDs) has been gaining popularity. LED chips generally have two types of basic structures which are lateral structure and vertical structure. Traditional mainstream LED chips are typical lateral chips. Due to the limitations of sapphire substrates on which the LED chips are based, such as electric non-conductivity and a low thermal conductivity, lateral chips suffer from a number of deficiencies since the advent. One aspect of the deficiencies is that the non-conductive sapphire substrate and the arrangement of both p-electrode and n-electrode on the same side of an LED chip leads to many demerits, for example: 1) in terms of electric performance, lateral current paths in n- and p-type confinement layers in the LED chip have different lengths, which can lead to current crowding; and 2) in terms of light extraction performance, the p-electrode and the n-electrode are both arranged on the side where light exits and thus causes loss of part of the light. Another aspect of the deficiencies is that the sapphire substrate has a very low thermal conductivity, while the lateral LED chip relies on the sapphire substrate to dissipate heat generated by its p-n junction. For a power chip of a large size which has a relative long thermal conduction path, this means high thermal resistance of the LED chip and hence limitations to its working current.

In order to overcome such deficiencies of the lateral LED chips, Cree Inc. (US), Osram Licht AG (Germany), Philips Lumileds Lighting Company (US) and SemiLEDs Corporation (US) are all actively investing in the development of vertical LED (hereinafter referred to as V-LED) chips in which silicon or metal substrates that are highly conductive, both electrically and thermally, are employed. In a V-LED chip, on one hand, p-electrode and n-electrode are arranged on opposing sides of an epitaxial layer of an LED chip, and a patterned electrode and all p-type confinement layers together serve as the p-side electrode. As such, almost any current in the epitaxial layer of the LED chip flows vertically, and there is barely any lateral current therein. This results in an improvement over the lateral structures discussed above in terms of current distribution as well as an enhancement in light-emission efficiency, and can avoid the loss of light attributed to the p-electrode and hence allow a larger light-emission area of the LED chip. On the other hand, employment of the highly electrically and thermally conductive silicon or metal substrates can address the heat dissipation issue for p-n junctions, thereby allowing the fabrication of large-size power chips.

Since the silicon or metal substrate that comes into contact with the p-electrode at the bottom is not light-transmissive, a reflector is generally provided at the p-side of the V-LED chip in order to facilitate light extraction so that most light can exit the top n-side of the V-LED chip. Therefore, the ohmic contact quality at the p-side and the reflectivity of the reflector are the most crucial factors for performance of the V-LED chip and, between these factors, the reflectivity of the reflector at the p-side directly determines the brightness of the V-LED chip. Reflectors in existing vertical LED chips are mostly metallic features which utilize the high reflectivities of silver (Ag), aluminum (Al), rhodium (Rh) or a similar metal for reflecting light propagating toward the bottom of the chip.

Reference is now made to Fig. 1, which schematically illustrates a V-LED chip of the prior art. So far, the commercially available V-LED chip includes: a substrate 10 and, sequentially formed on the substrate 10, a protective layer, a metal bonding layer 20, a reflector 30, a p-GaN layer 40, a quantum well layer 50, an n-GaN layer 60 and an n-electrode 70. In general, the reflector 30 is made of a highly reflective metallic material typically containing Ag as the main ingredient. Due to the active nature of Ag, such a reflector 30 is susceptible to oxidation, clustering, migration and other adverse effects, necessitating the protective layer. In addition, as Ag cannot be adhesively attached to the p-GaN of the V-LED chip sufficiently, the reflector is typically further provided with a layer of chromium (Cr), nickel (Ni) or a like metal (not shown) to address the issue of insufficient adhesion. However, a reflector 30 made purely of Ag or another similar metal can absorb light at the boundary, which can lead to a reduction in the V-LED’s light-emission efficiency.

In order to solve this problem, there is also proposed a vertical LED chip in the prior art, as shown in Fig. 2. This architecture takes advantage of the physical phenomenon that light propagating within an optically dense medium are totally reflected when striking the boundary with an optically thin medium by using a double-layered composite reflector fabricated by adding to the Ag-based reflector 30 a layer of a non-conductive dielectric with a lower refractive index (e.g., silicon dioxide (SiOi)). This composite reflector has improved effective reflectivity because it can effectively reduce light absorption at the boundary of the reflector 30. As shown in Fig. 2, the vertical LED chip resembles that of Fig. 1 but additionally has the low-refractive-index dielectric 31 that is disposed between the reflector 30 and the p-GaN layer 40 in order to increase the effective reflectivity.

Another important function of the composite reflector is to serve as a p-side ohmic contact layer for the vertical LED chip. As the low-refractive-index dielectric 31 (generally S1O2) is not conductive, this ohmic contact function has to be accomplished by the Ag-based reflector 30. For this reason, a rather great proportion of the Ag-based reflector 30 in the composite reflector must be ensured. Generally, the low-refractive-index dielectric 31 accounts for only 20% to 80% of the composite reflector in terms of surface area. Therefore, it is not feasible to enhance the reflectivity of the composite reflector by infinitely increasing the proportion of the low-refractive-index dielectric 31 in the composite reflector. In addition, as the current spreading ability of the p-side is extremely weak, it is barely possible for the double-layered composite reflector to obtain uniform current diffusion at the p-side by current distribution adjustments based on modifications to configuration of the Ag-based reflector 30.

Therefore, it is an important task for those skilled in the art to solve the problems associated with these prior-art reflectors.

SUMMARY OF THE INVENTION

It is therefore an objective of the present invention to provide a vertical LED chip structure and a method of fabricating it, which can reduce the proportion of light absorbed in the reflector while taking current distribution uniformity at the p-side into account.

This objective is attained by a method for fabricating a vertical LED chip according to the present invention, including the steps of: providing a growth substrate and forming an epitaxial layer on the growth substrate, wherein the epitaxial layer includes, sequentially formed, a non-doped layer, an n-GaN layer, a quantum well layer and a p-GaN layer, with the non-doped layer directly formed on the growth substrate; forming a transparent conductive contact layer on the p-GaN layer; forming a low-refractive-index dielectric layer on the transparent conductive contact layer and patterning the low-refractive-index dielectric layer using a photolithographic process to form a pattern, wherein the pattern exposes a portion of the underlying transparent conductive contact layer; forming a reflective layer on the low-refractive-index dielectric layer and the transparent conductive contact layer; forming a protective layer and a metal bonding layer on the reflective layer; bonding a bond substrate onto the metal bonding layer; removing the growth substrate and etching the non-doped layer to expose at least a portion of the n-GaN layer; and forming an n-electrode on the exposed portion of the n-GaN layer.

Further, in the method for fabricating a vertical LED chip, the transparent conductive contact layer may be formed of ITO, ZnO or AZO.

Further, in the method for fabricating a vertical LED chip, the low-refractive-index dielectric layer may be formed of one or a stack of ones selected from the group consisting of S1O2, SiNx, ΊΊ3Ο5 and AI2O3, and the low-refractive-index dielectric layer has a thickness of from 10 A to 50 gm.

Further, in the method for fabricating a vertical LED chip, the low-refractive-index dielectric layer may have a cross-sectional area constituting 85% to 95% of a cross-sectional area of the vertical LED chip.

Further, in the method for fabricating a vertical LED chip, the reflective layer may be formed by vapor deposition using a negative resist lift-off technique such that the formed reflective layer has a cross-sectional area smaller than a cross-sectional area of the vertical LED chip.

Further, in the method for fabricating a vertical LED chip, the reflective layer may be formed of Ag, A1 or Rh.

Further, in the method for fabricating a vertical LED chip, the protective layer may be formed of (Ti-Pt)x, or a combination of TiW and Pt, wherein the metal bonding layer is formed of Au, Sn or an Au-Sn alloy.

Further, in the method for fabricating a vertical LED chip, the bond substrate may be formed of Si, Cu or MoCu.

Further, in the method for fabricating a vertical LED chip, the growth substrate may be removed using laser or a chemical process.

Further, in the method for fabricating a vertical LED chip, prior to removing the growth substrate and before forming the n-electrode, the non-doped layer may be etched using a wet etching process or a dry etching process to expose the n-GaN layer, and then the n-GaN layer may be roughened using a KOH or H2SO4 solution to form a rough surface.

Further, in the method for fabricating a vertical LED chip, a passivation layer may be formed on the rough surface after forming the n-electrode, wherein the passivation layer is SiCE.

Further, in the method for fabricating a vertical LED chip, the n-electrode may be formed of Ni/Au, Al/Ti/Pt/Au or Cr/Pt/Au.

The present invention also provides a vertical LED chip fabricated using the method as defined above, which includes, stacked sequentially, a bond substrate, a metal bonding layer, a protective layer, a reflective layer, a low-refractive-index dielectric layer with a pattern formed therein, a transparent conductive contact layer, a p-GaN layer, a quantum well layer, an n-GaN layer and an n-electrode, wherein the n-electrode is connected to the n-GaN layer.

Further, the vertical LED chip may also include a rough surface and a passivation layer, wherein the rough surface is formed on a top surface of the n-GaN layer; the passivation layer is formed on the rough surface; and both of the rough surface and the passivation layer expose the n-electrode.

Compared to the prior art, the present invention offers mainly the following benefits: the transparent conductive contact layer, the low-refractive-index dielectric layer with a pattern formed therein and the reflective layer that are sequentially formed on the p-GaN layer form a three-layered composite reflector in which the low-refractive-index dielectric layer accounts for a great proportion of area, resulting in a significant reduction in the proportion of light absorbed in the reflector. In addition, the transparent conductive contact layer is highly capable of lateral electrical conductance and thus allows a uniform current distribution within the entire p-GaN layer. This enables an effective increase in the comprehensive effective reflectivity of the composite reflector.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 schematically illustrates a vertical LED chip of the prior art.

Fig. 2 schematically illustrates another vertical LED chip of the prior art.

Fig. 3 is a flow chart graphically illustrating a method for fabricating a vertical LED chip structure in accordance with an embodiment of the present invention.

Figs. 4-12 are schematic cutaway views showing a process for fabricating a vertical LED chip structure in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION

Vertical LED chip structures and methods of fabricating them according to the present invention will be described in greater detail in the following description which presents preferred embodiments of the invention and is to be read in conjunction with the accompanying drawings. It is to be appreciated that those of skill in the art can make changes in the invention disclosed herein while still obtaining the beneficial results thereof. Therefore, the following description shall be construed as being intended to be widely known by those skilled in the art rather than as limiting the invention.

For simplicity and clarity of illustration, not all features of the disclosed specific embodiments are described. Additionally, descriptions and details of well-known functions and structures are omitted to avoid unnecessarily obscuring the invention. The development of any specific embodiment of the present invention includes specific decisions made to achieve the developer’s specific goals, such as compliance with system related and business related constraints, which will vary from one implementation to another. Moreover, such a development effort might be complex and time consuming but would nevertheless be a routine undertaking for those of ordinary skill in the art.

The present invention will be further described in the following paragraphs by way of example with reference to the accompanying drawings. Features and advantages of the invention will be more apparent from the following detailed description, and from the appended claims. Note that the accompanying drawings are provided in a very simplified form not necessarily presented to scale, with the only intention of facilitating convenience and clarity in explaining a few illustrative examples of the invention.

Reference is now made to Fig. 3, a method for fabricating a vertical LED chip according to an embodiment includes the steps as described below.

In step S100, a growth substrate is provided and an epitaxial layer is formed on the growth substrate. The epitaxial layer includes, sequentially formed, a non-doped layer, an n-GaN layer, a quantum well layer and a p-GaN layer, with the non-doped layer directly formed on the growth substrate.

In step S200, a transparent conductive contact layer is formed on the p-GaN layer.

In step S300, a low-refractive-index dielectric layer is formed on the transparent conductive contact layer and is patterned using a photolithographic process to form a pattern, wherein the pattern exposes a portion of the underlying transparent conductive contact layer.

In step S400, a reflective layer is formed on the low-refractive-index dielectric and the transparent conductive contact layer.

In step S500, a protective layer and a metal bonding layer are formed over the reflective layer.

In step S600, a bond substrate is bonded onto the metal bonding layer;

In step S700, the growth substrate is removed and the non-doped layer is etched such that the n-GaN layer is exposed;

In step S800, an n-electrode is formed on the n-GaN layer.

Specifically, with reference to Fig. 4, in step S100, the growth substrate 100 is provided which may be a sapphire substrate, a silicon substrate, a SiC substrate, a patterned substrate or the like. In this embodiment, the epitaxial layer includes the non-doped layer 210, the n-GaN layer 220, the quantum well layer 230 and the p-GaN layer 240. The epitaxial layer may be formed by a growth process such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

Referring to Fig. 5, in step S200, the transparent conductive contact layer 300 is formed on the p-GaN layer 240. The transparent conductive contact layer 300 may be a low-resistance, high-light-transmittance thin film formed of, for example, indium tin oxide (ITO), zinc oxide (ZnO) or aluminum-doped zinc oxide (AZO). The transparent conductive contact layer 300 serves as an ohmic contact layer.

Referring to Fig. 6, in step S300, the low-refractive-index dielectric layer 400 is formed on the transparent conductive contact layer 300, and a pattern, i.e., a through hole 410 is formed in the low-refractive-index dielectric layer 400. While only one of the through holes is schematically shown in the figure for the sake of simplicity, the present invention is not limited in this regard. The transparent conductive contact layer 300 is exposed in the pattern which may assume one of a variety of forms, such as circular holes, rectangular holes, ellipsoid holes or a combination thereof, without limitation. The low-refractive-index dielectric layer 400 can be one of S1O2, silicon nitride (SiNx), titanium oxide (T13O5) and aluminum oxide (AI2O3), or a stack of several of them. The low-refractive-index dielectric layer 400 may have a thickness of from 10 A to 50 pm, for example, 100 A. The low-refractive-index dielectric layer 400 may be formed using, for example, an e-beam process, a sputtering process or a reactive plasma deposition (RPD) process. Preferably, the formed low-refractive-index dielectric layer 400 accounts for 85% to 95% of the vertical LED chip being fabricated in terms of cross-sectional area, which can result in a significant reduction in the proportion of light absorbed by a subsequently formed reflector.

Referring to Fig. 7, in step S400, a reflective layer 500 is formed on the low-refractive-index dielectric layer 400 and the exposed transparent conductive contact layer 300. Specifically, the reflective layer 500 may be formed by vapor deposition in predetermined areas using a negative resist lift-off process, and the formed reflective layer 500 can have a size that is smaller than that of the vertical LED chip being fabricated. That is, an edge of the vertical LED chip being fabricated is exposed after the formation of the reflective layer 500, thereby allowing the reflective layer 500 to be fully protected by the subsequently formed protective layer. The reflective layer 500 may be formed of Ag, A1 or Rh.

Referring to Fig. 8, in step S500, the protective layer and the metal bonding layer 600 are formed over the reflective layer 500 (the protective layer and the metal bonding layer are schematically shown as a single layer for the sake of simplicity). The protective layer may be formed of (Ti-Pt)x, or a combination of TiW and Pt and fully covers the reflective layer 500 in order to protect it. The metal bonding layer may be formed of gold (Au), tin (Sn) or an Au-Sn alloy and bonded to the bond substrate in the subsequent step.

Referring to Fig. 9, in step S600, the bond substrate 700 is bonded onto the metal bonding layer. The bond substrate 700 may be a substrate with a high conductivity and high heat dissipation formed of Si, Cu, MoCu or the like.

Referring to Fig. 10, in step S700, the growth substrate 100 is removed. The removing of the growth substrate 100 may be generally accomplished using laser or a chemical process. Generally, use of laser can lead to the formation a gallium layer over the surface of the non-doped layer 210. In this case, an acid, an alkali or the like, such as an HC1 or KOH solution, can be used to remove the gallium layer.

Referring to Fig. 11, prior to the formation of the n-electrode, the non-doped layer 210 may be etched using a wet etching process or a dry etching (ICP) process such that the n-GaN layer 220 is exposed, wherein the non-doped layer 210 may be etched away either wholly or partially. Subsequently, the n-GaN layer 220 may be roughened so as to have a rough surface 211. The rough surface 211 obtained in this way can increase the surface area of the n-GaN layer 220, which results in a greater light-emission area and higher light-emission efficiency.

Referring to Fig. 12, in step S800, the n-electrode 212 is formed on the n-GaN layer 220. The n-electrode 212 may be formed of Ni/Au, Al/Ti/Pt/Au or Cr/Pt/Au. With the completion of the n-electrode 212, a passivation layer 800 may be formed over the rough surface 211. The passivation layer 800 may be S1O2 and serves to protect the whole chip being fabricated. The n-electrode 212 is exposed in the formed passivation layer 800.

With continued reference to Fig. 12, in another aspect of the present invention, a vertical LED chip structure fabricated using the method described above is also provided. The structure includes, stacked sequentially, a bond substrate 700, a metal bonding and protective layer 600, a reflective layer 500, a patterned low-refractive-index dielectric layer 400, a transparent conductive contact layer 300, a p-GaN layer 240, a quantum well layer 230, an n-GaN layer 220, an n-electrode 212, a rough surface 211 and a passivation layer 800. The n-electrode 212 is connected to the n-GaN layer 220, and the rough surface 211 is formed on the top surface of the n-GaN layer 220. The passivation layer 800 covers the rough surface 211, and the n-electrode 212 is exposed in both of the rough surface 211 and the passivation layer 800.

In conclusion, in the vertical LED chip structures and methods of fabricating them according to the present invention, the transparent conductive contact layer, the patterned low-refractive-index dielectric layer and the reflective layer that are sequentially formed above the p-GaN layer constitute a three-layered composite reflector, in which the low-refractive-index dielectric layer accounts for a great proportion of area of the composite reflector, resulting in a significant reduction in the proportion of light absorbed in the reflector. In addition, the transparent conductive contact layer is highly capable of lateral electrical conductance and thus allows a uniform current distribution within the entire p-GaN layer. This enables an effective increase in the comprehensive effective reflectivity of the composite reflector.

The foregoing description presents merely a preferred embodiment of the present invention and does not limit the scope of the invention in any way. All equivalent substitutions or modifications made to the subject matter disclosed herein by those of ordinary skill in the art without departing from the scope of the present invention fall within the scope of the invention.

Claims

1. A method for fabricating a vertical LED chip, comprising the steps of: providing a growth substrate and forming an epitaxial layer on the growth substrate, wherein the epitaxial layer comprises, sequentially formed, a non-doped layer, an n-GaN layer, a quantum well layer and a p-GaN layer, with the non-doped layer directly formed on the growth substrate; forming a transparent conductive contact layer on the p-GaN layer; forming a low-refractive-index dielectric layer on the transparent conductive contact layer and patterning the low-refractive-index dielectric layer using a photolithographic process to form a pattern, wherein the pattern exposes a portion of the underlying transparent conductive contact layer; forming a reflective layer on the low-refractive-index dielectric layer and the transparent conductive contact layer; forming a protective layer and a metal bonding layer on the reflective layer; bonding a bond substrate onto the metal bonding layer; removing the growth substrate and etching the non-doped layer to expose at least a portion of the n-GaN layer; and forming an n-electrode on the exposed portion of the n-GaN layer.

2. The method for fabricating a vertical LED chip of claim 1, wherein the transparent conductive contact layer is formed of ITO, ZnO or AZO.

3. The method for fabricating a vertical LED chip of claim 1, wherein the low-refractive-index dielectric layer is formed of one or a stack of ones selected from the group consisting of SiCE, SiNx, TisCE and AI2O3, and the low-refractive-index dielectric layer has a thickness of from 10 A to 50 pm.

4. The method for fabricating a vertical LED chip of claim 1, wherein the low-refractive-index dielectric layer has a cross-sectional area constituting 85% to 95% of a cross-sectional area of the vertical LED chip.

5. The method for fabricating a vertical LED chip of claim 1, wherein the reflective layer is formed by vapor deposition using a negative resist lift-off technique such that the formed reflective layer has a cross-sectional area smaller than a cross-sectional area of the vertical LED chip.

6. The method for fabricating a vertical LED chip of claim 5, wherein the reflective layer is formed of Ag, A1 or Rh.

7. The method for fabricating a vertical LED chip of claim 1, wherein the protective layer is formed of (Ti-Pt)x, or a combination eof TiW and Pt, and wherein the metal bonding layer is formed of Au, Sn or an Au-Sn alloy.

8. The method for fabricating a vertical LED chip of claim 1, wherein the bond substrate is formed of Si, Cu or MoCu.

9. The method for fabricating a vertical LED chip of claim 1, wherein the growth substrate is removed using laser or a chemical process.

10. The method for fabricating a vertical LED chip of claim 1, wherein etching the non-doped layer comprises: etching the non-doped layer using a wet etching process or a dry etching process to expose the n-GaN layer.

11. The method for fabricating a vertical LED chip of claim 10, further comprising, prior to forming the n-electrode, roughening the n-GaN layer using a KOH or H2SO4 solution to form a rough surface.

12. The method for fabricating a vertical LED chip of claim 11, further comprising forming a passivation layer on the rough surface after forming the n-electrode, wherein the passivation layer exposes the n-electrode.

13. The method for fabricating a vertical LED chip of claim 1, wherein the n-electrode is formed of Ni/Au, Al/Ti/Pt/Au or Cr/Pt/Au.

14. A vertical LED chip fabricated using a method as defined in any one of claims 1 to 13, comprising, stacked sequentially, a bond substrate, a metal bonding layer, a protective layer, a reflective layer, a low-refractive-index dielectric layer with a pattern formed therein, a transparent conductive contact layer, a p-GaN layer, a quantum well layer, an n-GaN layer and an n-electrode, wherein the n-electrode is connected to the n-GaN layer.

15. The vertical LED chip of claim 14, further comprising a rough surface and a passivation layer, wherein the rough surface is formed on a top surface of the n-GaN layer; the passivation layer is formed on the rough surface; and both of the rough surface and the passivation layer expose the n-electrode.