KR20140121608A

KR20140121608A - Reflective Electrode of LED, LED Chip Having the Same, and Method of Fabricating Those

Info

Publication number: KR20140121608A
Application number: KR1020130038023A
Authority: KR
Inventors: 이소라; 김재권; 이섬근
Original assignee: 서울바이오시스 주식회사
Priority date: 2013-04-08
Filing date: 2013-04-08
Publication date: 2014-10-16

Abstract

Provided are a reflective electrode of a light emitting diode, a light emitting diode chip including the same, and manufacturing methods thereof. A method for forming the reflective electrode of the light emitting diode includes a step of forming a mask pattern with an opening part to expose the surface of a semiconductor layer on the semiconductor layer. The mask pattern includes a cave which is extended from the opening part in a contact area between the mask pattern and the semiconductor layer. A reflective conductive layer is formed in the opening part. A conductive barrier layer which covers the surface and lateral side of the reflective conductive layer is formed on the reflective conductive layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reflective electrode of a light emitting diode, a light emitting diode chip including the same,

The present invention relates to a semiconductor device, and more particularly, to a light emitting diode.

The light emitting diode includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer disposed between the n-type and p-type semiconductor layers. When a forward electric field is applied to the n- Electrons and holes are injected into the active layer, and electrons and holes injected into the active layer are recombined to emit light.

The light emitting diode may be provided with an electrode including a reflective metal film on a semiconductor layer located on a surface opposite to a surface from which light is extracted. In general, the reflective metal film may be a metal film which is easily diffused or contaminated, and thus the barrier metal film may be laminated on the reflective metal film. This example is also disclosed in Korean Patent Publication No. 2006-0000836.

However, in the Korean Unexamined Patent Publication, the barrier metal film is not formed to cover the reflective metal film, so that the side of the reflective metal film is exposed, so diffusion or contamination may still be a problem.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a light emitting diode capable of preventing diffusion or contamination by a reflective metal film.

According to an aspect of the present invention, there is provided a method of forming a reflective electrode of a light emitting diode. First, a mask pattern having openings exposing the surface of the semiconductor layer is formed on the semiconductor layer. Wherein the mask pattern has a cave extending from the opening in a portion of the mask pattern contacting the semiconductor layer. A reflective conductive film is formed in the opening. A conductive barrier layer is formed on the reflective conductive film to cover the surface and the side surface of the reflective conductive film.

The conductive barrier layer may be formed using a deposition method in which the orientation of the deposition beam is lower than that of the deposition method of forming the reflective conductive film. The reflective conductive film may be formed using an electron beam evaporation method. The conductive barrier layer may be formed using a sputtering method.

The reflective conductive film may include Al, an Al alloy, Ag, or an Ag alloy. The conductive barrier layer may comprise W, TiW, Mo, Cr, Ni, Pt, Rh, Pd or Ti.

The opening may have a width of the inlet smaller than a width of the bottom. The conductive barrier layer may also be formed in the cave.

According to another aspect of the present invention, there is provided a reflective electrode of a light emitting diode. The reflective electrode of the light emitting diode has a reflective conductive film disposed on the semiconductor layer. A conductive barrier layer covering the surface and the side surface of the reflective conductive film and extending over the semiconductor layer is disposed on the reflective conductive film. The angle formed by the side surface of the conductive barrier layer and the surface of the semiconductor layer is smaller than the angle formed by the side surface of the reflective conductive film and the surface of the semiconductor layer.

Wherein a thickness of the conductive barrier layer is smaller than a thickness formed on a surface of the semiconductor layer in comparison with a thickness formed on an upper surface of the reflective conductive layer and is smaller than a thickness formed on a surface of the semiconductor layer, The thickness formed on the substrate may be small.

The distance between the edge of the conductive barrier layer and the edge of the reflective conductive film may be uniform over the entire circumference of the reflective conductive film.

According to another aspect of the present invention, there is provided a reflective electrode of a light emitting diode. The reflective electrode of the light emitting diode has a reflective conductive film disposed on the semiconductor layer. A conductive barrier layer covering the surface and the side surface of the reflective conductive film and extending over the semiconductor layer is disposed on the reflective conductive film. The edge portion of the conductive barrier layer has a smooth profile.

According to another aspect of the present invention, there is provided a method of fabricating a light emitting diode. First, a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer are sequentially formed on a substrate. And a mask pattern is formed on the second conductivity type semiconductor layer and has an opening for exposing a surface of the second conductivity type semiconductor layer. The mask pattern has a cave extending from the opening in a portion of the mask pattern contacting the second conductivity type semiconductor layer. A reflective conductive film is formed in the opening. A conductive barrier layer is formed on the reflective conductive film to cover the surface and the side surface of the reflective conductive film.

According to another aspect of the present invention, there is provided a light emitting diode. The light emitting diode includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer which are sequentially stacked on a substrate. A reflective conductive film is disposed on the second conductive type semiconductor layer. A conductive barrier layer covering the surface and the side surface of the reflective conductive film and extending over the semiconductor layer is disposed on the reflective conductive film. The angle formed by the side surface of the conductive barrier layer and the surface of the semiconductor layer is smaller than the angle formed by the side surface of the reflective conductive film and the surface of the semiconductor layer.

According to the present invention, the conductive barrier layer may be free from defects such as tearing of edge portions. As a result, no particles are generated due to the conductive barrier layer, so that contamination sources in subsequent processes can be avoided.

The technical effects of the present invention are not limited to those mentioned above, and other technical effects not mentioned can be clearly understood by those skilled in the art from the following description.

1A to 1E are cross-sectional views illustrating a light emitting diode according to an embodiment of the present invention.
2 is a cross-sectional view illustrating a light emitting diode according to an exemplary embodiment of the present invention.
3A to 3C are SEM photographs showing actual examples of forming the reflective electrode.
4A to 4E are plan views and sectional views illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention.
5A to 5E are plan views and sectional views showing a method of manufacturing a light emitting diode according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms.

When a layer is referred to herein as being "on" another layer or substrate, it may be formed directly on another layer or substrate, or a third layer may be interposed therebetween. In the present specification, directional expressions of the upper side, the upper side, the upper side, and the like can be understood as meaning lower, lower (lower), lower, and the like. That is, the expression of the spatial direction should be understood in a relative direction, and it should not be construed as definitively as an absolute direction.

In the present embodiments, "first "," second ", or "third" is not intended to impose any limitation on the elements, but merely as terms for distinguishing the elements.

Further, in the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals designate like elements throughout the specification.

1A to 1E are cross-sectional views illustrating a light emitting diode according to an embodiment of the present invention.

Referring to FIG. 1A, a first conductive semiconductor layer 110, an active layer 120, and a second conductive semiconductor layer 130 are sequentially formed on a substrate 100. The substrate 100 may be made of any material as long as it has a structure capable of inducing growth of the first semiconductor layer 110. As an example, the substrate 100 may be formed of a material selected from the group consisting of sapphire (Al ₂ O ₃ ), silicon carbide (SiC), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN) Oxide (Ga ₂ O ₃ ), or a silicon substrate. Specifically, the substrate 100 may be a sapphire substrate.

The first conductive semiconductor layer 110 may be a nitride-based semiconductor layer doped with an n-type dopant. As an example, the first conductivity type semiconductor layer 110 may be formed of an n-type doped layer of In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, x + May be a doped layer. Specifically, the first conductivity type semiconductor layer 110 may be a Si-doped GaN layer. The second conductivity type semiconductor layer 130 may also be a nitride semiconductor layer or a layer doped with a p-type dopant. As an example, the second conductivity type semiconductor layer 130 may be formed of a p-type conductivity type In _x Al _y Ga _1-xy N (0 x 1, 0 y 1, 0 x + y 1) May be a layer doped with Mg or Zn. Specifically, the second conductivity type semiconductor layer 130 may be a GaN layer doped with Mg. The active layer 120 may be a layer of In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, 0? _X + y? 1), and may have a single quantum well structure or multi -quantum well (MQW). As an example, the active layer 120 may have a single quantum well structure of an InGaN layer or an AlGaN layer, or a multiple quantum well structure of a multi-layer structure of InGaN / GaN, AlGaN / (In) GaN, or InAlGaN / have.

The first conductive semiconductor layer 110, the active layer 120 and the second conductive semiconductor layer 130 may be formed using a metal organic chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method .

Referring to FIG. 1B, a photoresist pattern (not shown) is formed on the second conductive type semiconductor layer 130, and the second conductive type semiconductor layer 130 and the active layer 120 are formed as a first conductive Type semiconductor layer 110 is exposed to form a mesa (MS). The side of the mesa (MS) can be formed obliquely, and a technique such as photoresist reflow can be used for this purpose. The side of the mesa (MS) having such a tilted profile can improve the extraction efficiency of the light generated in the active layer 120.

After the mesa (MS) is formed, the edges of the exposed first conductivity type semiconductor layer 110 may be additionally etched to expose the upper surface of the substrate 100. At this time, the side surfaces of the first conductivity type semiconductor layer 110 may also be inclined. However, the present invention is not limited to this, and the process of further etching the edge of the first conductivity type semiconductor layer 110 may be omitted.

Referring to FIG. 1C, a mask pattern 160 including an opening 160a exposing a surface of the second conductive semiconductor layer 130 is formed on a mesa (MS). The mask pattern 160 may be a photoresist pattern. The opening 160a of the mask pattern 160 may have a shape that the width thereof increases toward the bottom. In other words, the bottom width W2 may be larger than the inlet width W1 of the opening 160a. The mask pattern 160 may be a negative type in which the exposed portion is cross-linked and the unexposed portion is dissolved by the developer. The direction of the exposure beam may have a predetermined slope with respect to the substrate 100 in order to form the opening portion 160a such that the bottom width W2 is larger than the entrance width W1. The bottom width W2 may be about 1um or more, for example, about 2um or more, as compared with the entrance width W1 of the opening 160a. In addition, the angle x between the upper surface and the side surface of the mask pattern 160 may be about 70 to 80 degrees, for example, about 71 degrees. The height h2 of the mask pattern 160 may be about 5 to 6 um.

A cave 160b extending from the opening 160a may be formed at a portion of the mask pattern 160 that is in contact with the second conductivity type semiconductor layer 130. [ As viewed from above, the cave 160b may extend from all sides of the opening 160a and surround the opening 160a. For this purpose, the mask pattern 160 may be composed of two layers 161 and 162 having different concentrations of the light-sensitive crosslinking agent. As an example, the concentration of the photoinitiator in the lower layer 161 may be lower than in the upper layer 162. In this case, the degree of crosslinking of the lower layer 161 may be less than the degree of crosslinking of the upper layer 162. As a result, a portion of the lower layer 161 adjacent to the side of the opening 160b is dissolved by the developer, Can be formed. However, the method of forming the cave 160b is not limited thereto. The height h1 of the cave 160b may be about 0.1 to 1 mu m and the width W3 may be about 1 mu m or more, e.g. about 2 mu m.

Referring to FIG. 1D, a reflective conductive layer 142 may be formed on the second conductive semiconductor layer 130 exposed in the opening 160a. The ohmic contact layer 141 may be formed on the second conductivity type semiconductor layer 130 before forming the reflective conductive layer 142. [ In addition, the stress relieving layer 143 can be formed on the reflective conductive film 142.

The reflective conductive film 142 includes Al, an Al alloy, Ag, or an Ag alloy. The thickness of the reflective conductive film 142 may be in the range of 100 nm to 1 [mu] m, considering the efficient reflection of the light emitted from the active layer 120 and the suitability of the deposition time. The ohmic contact layer 141 may include Ni, Pt, ITO, or ZnO. Further, the thickness of the ohmic contact layer 141 may be 0.1 nm to 20 nm in consideration of sufficient ohmic characteristics and good light transmittance.

The reflective conductive film 142 may be formed by a conventional metal water vapor deposition method. As an example, the reflective conductive film 142 may be formed using e-beam evaporation in which the deposition beam has a directional, e.g., perpendicular, directional, or anisotropic. In this case, the reflective conductive film 142 is formed so as to have substantially the same width as the entrance width (W1 in FIG. 1C) of the opening 160a. The ohmic contact layer 141 and the stress relieving layer 143 can also be formed using the same method as that for forming the reflective conductive film 142. [ In this process, the ohmic contact layer 141, the reflective conductive film 142, and the stress relieving layer 143 may be sequentially stacked on the mask pattern 160.

Subsequently, when the stress relieving layer 143 is formed on the reflective conductive film 142, the conductive barrier layer 144 may be formed on the stress relieving layer 143. The ohmic contact layer 141, the reflective conductive film 142, the stress relieving layer 143, and the conductive barrier layer 144 can form the reflective electrode 140.

The conductive barrier layer 144 may comprise W, TiW, Mo, Cr, Ni, Pt, Rh, Pd or Ti. The conductive barrier layer 144 may be formed of a single layer of 100 nm or more by selecting a specific metal. Alternatively, the conductive barrier layer 144 may be a layer in which two or more metal layers having different refractive indexes are alternately laminated, and each metal layer may be 20 nm or more. For example, the conductive barrier layer 144 may be formed by alternately depositing TiW having a thickness of 50 nm and Ni layer or Ti layer having a thickness of 50 nm, or by alternately depositing a Ni layer and a Ti layer. The material constituting the conductive barrier layer 144 may be changeable depending on the selection of the material of the reflective metal layer 142 and the stress relieving layer 143. Also, on the conductive barrier layer 144, a Ni / Au / Ti layer may be additionally formed for stable contact with subsequent materials.

The conductive barrier layer 144 may be formed to cover the reflective conductive film 142. When the stress relieving layer 143 is formed, the conductive barrier layer 144 may be formed to cover the stress relieving layer 143 as well as the reflective conductive layer 142. In this case, the side surface of the reflective conductive film 142 is shielded by the conductive barrier layer 144 to prevent the diffusion of the metal from the reflective conductive film 142 and the contamination. For this purpose, the conductive barrier layer 144 may be formed using a deposition method with a lower orientation of the deposition beam than the method of forming the reflective conductive layer 142. In other words, the conductive barrier layer 144 may be formed using isotropic deposition. As an example, the conductive barrier layer 144 may be formed using a sputtering method.

The conductive barrier layer 144 may be formed not only in the opening 160a but also in the cave (160b in Fig. 1C). In other words, the edge of the conductive barrier layer 144 may be located in the cave 160b. The conductive barrier layer 144 may also be formed on the mask pattern 160 and on the mask pattern 160 side due to isotropic deposition. However, due to the formation of the cave 160b, the edge portion of the conductive barrier layer 144 may not contact the conductive barrier layer 144 formed on the side of the mask pattern 160 or the mask pattern 160. [

The stress relieving layer 143 has a lower thermal expansion coefficient than the reflective conductive layer 142 and may have a higher thermal expansion coefficient than the conductive barrier layer 144 described later. The stress relieving layer 143 can absorb the stress caused by the difference in thermal expansion coefficient between the conductive barrier layer 144 and the reflective metal layer 142. [ When the reflective conductive layer 142 is Al or an Al alloy and the conductive barrier layer 144 includes W, TiW or Mo, the stress relieving layer 143 may be formed of Ag, Cu, Ni, Pt, Ti, A single layer of Rh, Pd or Cr, or a composite layer of Cu, Ni, Pt, Ti, Rh, Pd or Au. When the reflective conductive layer 142 is Al or an Al alloy and the conductive barrier layer 144 is Cr, Pt, Rh, Pd or Ni, the stress relieving layer 143 may be a single layer of Ag or Cu, Ni, Au, Cu or Ag. When the reflective conductive layer 142 is Ag or an Ag alloy and the conductive barrier layer 144 includes W, TiW, or Mo, the stress relieving layer 143 may be formed of Cu, Ni, Pt, Ti, Rh, A single layer of Pd or Cr, or a composite layer of Cu, Ni, Pt, Ti, Rh, Pd, Cr or Au. When the reflective conductive layer 142 is Ag or an Ag alloy and the conductive barrier layer 144 includes Cr or Ni, the stress relieving layer 143 may be a single layer of Cu, Cr, Rh, Pd, TiW, or Ti , A composite layer of Ni, Au, or Cu. In one embodiment, the ohmic contact layer 141 is made of Ni, the reflective conductive layer 142 is made of Ag, the stress relieving layer 143 is made of Ni / Au, and the conductive barrier layer 144 is made of Ni / Ti / Ni / Ti .

Referring to FIG. 1E, the mask pattern 160 is removed. As a result, on the second conductivity type semiconductor layer 130, the conductive conductive layer 142 and the conductive barrier layer 144 covering the upper and side portions thereof and extending on the second conductive type semiconductor layer 130 are formed . The conductive barrier layer 144, the reflective conductive film 142, and the like formed on the mask pattern 160 can also be removed by removing the mask pattern 160. The conductive barrier layer 144 extending on the second conductive semiconductor layer 130 is not in contact with the conductive barrier layer 144 formed on the side of the mask pattern 160 or the mask pattern 160, There may be no defects such as tearing of the edge portion. As a result, particles may not be generated due to the conductive barrier layer 144, so that a contamination source in a subsequent process may not be generated.

2 is a cross-sectional view illustrating a light emitting diode according to an exemplary embodiment of the present invention. The light emitting diode according to Fig. 2 may be formed using the method described with reference to Figs. 1A to 1E.

Referring to FIG. 2, the first conductive semiconductor layer 110 may be disposed on the substrate 100. A mesa (MS) including the active layer 120 and the second conductivity type semiconductor layer 130 may be disposed on the first conductivity type semiconductor layer 110. The side of the mesa (MS) may be inclined so that the width of the mesa (MS) becomes narrower toward the upper part.

A conductive barrier layer 144 may be disposed on the second conductive semiconductor layer 130 so as to cover the reflective conductive layer 142 and the upper and side surfaces of the reflective conductive layer 142 and the second conductive semiconductor layer 130. The conductive barrier layer 144 may be formed without cracks on the top and sides of the reflective conductive film 142. The ohmic contact layer 141, the reflective conductive film 142, the stress relieving layer 143, and the conductive barrier layer 144 can form the reflective electrode 140.

An ohmic contact layer 141 may be disposed between the reflective conductive layer 142 and the second conductive semiconductor layer 130 so that stress relaxation between the conductive barrier layer 144 and the reflective conductive layer 142 Layer (143 in FIG. 1E) may be disposed. The ohmic contact layer (141 in FIG. 1E) and the stress relieving layer (143 in FIG. 1E) can have a thinner thickness than the reflective conductive film 142, and the illustration is omitted. In this embodiment, it can be understood that the ohmic contact layer (141 in FIG. 1E) and the stress relieving layer (143 in FIG. 1E) are included in the reflective conductive film 142.

The angle a formed between the side surface of the reflective conductive film 142 and the surface of the second semiconductor layer 130 is set to a sufficient thickness of the reflective conductive film 142 and the thickness of the conductive barrier layer 142 144 to prevent cracking. The angle β formed between the side surface of the conductive barrier layer 144 and the surface of the second semiconductor layer 130 is set to be equal to the angle α between the side surface of the reflective conductive film 142 and the surface of the second semiconductor layer 130 ). This is because as the conductive barrier layer 144 is formed through isotropic deposition as described with reference to FIG. 1D and extending into the cave (160b in FIG. 1d) in the mask pattern (160 in FIG. 1d) Since the thickness can be reduced very gently toward the edge portion of the substrate 144.

The thickness t3 of the conductive barrier layer 144 formed on the surface of the second conductivity type semiconductor layer 130 is smaller than the thickness t1 formed on the upper surface of the reflective conductive layer 142, The thickness t2 formed on the side surface of the reflective metal layer 142 may be smaller than the thickness t3 formed on the surface of the second conductivity type semiconductor layer 130. [ In addition, as described above, the thickness t3 formed on the surface of the second conductivity type semiconductor layer 130 of the conductive barrier layer 144 can be gradually reduced toward the edge portion.

The distances L1 and L2 between the edge of the conductive barrier layer 144 and the edge of the reflective conductive film 142 can be uniform over the entire circumference of the reflective conductive film 142. [ In particular, the edge of the conductive barrier layer 144 can exhibit a smooth profile without defects such as tearing or hanging up.

3A to 3C are SEM photographs showing actual examples of forming the reflective electrode.

Referring to FIGS. 3A to 3C, a photoresist pattern 160 having a thickness of about 5.3 mu is formed on the semiconductor layer 130. The photoresist pattern 160 is formed to have an opening 160a for exposing the semiconductor layer 130. [ A cave 160b extending from the opening portion 160a is formed in a portion where the photoresist pattern 160 is in contact with the semiconductor layer 130. [ Cave 160b had a width of about 2 um and a height of about 0.23 um. A reflective conductive film 142 is formed on the semiconductor layer 130 exposed in the opening 160a using the electron beam method. A conductive barrier layer 144 was formed on the reflective conductive film 142 by sputtering. The conductive barrier layer 144 formed by using the sputtering method, particularly, the edge portion is also formed in the cave 160b, while the reflective conductive film 142 formed by using the electron beam method is formed in the region within the opening 160a. On the other hand, the conductive barrier layer 144 is formed by alternately depositing a TiW layer and a Ti layer. The reflective conductive layer 142 and the conductive barrier layer 144 were also formed on the photoresist pattern 160 and the conductive barrier layer 144 formed using the sputtering method was also formed on the side surface of the photoresist pattern 160 . However, due to the formation of the cave 160b, the conductive barrier layer 144 formed on the semiconductor layer 130 and the conductive barrier layer 144 formed on the side of the photoresist pattern 160 are formed apart from each other without contact with each other . The conductive barrier layer 144 formed on the semiconductor layer 130 which is not in contact with the reflective conductive layer 142 and the conductive barrier layer 144 is removed A smooth edge profile can be displayed without edge defects such as tearing or hanging up. In addition to this, contamination such as generation of a particle caused by an edge failure can be prevented.

4A to 4E are plan views and sectional views illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention. Each section is taken along the cutting line of the relevant plan view. The structure described with reference to Fig. 2 has been applied to the light emitting diode according to this embodiment.

Referring to FIG. 4A, the first conductive semiconductor layer 110 may be disposed on the substrate 100. A plurality of mesas MS including the active layer 120 and the second conductivity type semiconductor layer 130 may be disposed on the first conductivity type semiconductor layer 110. Mesa (MS) can have a stripe shape parallel to each other. In addition, the side surface of the mesa (MS) can be inclined so that the width of the mesa (MS) becomes narrower toward the upper part. After the mesa (MS) is formed, the edges of the exposed first conductivity type semiconductor layer 110 may be additionally etched to expose the upper surface of the substrate 100. At this time, the side surfaces of the first conductivity type semiconductor layer 110 may also be inclined.

A conductive barrier layer 144 may be disposed on the second conductive semiconductor layer 130 so as to cover the reflective conductive layer 142 and the upper and side surfaces of the reflective conductive layer 142 and the second conductive semiconductor layer 130. The ohmic contact layer 141 may be disposed between the reflective conductive layer 142 and the second conductive semiconductor layer 130 and the stress relieving layer 143 may be disposed between the conductive barrier layer 144 and the reflective conductive layer 142. [ May be disposed. The ohmic contact layer 141, the reflective conductive film 142, the stress relieving layer 143, and the conductive barrier layer 144 can form the reflective electrode 140. The reflective electrode 140 may be formed using the method described with reference to FIGS. 1C and 1D. In one embodiment, the ohmic contact layer 141 is made of Ni, the reflective conductive layer 142 is made of Ag, the stress relieving layer 143 is made of Ni / Au, and the conductive barrier layer 144 is made of Ni / Ti / Ni / Ti .

A first insulating layer 200 may be formed on the reflective electrode 140. An opening 200b exposing a part of the reflective electrode 140 may be formed in the first insulating layer 200. [ At the same time, the first conductive semiconductor layer 110 exposed between the mesas MS and the first conductive semiconductor layer 110 exposed adjacent to the mesas MS located at both ends of the first insulating semiconductor layer 110 The openings 200a may be formed. The plurality of openings 200b may be formed, and at least one of the openings 200b may be formed on each mesa MS. The openings 200b are formed on the mesas MS one by one. However, the openings 200b may be formed on each mesa MS. In addition, although the opening 200a is shown in the form of a stripe, it is not limited thereto and may have a shape such as a hole.

The first insulating layer 200 may be an oxide film such as SiO2 formed using a technique such as chemical vapor deposition (CVD), a nitride film such as SiN, a fluoride film such as MgF2, or a complex layer thereof. As an example, the first insulating layer 200 may be formed of a DBR (Distributed Bragg Reflector) as an insulating reflection layer having a high reflectivity by alternately stacking a low refractive index material layer and a high refractive index material layer. For this purpose, a plurality of layers such as SiO2 / TiO2 and SiO2 / Nb2O5 may be laminated. When the first insulating layer 200 is formed of an insulating reflective layer, the light generated from the active layer 120 may be reflected to be emitted toward the substrate 100.

Referring to FIG. 4B, the current spreading layer 210 may be formed on the first insulating layer 200. The current spreading layer 210 may be formed to cover the top and sides of the mesa MS and to cover the first conductivity type semiconductor layer 110 exposed between the mesas MS. As a result, the current spreading layer 210 can be connected to the first conductivity type semiconductor layer 110 through the opening 200a in the first insulating layer 200, and specifically make ohmic contact therewith. The current spreading layer 210 has an opening 210a for exposing the reflective electrode 140 and is electrically insulated from the reflective electrode 140 and the second conductive semiconductor layer 130 by the first insulating layer 200, . For this purpose, the opening 210a may be wider than the opening 200b in the first insulating layer 200. [ Accordingly, the side wall of the opening 210a may be located on the first insulating layer 200 near the opening 210a.

The current spreading layer 210 may include a highly reflective metal layer 211 and a protective layer 212 thereon. The highly reflective metal layer 211 may include an Al layer, and the protective layer 212 may be a single layer or a composite layer of Ni, Cr, Au, Ti, or the like. Further, an adhesive layer (not shown) such as Ti, Cr or Ni may be formed on the bottom of the highly reflective metal layer 211. As an example, current spreading layer 210 may comprise a multilayer structure such as Ti / Al / Ti / Ni / Au, Cr / Al / Cr / Ni / Au, or Cr / Al / Ni / Ti / Ni / Lt; / RTI > When the current spreading layer 210 includes the highly reflective metal layer 211, light emitted from the active layer 120 may be reflected to be emitted toward the substrate 100.

Referring to FIG. 4C, a second insulating layer 230 may be formed on the current spreading layer 210. The second insulating layer 230 may have an opening 230a exposing the reflective electrode 140. [ The second insulating layer 230 may also cover the sidewall of the opening (210a in Fig. 4B) of the current spreading layer 210. [ Meanwhile, the second insulating layer 230 has an opening 230b spaced apart from the opening 230a and exposing the current-spreading layer 210. The second insulating layer 230 may be formed using an inorganic material such as an oxide insulating layer or a nitride insulating layer, or a polymer such as polyimide, Teflon, or parylene.

Referring to FIGS. 4D and 4E, the first pad 240 and the second pad 250 may be formed on the second insulating layer 230. FIG. The first pad 240 is formed to cover the opening 230b in the second insulating layer 230 and may be connected to the current spreading layer 210 through the opening 230b. As a result, the first pad 240 can be connected to the first conductive type semiconductor layer 110 through the current dispersion layer 210. The second pad 250 may be formed to cover the opening 230a in the second insulating layer 230 and may be connected to the reflective electrode 140 through the opening 230a. As a result, the second pad 250 may be connected to the second conductive type semiconductor layer 130 through the reflective electrode 140. The first pad 240 and the second pad 250 may be used as a pad for SMT (Surface Mounting Technology) or for connecting a bump for mounting a light emitting diode on a submount, a package, a printed circuit board, or the like.

The first and second pads 240 and 250 may be formed together in the same process and may be formed using, for example, a photo and etch technique, a lift-off technique, or a plating technique. The first and second pads 240 and 250 may include high conductivity metal layers 241 and 251 and pad barrier layers 242 and 252 thereon. The high barrier metal layers 241 and 251 may include Al, Cu, Ag or Au and the barrier barrier layers 242 and 252 may include Cr, Ni, TiW, TiW, Mo, Pt, Lt; / RTI > Further, an adhesive layer (not shown) such as Ti, Cr, or Ni may be formed under the high-conductivity metal layers 241 and 251. The pad barrier layers 242 and 252 may be formed to prevent the tin atoms contained in the bonding metal or solder material from diffusing into the high conductivity metal layer 241 and 251 pads and increasing the resistivity during bonding or soldering operations. have.

Thereafter, the substrate 100 is divided into unit cells to complete the light emitting diode chip. The substrate 100 may be deformed to have a thinner thickness through a thinning process before being divided into unit cells.

5A to 5E are plan views and sectional views showing a method of manufacturing a light emitting diode according to another embodiment of the present invention. Each section is taken along the cutting line of the relevant plan view.

Referring to FIG. 5A, the first conductive semiconductor layer 110 may be disposed on the substrate 100. A plurality of mesas MS including the active layer 120 and the second conductivity type semiconductor layer 130 may be disposed on the first conductivity type semiconductor layer 110. Mesa (MS) can have a stripe shape parallel to each other. In addition, the side surface of the mesa (MS) can be inclined so that the width of the mesa (MS) becomes narrower toward the upper part. 4A, the step of exposing the upper surface of the substrate 100 by further etching the edges of the first conductive semiconductor layer 110 exposed after the formation of the mesa (MS) is omitted in this embodiment .

Referring to FIG. 5B, the current spreading layer 210 may be formed on the first insulating layer 200. The current spreading layer 210 may be formed to cover the top and sides of the mesa MS and to cover the first conductivity type semiconductor layer 110 exposed between the mesas MS. As a result, the current spreading layer 210 can be connected to the first conductivity type semiconductor layer 110 through the opening 200a in the first insulating layer 200, and specifically make ohmic contact therewith. The current spreading layer 210 has an opening 210a for exposing the reflective electrode 140 and is electrically insulated from the reflective electrode 140 and the second conductive semiconductor layer 130 by the first insulating layer 200, . For this purpose, the opening 210a may be wider than the opening 200b in the first insulating layer 200. [ Accordingly, the side wall of the opening 210a may be located on the first insulating layer 200 near the opening 210a.

Referring to FIG. 5C, a second insulating layer 230 may be formed on the current spreading layer 210. The second insulating layer 230 may have an opening 230a exposing the reflective electrode 140. [ The second insulating layer 230 may also cover the sidewall of the opening (210a in Fig. 4B) of the current spreading layer 210. [ Meanwhile, the second insulating layer 230 has an opening 230b spaced apart from the opening 230a and exposing the current-spreading layer 210. The second insulating layer 230 may be formed using an inorganic material such as an oxide insulating layer or a nitride insulating layer, or a polymer such as polyimide, Teflon, or parylene.

Referring to FIGS. 5D and 5E, the first pad 240 and the second pad 250 may be formed on the second insulating layer 230. FIG. The first pad 240 is formed to cover the opening 230b in the second insulating layer 230 and may be connected to the current spreading layer 210 through the opening 230b. As a result, the first pad 240 can be connected to the first conductive type semiconductor layer 110 through the current dispersion layer 210. The second pad 250 may be formed to cover the opening 230a in the second insulating layer 230 and may be connected to the reflective electrode 140 through the opening 230a. As a result, the second pad 250 may be connected to the second conductive type semiconductor layer 130 through the reflective electrode 140. The first pad 240 and the second pad 250 may be used as a pad for SMT (Surface Mounting Technology) or for connecting a bump for mounting a light emitting diode on a submount, a package, a printed circuit board, or the like.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, This is possible.

100: substrate 110: first conductivity type semiconductor layer
120: active layer 130: second conductivity type semiconductor layer
140: reflective electrode 141: ohmic bonding layer
142: reflective conductive film 143: stress relieving layer
144: conductive barrier layer MS: mesa
200: first insulation layer 210: current dispersion layer
230: second insulating layer 240: first pad
250: second pad

Claims

Forming a mask pattern having an opening for exposing a surface of a semiconductor layer on a semiconductor layer, the mask pattern including a cave extending from the opening in a portion of the mask pattern contacting the semiconductor layer;
Forming a reflective conductive film in the opening; And
And forming a conductive barrier layer covering the surface and the side surface of the reflective conductive film on the reflective conductive film.

The method according to claim 1,
Wherein the conductive barrier layer is formed using a vapor deposition method having a lower deposition direction of the deposition beam than the vapor deposition method of forming the reflective conductive layer.

3. The method of claim 2,
Wherein the reflective conductive film is formed using an electron beam evaporation method.

3. The method of claim 2,
Wherein the conductive barrier layer is formed using a sputtering method.

The method according to claim 1,
Wherein the reflective conductive film comprises Al, an Al alloy, Ag, or an Ag alloy.

The method according to claim 1,
Wherein the conductive barrier layer comprises W, TiW, Mo, Cr, Ni, Pt, Rh, Pd, or Ti.

The method according to claim 1,
Wherein the width of the opening of the opening is smaller than the width of the bottom.

The method according to claim 1,
Wherein the conductive barrier layer is also formed in the cave.

A reflective conductive film disposed on the semiconductor layer; And
And a conductive barrier layer disposed on the reflective conductive film and covering the surface and the side surface of the reflective conductive film and extending on the semiconductor layer,
Wherein an angle between the side surface of the conductive barrier layer and the surface of the semiconductor layer is smaller than an angle formed between a side surface of the reflective conductive film and a surface of the semiconductor layer.

10. The method of claim 9,
Wherein a thickness of the conductive barrier layer is smaller than a thickness formed on a surface of the semiconductor layer in comparison with a thickness formed on an upper surface of the reflective conductive layer and is smaller than a thickness formed on a surface of the semiconductor layer, A reflective electrode formed on the light emitting diode.

10. The method of claim 9,
Wherein a distance between an edge of the conductive barrier layer and an edge of the reflective conductive film is uniform in the entire periphery of the reflective conductive film.

A reflective conductive film disposed on the semiconductor layer; And
And a conductive barrier layer disposed on the reflective conductive film and covering the surface and the side surface of the reflective conductive film and extending on the semiconductor layer,
And the edge portion of the conductive barrier layer has a smooth profile.

Forming a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer on the substrate in this order;
And a mask pattern having an opening portion for exposing the surface of the second conductivity type semiconductor layer on the second conductivity type semiconductor layer, wherein the mask pattern is formed on a portion of the mask pattern adjacent to the second conductivity type semiconductor layer Providing a cave extending from the opening;
Forming a reflective conductive film in the opening; And
And forming a conductive barrier layer covering the surface and the side surface of the reflective conductive film on the reflective conductive film.

14. The method of claim 13,
Wherein the conductive barrier layer is formed using a vapor deposition method with a lower deposition direction of the deposition beam than the deposition method of forming the reflective conductive layer.

15. The method of claim 14,
Wherein the reflective conductive film is formed using an electron beam evaporation method.

15. The method of claim 14,
Wherein the conductive barrier layer is formed using a sputtering method.

14. The method of claim 13,
Wherein the width of the opening of the opening is smaller than the width of the bottom.

14. The method of claim 13,
Wherein the conductive barrier layer is also formed in the cave.

A first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer sequentially stacked on a substrate;
A reflective conductive film disposed on the second conductive type semiconductor layer; And
And a conductive barrier layer disposed on the reflective conductive film and covering the surface and the side surface of the reflective conductive film and extending on the semiconductor layer,
Wherein the angle formed by the side surface of the conductive barrier layer and the surface of the semiconductor layer is smaller than the angle formed by the side surface of the reflective conductive film and the surface of the semiconductor layer.

20. The method of claim 19,
Wherein the thickness of the conductive barrier layer is smaller than a thickness formed on the upper surface of the reflective conductive layer and formed on the surface of the second conductive type semiconductor layer and formed on the surface of the second conductive type semiconductor layer And a thickness formed on the side of the reflective metal layer in comparison with the thickness.

20. The method of claim 19,
Wherein the distance between the edge of the conductive barrier layer and the edge of the reflective conductive film is uniform over the entire circumference of the reflective conductive film.

20. The method of claim 19,
And an edge portion of the conductive barrier layer has a smooth profile.