KR20130125609A - Light emitting diode having improved light extraction efficiency - Google Patents

Abstract

A light emitting diode is provided. The light emitting diode includes a substrate and a light emitting structure which is located on the substrate. The light emitting structure includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer which are successively arranged on the substrate, and a mesa etching region. A first electrode is arranged on the first conductive semiconductor layer which is exposed in the mesa etching region and is electrically connected. The first electrode includes a reflection layer and a low resistive layer which are successively laminated. The upper surface of the reflection layer is equal to or higher than the upper surface of the active layer. A second electrode is arranged on the second conductive semiconductor and is electrically connected.

Description

Light Emitting Diode having Improved Light Extraction Efficiency

The present invention relates to a semiconductor device, and more particularly, to a light emitting diode.

The light emitting diode includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer disposed between the n-type and p-type semiconductor layers, wherein when a forward electric field is applied to the n- Electrons and holes are injected into the active layer, and electrons injected into the active layer recombine with holes to emit light.

The electrodes respectively connected to the n-type semiconductor layer and the p-type semiconductor layer may be Au electrodes having excellent electrical conductivity. However, Au has a disadvantage in that the reflectance is not high and is a very expensive material.

The problem to be solved by the present invention is to provide a light emitting diode with improved light extraction efficiency and reduced manufacturing cost.

According to an aspect of the present invention, there is provided a light emitting diode. The light emitting diode includes a substrate and a light emitting structure positioned on the substrate. The light emitting structure includes a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer sequentially disposed on the substrate, and a mesa etching region exposing the first conductivity type semiconductor layer. A first electrode electrically connected to the first conductive semiconductor layer exposed in the mesa etching region is disposed. The first electrode may include a reflective layer and a low resistance layer, which are sequentially stacked, and an upper surface of the reflective layer may have a level equal to or higher than an upper surface of the active layer. A second electrode electrically connected to the second conductive semiconductor layer is disposed. The reflective layer may be Al, Ag, or a composite layer thereof. The low resistance layer may be an Au layer.

The first electrode may further include an ohmic contact layer disposed between the reflective layer and the first conductive semiconductor layer. The ohmic contact layer may be Cr, Ti, Rh, W, Pt, or a composite layer thereof. The first electrode may further include a barrier layer disposed between the reflective layer and the low resistance layer. The barrier layer may be Ti, W, Cr, Ni, Mo, Pt, or a composite layer thereof.

The upper surface of the reflective layer may have the same level as or higher than the upper surface of the second conductive semiconductor layer. Furthermore, the light emitting structure further includes a current spreading conductive film disposed between the second conductivity type semiconductor layer and the second electrode, and an upper surface of the reflective layer has a level equal to or higher than an upper surface of the current spreading conductive film. Can have

Sidewalls of the mesa etching region may be inclined. In addition, the sidewall of the first electrode may be inclined.

According to the present invention, the upper surface of the reflective layer provided on the first electrode may have the same level or higher than the upper surface of the active layer. In this case, the probability that the light traveling from the active layer toward the first electrode is reflected by the reflective layer and emitted to the outside may increase. This may be further increased when the upper surface of the reflective layer has the same or higher level as the upper surface of the second conductive semiconductor layer, and further, the upper surface of the current spreading conductive film. In addition, by forming a portion of the first electrode as the reflective layer, the ratio of the low resistance layer formed of a relatively expensive and relatively expensive metal in the first electrode can be reduced. Accordingly, light absorption due to the low resistance layer is reduced, thereby improving light emission efficiency, and the amount of the expensive metal forming the low resistance layer can be lowered, which may be advantageous in reducing manufacturing costs.

1A and 1B are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention, according to process steps.
2 is a cross-sectional view showing a light emitting diode according to another embodiment of the present invention.
3 is a cross-sectional view showing a light emitting diode according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms.

Where a layer is referred to herein as "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. In the present specification, directional expressions of the upper side, the upper side, the upper side, and the like can be understood as meaning lower, lower (lower), lower, and the like. That is, the expression of the spatial direction should be understood in a relative direction, and it should not be construed as definitively as an absolute direction. In addition, in this specification, "first" or "second" should not be construed as limiting the elements, but merely as terms for distinguishing the elements.

Further, in the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals designate like elements throughout the specification.

1A and 1B are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention, according to process steps.

Referring to FIG. 1A, a substrate 10 is provided. The substrate 10 may be formed of a material such as sapphire (Al ₂ O ₃ ), silicon carbide (SiC), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum nitride ₂ O ₃ ), or a silicon substrate. As an example, the substrate 10 may be a sapphire substrate. The substrate pattern 10a may be located in an upper surface of the substrate 10. The substrate pattern 10a may be formed by etching the upper surface of the substrate 10.

A buffer layer 21 may be formed on the substrate 10. In the case where the substrate 10 has a lattice constant different from that of the first conductivity type semiconductor layer, which will be described later, the buffer layer 21 is a layer formed to mitigate lattice mismatch between the substrate 10 and undoped GaN ) Layer.

The first conductive semiconductor layer 23 may be formed on the buffer layer 21. The first conductive semiconductor layer 23 may be a nitride-based semiconductor layer doped with an n-type dopant. For example, the first conductivity type semiconductor layer 23 may include a plurality of In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, x + y? 1) . Thereafter, the active layer 25 may be formed on the first conductivity type semiconductor layer 23. The active layer 25 may be a layer of In _x Al _y Ga _1-xy N (0 x 1, 0 y 1, 0 x + y 1), and may be a single quantum well structure or a multiple quantum well structure multi-quantum well (MQW). As an example, the active layer 25 may have a single quantum well structure of an InGaN layer or an AlGaN layer, or a multiple quantum well structure of a multilayer structure of InGaN / GaN, AlGaN / (In) GaN, or InAlGaN / . The second conductive semiconductor layer 27 may be formed on the active layer 25. The second conductive semiconductor layer 27 may also be a nitride semiconductor layer or a layer doped with a p-type dopant. As an example, the second conductivity-type semiconductor layer 27 is a p-type diagram in an In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) layer. It may be a layer doped with Mg or Zn as a fund. In contrast, the second conductivity-type semiconductor layer 27 may include a plurality of In _x Al _y Ga _1-xy Ns having different compositions (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). It may be provided with layers.

The buffer layer 21, the first conductivity type semiconductor layer 23, the active layer 25, and the second conductivity type semiconductor layer 27 may form a light emitting structure, and they may be formed of a metal organic chemical vapor deposition method (Metal). Organic Chemical Vapor Deposition (MOCVD), Chemical Vapor Deposition (CVD), Plasma-Enhanced Chemical Vapor Deposition (PECVD), Molecular Beam Epitaxy (MBE), Hydride Vapor Growth It can be formed using various deposition or growth methods, including (Hydride Vapor Phase Epitaxy; HVPE).

Referring to FIG. 1B, a mesa etched region (MR) may be formed in the light emitting structure to expose the first conductive semiconductor layer 23. Thereafter, the current spreading conductive layer 30 may be formed on the second conductive semiconductor layer 27. The current spreading conductive layer 30 may be a light transmissive conductive layer. As an example, ITO (Indium Tin Oxide), Ni / Au, or Cu / Au may be used. The first electrode 40 and the second electrode 50 may be formed on the first conductivity type semiconductor layer 23 and the current spreading conductive layer 30 exposed in the mesa etching region MR, respectively. have.

The first electrode 40 and the second electrode 50 may include reflective layers 43 and 53 and low resistance layers 47 and 57. The reflective layers 43 and 53 may have a higher reflectance than the low resistance layers 47 and 57 and may be Al, Al alloys, Ag, Ag alloys, or a composite layer thereof. For example, the reflective layers 43 and 53 may be layers having a higher reflectance than the low resistance layers 47 and 57 in the visible and ultraviolet regions. In detail, the reflective layers 43 and 53 may be Al layers. The low resistance layers 47 and 57 may be Au or Au alloy layers having lower resistance than the reflective layers 43 and 53.

The first electrode 40 and the second electrode 50 may have an ohmic contact layer between the reflective layers 43 and 53 and the first conductive semiconductor layer 23 or the current spreading conductive layer 30. 41, 51). The ohmic contact layers 41 and 51 are layers for ohmic contact with the first conductivity-type semiconductor layer 23 and / or the second conductivity-type semiconductor layer 27 below, and include Cr, Cr alloy, Ti, Ti alloy, Rh, Rh alloy, W, W alloy, Pt, Pt alloy, or a composite layer thereof. As an example, the ohmic contact layers 41 and 51 may be Cr layers. The ohmic contact layers 41 and 51 may be formed to a thickness of about 1 to 50 nm. For example, the ohmic contact layers 41 and 51 may be formed to a thickness of about 10 nm. The ohmic contact layers 41 and 51 may serve as an adhesion layer for stably bonding the reflective layers 43 and 53 on the lower layer.

The first electrode 40 and the second electrode 50 may have barrier layers 45 and 55 between the reflective layers 43 and 53 and the low resistance layers 47 and 57. The barrier layers 45 and 55 may reduce agglomeration or void formation due to particle migration between the reflective layers 43 and 53 and the low resistance layers 47 and 57. The reflection characteristics of (43, 53) can be maintained in a good state. The barrier layers 45 and 55 are high melting point metal films having higher melting points than the reflective layers 43 and 53, and include Ti, Ti alloys, W, W alloys, Cr, Cr alloys, Ni, Ni alloys, Mo, and Mo. Alloy, Pt, Pt alloy, or a composite layer thereof. For example, the barrier layers 45 and 55 may include lower barrier layers 45a and 55a and upper barrier layers 45b and 55b. As such, when the barrier layers 45 and 55 are multiple layers, film peeling due to tension can be suppressed. Specifically, the lower barrier layers 45a and 55a may be Cr layers, and the upper barrier layers 45b and 55b may be Ni layers.

In the first electrode 40, the upper surface 43_u of the reflective layer may have the same level as or higher than the upper surface 25_u of the active layer. In this case, the probability that the light traveling from the active layer 25 toward the first electrode 40 is reflected by the reflective layer 43 and emitted to the outside may increase. In addition, the upper surface 43_u of the reflective layer may have the same level as or higher than the upper surface 27_u of the second conductive semiconductor layer, and further, the upper surface 30_u of the current spreading conductive layer. In this case, since the probability that the light traveling from the active layer 25 toward the first electrode 40 meets the reflective layer 43 is increased, the light emission efficiency may be further increased.

Specifically, after the light flows toward the substrate 10 from the active layer 25, the light L1 reflected by the substrate pattern 10a toward the reflective layer 43 is reflected by the reflective layer 43. It can be released to the outside. The lights L2, L3, and L4 traveling from the active layer 25 toward the reflective layer 43 are partially reflected by the reflective layer 43 according to an incident angle incident to the reflective layer 43. Can be released.

On the other hand, the light L5 traveling from the active layer 25 toward the low resistance layer 47 (or the barrier layer 45) is absorbed by the low resistance layer 47 (or the barrier layer 45). Can be destroyed. However, in the present exemplary embodiment, by forming a part of the first electrode 40 as the reflective layer 43, the ratio of the low resistance layer 47 in the first electrode 40 can be lowered. Light absorption due to the low resistance layer 47 is reduced to improve light emission efficiency. In addition, the amount of Au used to form the low resistance layer 47 can be lowered, which can be advantageous for reducing manufacturing costs.

Although the first electrode 40 and the second electrode 50 have been described as having the same layer structure for the convenience of process, the present invention is not limited thereto and may have different structures.

2 is a cross-sectional view showing a light emitting diode according to another embodiment of the present invention. The light emitting diode according to the present embodiment may be similar to the light emitting diode described with reference to FIGS. 1A and 1B except as described below.

Referring to FIG. 2, when the mesa etching region MR is formed, the sidewall MR-s of the mesa etching region MR may be inclined. In other words, the sidewall MR-s of the mesa etching region may be formed to be farther away from the first electrode 40 as the upper side thereof is upward. In this case, the escape path of the light traveling from the active layer 25 toward the reflective layer 40 and reflected from the reflective layer 40 can be secured widely, so that the light emission efficiency can be further increased.

Specifically, among the lights L2, L3, and L4 having various incident angles with respect to the reflective layer 43 and traveling toward the reflective layer 43 in the active layer 25, the light is reflected by the reflective layer 43 and emitted to the outside. The proportion of light L2, L3 that can be increased.

3 is a cross-sectional view showing a light emitting diode according to another embodiment of the present invention. The light emitting diode according to the present embodiment may be similar to the light emitting diode described with reference to FIGS. 1A and 1B except as described below.

Referring to FIG. 3, when the mesa etching region MR is formed, the sidewall MR-s of the mesa etching region MR may be inclined. In addition, when the first electrode 40 is formed, the sidewall 40-s of the first electrode may be inclined. In other words, the width between the sidewall MR-s of the mesa etching region and the sidewall 40-s of the first electrode may be widened upward. In this case, the escape path of the light traveling from the active layer 25 toward the reflective layer 40 and reflected from the reflective layer 40 can be more widely secured, so that the light emission efficiency can be further increased.

In detail, among the lights L2, L3, and L4 having various incident angles with respect to the reflective layer 43, the active layer 25 may be reflected toward the reflective layer 43 and may be emitted to the outside. The proportion of possible light L2, L3, L4 may be further increased.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, This is possible.

10: substrate 10a: substrate pattern
21: buffer layer 23: first conductive semiconductor layer
25: active layer 27: second conductive semiconductor layer
30: current spreading conductive film 40, 50: electrode
41, 51: ohmic contact layer 43, 53: reflective layer
45, 55: barrier layers 47, 57: low resistance layer
MR: mesa etching area

Claims (11)

Board;
A light emitting structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer sequentially disposed on the substrate, and a mesa etching region exposing the first conductivity type semiconductor layer;
A reflective layer and a low resistance layer electrically connected to the first conductivity-type semiconductor layer exposed in the mesa etching region, and sequentially stacked, wherein an upper surface of the reflective layer has a level equal to or higher than an upper surface of the active layer; A first electrode; And
A light emitting diode comprising a second electrode electrically connected to the second conductive semiconductor layer. The method of claim 1,
The reflective layer is Al, Ag, or a light emitting diode thereof. The method of claim 1,
The low resistance layer is an Au layer light emitting diode. The method of claim 1,
The first electrode further comprises an ohmic contact layer disposed between the reflective layer and the first conductive semiconductor layer. 5. The method of claim 4,
The ohmic contact layer is a light emitting diode of Cr, Ti, Rh, W, Pt, or a composite layer thereof. The method according to claim 1 or 4,
The first electrode further comprises a barrier layer disposed between the reflective layer and the low resistance layer. The method according to claim 6,
The barrier layer is a light emitting diode of Ti, W, Cr, Ni, Mo, Pt, or a composite layer thereof. The method of claim 1,
The upper surface of the reflective layer has a level equal to or higher than the upper surface of the second conductive semiconductor layer. The method of claim 1,
The light emitting structure further includes a current spreading conductive film disposed between the second conductivity type semiconductor layer and the second electrode,
The upper surface of the reflective layer has a level equal to or higher than the upper surface of the current spreading conductive film. The method of claim 1,
Sidewalls of the mesa etching regions are inclined. 11. The method according to claim 1 or 10,
The sidewall of the first electrode is inclined light emitting diode.

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