KR20130128747A - Light emitting diode of having stress buffering layer and method of forming the same - Google Patents

Light emitting diode of having stress buffering layer and method of forming the same Download PDF

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Publication number
KR20130128747A
KR20130128747A KR1020120052722A KR20120052722A KR20130128747A KR 20130128747 A KR20130128747 A KR 20130128747A KR 1020120052722 A KR1020120052722 A KR 1020120052722A KR 20120052722 A KR20120052722 A KR 20120052722A KR 20130128747 A KR20130128747 A KR 20130128747A
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South Korea
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layer
formed
reflective
semiconductor layer
method
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KR1020120052722A
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Korean (ko)
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채종현
장종민
노원영
서대웅
갈대성
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서울바이오시스 주식회사
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Priority to KR1020120052722A priority Critical patent/KR20130128747A/en
Priority claimed from EP18158047.3A external-priority patent/EP3361517A1/en
Publication of KR20130128747A publication Critical patent/KR20130128747A/en

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Abstract

Disclosed are a light emitting diode in which a stress relaxation layer is formed and a method of manufacturing the same. A reflective pattern including a stress relaxation layer is formed on the light emitting structure in which the first semiconductor layer, the active layer, and the second semiconductor layer are formed. The reflective pattern has a reflective metal layer, a stress relaxation layer and a conductive barrier layer. The stress relaxation layer is equal to or larger than the thermal expansion coefficient of the conductive barrier layer and has a thermal expansion coefficient equal to or lower than the thermal expansion coefficient of the reflective metal layer. Therefore, the stress generated in the coefficient of thermal expansion of the reflective metal layer and the conductive barrier layer is absorbed by the stress relaxation layer. Through this, various types of light emitting diode modules may be formed.

Description

Light Emitting Diode Of Having Stress Buffering Layer And Method Of Forming The Same

The present invention relates to a light emitting diode, and more particularly, to a light emitting diode including a stress relaxation layer and a method of manufacturing the same.

A light emitting diode is an element having an n-type semiconductor layer, a p-type semiconductor layer and an active layer positioned between the n-type and p-type semiconductor layers, when the forward electric field is applied to the n-type and p-type semiconductor layers Electrons and holes are injected into the active layer, and electrons and holes injected into the active layer recombine to emit light.

In addition, the light emitting diode may include a reflective layer depending on the shape of the chip. That is, in the case of the flip chip type, light is emitted through the substrate. Therefore, after the semiconductor layer is formed on the substrate, a metal reflective layer is introduced over the semiconductor layer or the current spreading layer, and light is reflected from the reflective layer.

1 is a cross-sectional view showing a light emitting diode in which a reflective layer is introduced according to the prior art.

Referring to FIG. 1, an ohmic layer 20 and a reflective layer 30 are provided on the mesa layer 10. In addition, the two barrier layers 40 surround the side surfaces of the ohmic layer 20 and surround the upper and side surfaces of the reflective layer 30.

The mesa layer 10 is an epitaxially grown region, and the ohmic layer 20 is made of a conductive metal or a conductive oxide. In addition, the reflective layer 30 reflects light generated in the mesa layer 10 or the stacked structure below it. Ag (silver) or Al (aluminum) is used as the reflective layer 30.

The barrier layer 40 surrounding the top and sidewalls of the reflective layer 30 has a structure in which the first barrier layer 40A and the second barrier layer 40B are alternately formed. The first barrier layer 40A comprises nickel and the second barrier layer 40B comprises W (tungsten) or TiW (titanium tungsten). The barrier layer 40 prevents diffusion of metal constituting the reflective layer 30. However, the reflective layer 30 has a higher coefficient of thermal expansion than the barrier layer 40. For example, the coefficient of thermal expansion of Ag is 18.9um · m -1 · K at room temperature is 1, the coefficient of thermal expansion of W is 4.5um · m -1 · K at room temperature for-1. In other words, the reflective layer 30 and the barrier layer 40 have a high thermal expansion coefficient difference.

The difference in coefficient of thermal expansion appearing between the reflective layer 30 and the barrier layer 40 acts as a stress on the reflective layer 30. Therefore, stress is applied to the reflective layer 30 under the same temperature condition, and a problem arises in that the reflective layer 30 is separated from the ohmic layer 20 or the mesa layer 10 under the action of the stress.

An object of the present invention is to provide a light emitting diode including a stress relaxation layer.

In addition, another object of the present invention is to provide a method of forming a light emitting diode including a stress relaxation layer.

One aspect of the present invention to achieve the above object is a first semiconductor layer formed on a substrate; An active layer formed on the first semiconductor layer and forming light; A second semiconductor layer formed on the active layer and having a conductivity type complementary to the first semiconductor layer; And a reflection pattern formed on the second semiconductor layer, reflecting light formed in the active layer, and including a reflection pattern absorbing stress generated from a difference in coefficient of thermal expansion between dissimilar metal films.

In addition, another aspect of the present invention to achieve the above object is a step of sequentially forming a first semiconductor layer, an active layer and a second semiconductor layer on a substrate; Etching the second semiconductor layer and the active layer to form a mesa region exposing a surface of the first semiconductor layer; And forming a reflection pattern formed on the second semiconductor layer, reflecting light formed in the active layer, and absorbing a stress generated in a difference in coefficient of thermal expansion between dissimilar metal films. Provide a method.

According to the present invention, a reflective pattern including a stress relaxation layer is formed on the light emitting structure including the first semiconductor layer, the active layer, and the second semiconductor layer.

The reflective pattern includes a reflective metal layer, a stress relaxation layer and a conductive barrier layer. The stress relaxation layer has a smaller coefficient of thermal expansion than the reflective metal layer and a larger coefficient of thermal expansion than the conductive barrier layer. Therefore, the stress generated by the difference in the coefficient of thermal expansion of the reflective metal layer and the conductive barrier layer is absorbed in the stress relaxation layer.

In addition, deterioration of the characteristics of the second semiconductor layer through side diffusion of the reflective metal layer is prevented by the conductive barrier layer.

Through the absorption of stress, the influence of heat generated in the continuous use environment of the light emitting diode can be reduced.

In addition, the reflective metal layer, the stress relaxation layer, and the conductive barrier layer may be formed through a continuous deposition process in the space formed by the formation of the photoresist pattern. This has the advantage of lowering the cost of processing.

The technical effects of the present invention are not limited to those mentioned above, and other technical effects not mentioned can be clearly understood by those skilled in the art from the following description.

1 is a cross-sectional view showing a light emitting diode in which a reflective layer is introduced according to the prior art.
2 is a cross-sectional view of a substrate for fabricating a light emitting diode according to a first embodiment of the present invention.
3 to 5 are cross-sectional views illustrating a method of manufacturing the patterned substrate shown in FIG. 2 according to the first embodiment of the present invention.
6 is a cross-sectional view illustrating a light emitting diode according to a second embodiment of the present invention.
7 to 12 are cross-sectional views illustrating a method of manufacturing the light emitting diode shown in FIG. 6 according to a second embodiment of the present invention.
13 to 17 are plan views and cross-sectional views illustrating a light emitting diode module to which the structure of FIG. 6 is applied, according to a third embodiment of the present invention.
18 to 20 are plan views and cross-sectional views illustrating a light emitting diode module to which the structure of FIG. 6 is applied, according to a fourth embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms.

Where a layer is referred to herein as "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. In addition, in the present specification, the directional expression of the upper portion, the upper portion, and the upper surface may be understood as the meaning of the lower portion, the lower portion, the lower surface, and the like. That is, the expression of the spatial direction should be understood in a relative direction, and it should not be construed as definitively as an absolute direction.

In the present embodiments, "first "," second ", or "third" is not intended to impose any limitation on the elements, but merely as terms for distinguishing the elements.

Further, in the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals designate like elements throughout the specification.

First Embodiment

2 is a cross-sectional view of a substrate for fabricating a light emitting diode according to a first embodiment of the present invention.

Referring to FIG. 2, a patterned substrate 90 is disclosed. The patterned substrate 90 has a substrate 50 and an antireflection film 60.

A recess 70 is disclosed that is recessed in a substantially circular or elliptical shape on the substrate 50. In particular, the depression 70 has an aspect of a regular pattern. The regular pattern may be an island type having a constant distance between adjacent patterns, and may be a line type.

The substrate 50 includes sapphire (Al 2 O 3 ), silicon carbide (SiC), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium oxide (Ga 2 O 3 ) or silicon. Specifically, the substrate 50 may be a sapphire substrate.

An anti-reflection film 60 is formed between the recesses 70. The anti-reflection film 60 is provided to minimize reflection of light incident toward the substrate 50. When the substrate 50 is made of sapphire material, the anti-reflection film 60 is selected from a material having a refractive index of 1.7 to 2.2. In particular, the anti-reflection film 60 is preferably composed of a silicon nitride film having a refractive index of 2.0 to 2.1.

In addition, when the wavelength of the incident light is λ, the thickness of the anti-reflection film 60 is preferably set to an integer multiple of λ / 4. However, the thickness of the antireflection film 60 may have a deviation of ± 30% from an integer multiple of λ / 4.

3 to 5 are cross-sectional views illustrating a method of manufacturing the patterned substrate shown in FIG. 2 according to the first embodiment of the present invention.

Referring to FIG. 3, an antireflection film 60 is formed on the substrate 50. The anti-reflection film 60 is preferably a silicon nitride film, and when the wavelength is λ, it is applied at an integer multiple of λ / 4. However, the thickness to be applied does not depart from the spirit of the present embodiment even if the thickness is varied by ± 30% at an integer multiple of λ / 4.

Referring to FIG. 4, a photoresist is applied on the formed antireflection film 60, and a photoresist pattern 80 is formed. The formed photoresist pattern 80 may have a substantially hemispherical shape. The shape of the photoresist pattern 80 determines the shape of the depression 70 disclosed in FIG. 2. Exposure and development of the applied photoresist are performed to form the hemispherical photoresist pattern 80. Thus, a substantially rectangular photoresist pattern is formed on the cross sectional view. Next, a reflow process for the photoresist is performed. Through the reflow, the photoresist having a viscosity is formed of a coherent force between molecules to form a photoresist pattern 80 having a substantially hemispherical shape.

Subsequently, an etching process is performed using the hemispherical photoresist pattern 80 as an etching mask. The etching process preferably uses anisotropic dry etching. Therefore, etching is enhanced in the areas opened by the photoresist pattern 80. However, since the photoresist pattern 80 has a hemispherical shape, the degree of etching decreases from the edge of the hemisphere to the central region. In addition, as the etching proceeds, the hemispherical photoresist pattern 80 is gradually removed. Accordingly, the recessed portion 70 recessed in a hemispherical shape from the surface is formed around the spaced space between the photoresist patterns 80.

Referring to FIG. 5, a hemispherical recess 70 is formed through an etching process. The surface of the substrate 50 is exposed on the formed recess 70, and the anti-reflection film 60 is exposed between the recesses 70. In order to expose the anti-reflection film 60, the photoresist pattern which may remain in the etching process of FIG. 4 may be removed.

In addition, the anti-reflection film 60 remaining as necessary may be removed.

Through the above-described process, a substrate having a regular pattern and having depressions recessed from the surface can be formed.

In addition, according to the present embodiment, it will be possible to manufacture recesses having various shapes according to the shape of the photoresist pattern. For example, the photoresist may be coated and the angle of exposure may be adjusted so that the shape of each photoresist pattern has a triangular or trapezoidal shape instead of a hemispherical shape. When the etching process is performed using a photoresist pattern having a triangular or trapezoidal shape as an etching mask, depressions recessed in the form of an inverted triangle or inverted trapezoid from the surface are formed on the substrate.

However, in the present embodiment, it is possible to form recesses of various shapes recessed from the surface of the substrate, but the recesses will not depart from the spirit of the present invention as long as the recesses have a shape of a pattern having a regular arrangement therebetween.

Second Embodiment

6 is a cross-sectional view illustrating a light emitting diode according to a second embodiment of the present invention.

Referring to FIG. 6, the first semiconductor layer 110, the active layer 120, the second semiconductor layer 130, and the reflective pattern 140 are formed on the substrate 100.

The substrate 100 may be any material as long as it has a structure capable of inducing the growth of the first semiconductor layer 110. Accordingly, the substrate 100 may include sapphire (Al 2 O 3 ), silicon carbide (SiC), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), and gallium oxide. (Ga 2 O 3 ) or silicon. Specifically, the substrate 100 may be a sapphire substrate.

In addition, the substrate 100 may be a substrate which is not surface treated, and may be a patterned substrate described in the first embodiment.

In addition, the first semiconductor layer 110 is provided on the substrate 100. It is preferable that the first semiconductor layer 110 has an n-type conductivity.

In addition, the active layer 120 formed on the first semiconductor layer 110 may be a single quantum well structure in which a well layer and a barrier layer are stacked, or a multi-quantum well structure in which a well layer and a barrier layer are alternately stacked. .

The second semiconductor layer 130 is provided on the active layer 120. The second semiconductor layer 130 preferably has a p-type conductivity.

In addition, the first semiconductor layer 110, the active layer 120, and the second semiconductor layer 130 may include Si, GaN, AlN, InGaN, or AlInGaN. If the first semiconductor layer 110 includes GaN, the active layer 120 and the second semiconductor layer 130 may also include GaN. However, since the second semiconductor layer 130 has a conductivity type complementary to that of the first semiconductor layer 110, a dopant different from the first semiconductor layer 110 is introduced. That is, when a dopant having a donor function is introduced into the first semiconductor layer 110, a dopant having an acceptor function is introduced into the second semiconductor layer 130. In addition, the active layer 120 preferably includes a material for which bandgap engineering is performed to form the barrier layer and the well layer.

The reflective pattern 140 is formed on the second semiconductor layer 130.

The reflective pattern 140 has an ohmic bonding layer 141, a reflective metal layer 142, a stress relaxation layer 143, and a conductive barrier layer 144.

The ohmic bonding layer 141 may be any material that can achieve ohmic bonding between the reflective metal layer 142 and the second semiconductor layer 130. Therefore, the ohmic bonding layer 141 may include a metal material including Ni or Pt, and may include a conductive oxide such as ITO or ZnO. However, the ohmic bonding layer 141 may be omitted according to the embodiment.

The reflective metal layer 142 is formed on the ohmic bonding layer 141. The reflective metal layer 142 reflects light formed in the active layer 120. Therefore, it is selected as a material having conductivity and high reflectivity to light. The reflective metal layer 142 has Ag, Ag alloy, Al or Al alloy.

In addition, a stress relaxation layer 143 is formed on the reflective metal layer 142. The thermal expansion coefficient of the stress relaxation layer 143 is equal to or higher than the thermal expansion coefficient of the conductive barrier layer 144 and preferably has a value equal to or lower than the thermal expansion coefficient of the reflective metal layer 142. As a result, the stress generated by the difference in the coefficient of thermal expansion of the reflective metal layer 142 and the conductive barrier layer 144 may be relaxed. Therefore, the material of the stress relaxation layer 143 is differently selected depending on the selection of the material of the reflective metal layer 142 and the conductive barrier layer 144.

The conductive barrier layer 144 is formed on the stress relaxation layer 143. The conductive barrier layer 144 surrounds at least the side surface of the reflective metal layer 142 and is formed to surround the top and side surfaces of the stress relaxation layer 142. Therefore, diffusion of metal atoms or ions constituting the reflective metal layer 142 is prevented. In addition, the stress generated due to the difference in thermal expansion coefficient between the conductive barrier layer 144 and the reflective metal layer 142 is absorbed in the stress relaxation layer 143.

For example, when the reflective metal layer 142 is Al or an Al alloy, and the conductive barrier layer 144 includes W, TiW, or Mo, the stress relaxation layer 143 is formed of Ag, Cu, Ni, Pt, Ti, It may be a single layer of Rh, Pd or Cr or a composite layer of Cu, Ni, Pt, Ti, Rh, Pd or Au. In addition, when the reflective metal layer 142 is Al or Al alloy, the conductive barrier layer 144 is Cr, Pt, Rh, Pd or Ni, the stress relaxation layer 143 is a single layer of Ag or Cu, It may be a composite layer of Ni, Au, Cu or Ag.

In addition, when the reflective metal layer 142 is Ag or Ag alloy, and the conductive barrier layer 144 includes W, TiW or Mo, the stress relaxation layer 143 is formed of Cu, Ni, Pt, Ti, Rh, It may be a single layer of Pd or Cr or a composite layer of Cu, Ni, Pt, Ti, Rh, Pd, Cr or Au. In addition, when the reflective metal layer 142 is Ag or Ag alloy, and the conductive barrier layer 144 is Cr or Ni, the stress relaxation layer 143 is a single layer of Cu, Cr, Rh, Pd, TiW, Ti. Or a composite layer of Ni, Au, or Cu.

7 to 12 are cross-sectional views illustrating a method of manufacturing the light emitting diode shown in FIG. 6 according to a second embodiment of the present invention.

Referring to FIG. 7, the first semiconductor layer 110, the active layer 120, and the second semiconductor layer 130 are sequentially formed on the substrate 100.

The substrate 100 includes sapphire (Al 2 O 3 ), silicon carbide (SiC), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium oxide (Ga 2 O 3 ) or silicon. Specifically, the substrate 100 may be a sapphire substrate. In addition, the substrate 100 may be a patterned substrate of the first embodiment.

In addition, the first semiconductor layer 110 is provided on the substrate 100. It is preferable that the first semiconductor layer 110 has an n-type conductivity.

In addition, the active layer 120 formed on the first semiconductor layer 110 may be a single quantum well structure in which a well layer and a barrier layer are stacked, or a multi-quantum well structure in which a well layer and a barrier layer are alternately stacked. .

The second semiconductor layer 130 is provided on the active layer 120. The second semiconductor layer 130 preferably has a p-type conductivity.

In addition, the material and configuration of the first semiconductor layer 110, the active layer 120, and the second semiconductor layer 130 are the same as described with reference to FIG. 6. Therefore, this is used.

In addition, the first semiconductor layer 110, the active layer 120, and the second semiconductor layer 130 are formed through epitaxial growth. Accordingly, it is preferable that the 110, the active layer 120, and the second semiconductor layer 130 are formed through the MOCVD process.

Referring to FIG. 8, portions of the active layer 120 and the second semiconductor layer 130 are removed according to a conventional etching process. As a result, a part of the first semiconductor layer 110 is exposed. An upper surface of the first semiconductor layer 110 is exposed through the etching process, and side surfaces of the active layer 120 and the second semiconductor layer 130 are exposed. Accordingly, a trench in which portions of the active layer 120 and the second semiconductor layer 130 are removed may be formed through the etching, and holes may be formed. That is, the mesa region 150 etched from the surface of the second semiconductor layer 130 to the surface of the first semiconductor layer 110 of FIG. 7 may have a stripe type in the form of a trench and may be a hole type.

In addition, when the mesa region 150 has a stripe type, the mesa region 150 may have a vertical profile or an inclined profile from the surface of the first semiconductor layer 110, but may be at an angle of 20 degrees to 70 degrees from the surface of the first semiconductor layer 110. It is desirable to have a slanted inclined profile. In addition, when the mesa region 150 has a substantially circular hole type, the mesa region 150 may have a vertical profile or an inclined profile from the surface of the first semiconductor layer 110, but may be 20 to 70 degrees from the surface of the first semiconductor layer 110. It is preferred to have an inclined profile tilted at an angle of degrees. If the profile is less than 20 degrees, the mesa region 150 becomes very wider at the top. Therefore, a problem arises in that the concentration of light generated on the light emitting structure is lowered. In addition, when the profile exceeds 70 degrees, the mesa region 150 has a profile close to the vertical. Thus, the effect of reflecting the generated light on the sidewalls of the films is minimal.

9, a photoresist pattern 160 is formed on the exposed first semiconductor layer 110 while forming the bottom surface of the mesa region 150. The photoresist pattern 160 may have a profile perpendicular to the surface of the first semiconductor layer 110. In some embodiments, the photoresist pattern 160 may have an overhang structure in which a width of a bottom surface is narrower than a width of an upper surface. The photoresist pattern 160 is preferably of a negative type. Thus, the exposed site has the property of crosslinking. In order to form the overhang structure, the photoresist pattern 160 is preferably exposed with a predetermined slope. In the case of the overhang structure, the separation distance between the bottom surfaces between the photoresist patterns 160 may be set to be 1 μm or more than the separation distance between the top surfaces.

Referring to FIG. 10, the reflective metal layer 142 and the stress relaxation layer 143 are sequentially stacked on the second semiconductor layer 130.

The reflective metal layer 142 includes Al, Al alloy, Ag or Ag alloy. The reflective metal layer 142 may be formed through a conventional metal deposition method. However, e-beam evaporation may be used in which most metal atoms or ions may move in a vertical direction on the surface of the second semiconductor layer 130. Through this, the metal atoms or ions may enter the spaced spaces between the photoresist patterns 160 and have anisotropy to form the reflective metal layer 142.

The thickness of the reflective metal layer 142 is preferably 100nm to 1um. If the thickness of the reflective metal layer 142 is less than 100 nm, a problem may occur in that reflection of the light formed in the active layer 120 is not smooth. In addition, when the thickness of the reflective metal layer 142 exceeds 1um, process loss due to excessive process time occurs.

If necessary, the ohmic bonding layer 141 may be formed before the formation of the reflective metal layer 142. The ohmic bonding layer 141 may include Ni, Pt, ITO, or ZnO. In addition, the thickness of the ohmic bonding layer 141 is preferably set to 0.1nm to 20nm. If the thickness of the ohmic bonding layer 141 is less than 0.1 nm, sufficient ohmic characteristics cannot be secured due to a very thin thin film. In addition, when the thickness exceeds 20 nm, the amount of light transmitted decreases, thereby causing a problem in that the amount of light reflected by the upper reflective metal layer 142 decreases.

The stress relaxation layer 143 is formed on the reflective metal layer 142.

The stress relaxation layer 143 may be formed through a conventional metal deposition method. However, it is preferable to use an electron beam deposition method having a high directivity in the deposition process. That is, the metal atoms or ions evaporated by the electron beam have directivity, have anisotropy in the spaces between the photoresist patterns 160, and may be formed of a metal film. In addition, the stress relaxation layer 143 has a lower coefficient of thermal expansion than the reflective metal layer 142 and a higher coefficient of thermal expansion than the conductive barrier layer 144 of FIG. 6. Therefore, the material of the stress relaxation layer 143 may be differently selected depending on the selection of the material of the reflective metal layer 142 and the conductive barrier layer 144. The material of the stress relaxation layer 143 is mentioned later.

When the reflective metal layer 142 and the stress relaxation layer 143 are formed by the electron beam deposition method, the side surface of the reflective metal layer 142 and the side surface of the stress relaxation layer 143 are exposed. In addition, the anisotropic deposition forms the reflective metal layer 142 and the stress relaxation layer 143 corresponding to the open area on the photoresist pattern 160.

In addition, in FIG. 10, the metal material formed on the photoresist pattern 160 is omitted in the process of forming the reflective metal layer 142 and the stress relaxation layer 143.

Referring to FIG. 11, a conductive barrier layer 144 is formed through an open area of the photoresist pattern 160.

The conductive barrier layer 144 includes W, TiW, Mo, Cr, Ni, Pt, Rh, Pd or Ti. In particular, the material constituting the conductive barrier layer 144 may be changed according to the selection of the materials of the reflective metal layer 142 and the stress relaxation layer 143.

The conductive barrier layer 144 is formed on the stress relaxation layer 143 and shields side surfaces of the reflective metal layer 142 and the stress relaxation layer 143. Therefore, the phenomenon in which the metal constituting the reflective metal layer 142 is diffused into the second semiconductor layer 130 through side diffusion is prevented. Formation of the conductive barrier layer 144 is realized through conventional metal deposition processes. However, the conductive barrier layer 144 is preferably formed through isotropic deposition. This is because the conductive barrier layer 144 has a structure surrounding the side surfaces of the stress relaxation layer 143 and the reflective metal layer 142. For example, the conductive barrier layer 144 may be formed through sputtering.

In addition, the conductive barrier layer 144 may be formed of a single layer of 100 nm or more by selecting a specific metal. In addition, the conductive barrier layer 144 may be selected by alternating two or more metals, and the thickness of each layer may be set to 20 nm or more. For example, the conductive barrier layer 144 may be formed by alternately depositing a TiW having a thickness of 50 nm and a Ni layer or a Ti layer having a thickness of 50 nm.

In addition, a Ni / Au / Ti layer may be additionally formed on the conductive barrier layer 144 for stable contact with the material thereafter.

As described above, the material of the stress relaxation layer 143 is selected according to the material of the reflective metal layer 142 and the conductive barrier layer 144. This is because the coefficient of thermal expansion of the stress relaxation layer 143 is higher than that of the conductive barrier layer 144 and lower than that of the reflective metal layer 142. Therefore, when the reflective metal layer 142 is Al or Al alloy, and the conductive barrier layer 144 includes W, TiW or Mo, the stress relaxation layer 143 is Ag, Cu, Ni, Pt, Ti, Rh It may be a single layer of Pd or Cr, or a composite layer of Cu, Ni, Pt, Ti, Rh, Pd or Au. In addition, when the reflective metal layer 142 is Al or an Al alloy and the conductive barrier layer 144 comprises Ti, Cr, Pt, Rh, Pd or Ni, the stress relaxation layer 143 is a single layer of Ag or Cu. It may be a layer or a composite layer of Ni, Au, Cu or Ag. In addition, when the reflective metal layer 142 is Ag or Ag alloy, and the conductive barrier layer 144 includes W, TiW or Mo, the stress relaxation layer 143 is Cu, Ni, Pt, Ti, Rh, Pd Or a single layer of Cr, or a composite layer of Cu, Ni, Pt, Ti, Rh, Pd, Cr, or Au. In addition, when the reflective metal layer 142 is Ag or Ag alloy, and the conductive barrier layer 144 includes Pt or Ni, the stress relaxation layer 143 is a single Cu, Cr, Rh, Pd, TiW or Ti. Layer, or a composite layer of Ni, Au, or Cu.

Referring to FIG. 12, the photoresist pattern is removed through lift-off of the photoresist pattern. Thus, the lower first semiconductor layer 130 and the upper reflective pattern 140 are exposed. In addition, the mesa region 150 is exposed through the removal of the photoresist pattern. As described above, the mesa region 150 may be a stripe type or a hole type.

Through the above-described process, the reflective pattern 140 is formed on the second semiconductor layer 130. The reflective pattern 140 includes a reflective metal layer 142, a stress relaxation layer 143, and a conductive barrier layer 144. The stress relaxation layer 143 has a smaller thermal expansion coefficient than the reflective metal layer 142 and has a larger thermal expansion coefficient than the conductive barrier layer 143. Therefore, the stress generated by the difference in thermal expansion coefficient between the reflective metal layer 142 and the conductive barrier layer 144 is absorbed in the stress relaxation layer 143.

Third Embodiment

13 to 17 are plan views and cross-sectional views illustrating a light emitting diode module to which the structure of FIG. 6 is applied, according to a third embodiment of the present invention.

Referring to FIG. 13, it is assumed in FIG. 12 that the mesa region 150 is a stripe-etched region. Subsequently, a first insulating layer 200 is formed on the entire structure of FIG. 12. The first insulating layer 200 exposes a portion of the upper surface of the reflective pattern 140 and exposes the surface of the first semiconductor layer 130. To form the first insulating layer 200, an oxide film such as SiO 2, a nitride film such as SiN, an insulating film such as MgF 2, or a DBR layer such as SiO 2 / TiO 2 (De-Bragg Reflector) is formed on the structure of FIG. 11. Subsequently, a portion of the reflective pattern 140 and the surface of the first semiconductor layer 110 are exposed through a conventional photolithography process.

13 is a cross-sectional view taken along the line AA ′ of the plan view of FIG. 13. In the sectional view, the line A-A 'is discontinuous and the portion indicated by the dotted line is not reflected on the sectional view. Discontinuities are, however, described as being continuous in cross section. Hereinafter, the same applies to FIG. 15.

In addition, in the present exemplary embodiment, three reflective patterns 140 are described as being exposed, but this is merely an example, and the number of the reflective patterns 140 exposed may be sufficiently changed.

The reflective pattern 140 is exposed in some areas, and the first semiconductor layer 110 is exposed in the mesa area 150. In addition, in the region where the reflective pattern 140 is not exposed, the first insulating layer 200 completely shields the reflective pattern 140.

Referring to FIG. 14, a conductive reflective layer 210 is formed on the first insulating layer 200. The conductive reflective layer 210 is formed of a conductive material. In addition, the conductive reflective layer 210 exposes a portion of the reflective pattern 140.

The conductive reflective layer 210 may include Al. Therefore, the first semiconductor layer 110 and the conductive reflective layer 210 are electrically connected, and the reflective pattern 140 is electrically insulated from the conductive reflective layer 210 by the first insulating layer 200.

This can be seen from the bottom cross section. That is, the reflective pattern 140 is exposed in the cross section that crosses the two exposed reflective patterns 140 in the AA ′ line, and the reflective pattern 140 is disposed in the cross section that crosses the region buried only by the conductive reflective layer 210. The first insulating layer 200 is formed on the conductive layer 200, and the conductive reflective layer 210 is formed on the first insulating layer 200. In addition, the conductive reflective layer 210 is formed on the surface of the first semiconductor layer 110 exposed in the form of a stripe in FIG. 13.

Since the conductive reflective layer 210 includes an Al material, the conductive reflective layer 210 may reflect light formed in the active layer. Thus, the conductive reflective layer 210 has a function as a reflective layer that reflects light while achieving electrical contact with the first semiconductor layer 110.

Prior to the formation of the conductive reflective layer 210, a bonding layer having the same shape as the conductive reflective layer 210 may be formed separately. The bonding layer comprises Ti, Cr or Ni. By placing the bonding layer, ohmic bonding between the conductive reflective layer 210 and the first semiconductor layer 110 is easily formed.

In addition, a passivation layer may be formed on the conductive reflective layer 210. The passivation layer may be a single layer of Ni, Cr or Au, or a composite layer thereof. The passivation layer is preferably a composite layer of Ti / Al / Ti / Ni / Au.

Referring to FIG. 15, a second insulating layer 220 is formed on the structure of FIG. 14. A portion of the conductive reflective layer 210 is exposed through the second insulating layer 220, and a portion of the reflective pattern 140 is also exposed. The reflective pattern 140 is electrically connected to the second semiconductor layer 130, and the conductive reflective layer 210 is electrically connected to the first semiconductor layer 110. Therefore, the electrical path between the first semiconductor layer 110 and the second semiconductor layer 130 is opened through the second insulating layer 220.

The second insulating layer 220 may be any type of insulating material. Accordingly, oxide-based insulators, nitride-based insulators, polymer-based polyimide, Teflon or parylene may be used.

Referring to FIG. 16, a first pad 230 and a second pad 240 are formed on the structure of FIG. 15. The first pad 230 is electrically connected to the conductive reflective layer 210 exposed in FIG. 15. Thus, the first pad 230 and the first semiconductor layer 110 are electrically connected. This means that the first semiconductor layer 110 is electrically connected to an external power source or power supply line through the first pad 230. In addition, the second pad 240 is electrically connected to the reflective pattern 140 exposed in FIG. 15. Thus, the second pad 240 and the second semiconductor layer 130 are electrically connected. This means that the second semiconductor layer 130 is electrically connected to an external power source or power supply line through the second pad 240.

The first pad 230 and the second pad 240 may be formed of a layer including Ti, Cr, or Ni and a double layer structure of Al, Cu, Ag, or Au. In addition, the first pad 230 and the second pad 240 may be formed by using a lift-off process of depositing a metal material between the patterned space of the photoresist and the patterned separation space and then removing it. In addition, after forming a double layer or a single layer of a metal film, a pattern through a conventional photolithography process may be formed, and may be formed through dry etching or wet etching using the same as an etching mask. However, the etchant during dry etching and wet etching may be set differently according to the material of the metal to be etched.

17 is a cross-sectional view taken along the line B-B 'and a cross-sectional view taken along the line C-C'.

First, the line B-B 'cuts an area where the first pad 230 is formed. The first pad 230 is electrically connected to the exposed conductive reflective layer 210.

In addition, the C-C ′ line cuts the region where the second pad 240 is formed. The second pad 240 is electrically connected to the exposed reflection pattern 140.

As a result, it can be seen that the first pad 230 is electrically connected to the first semiconductor layer 110 and the second pad 240 is electrically connected to the second semiconductor layer 130.

Through the above-described process, a stress relaxation layer may be introduced into the reflective pattern, the first semiconductor layer may be exposed in a stripe type, and a light emitting diode module may be formed by achieving electrical contact.

Fourth Embodiment

18 to 20 are plan views and cross-sectional views illustrating a light emitting diode module to which the structure of FIG. 6 is applied, according to a fourth embodiment of the present invention.

Referring to FIG. 18, in FIG. 12 of the second embodiment, the mesa region 150 is formed in a hole type. Thus, the first semiconductor layer 110 is exposed in a substantially circular shape.

Subsequently, the first insulating layer 200 is formed on the entire surface of the structure of FIG. 12. The first insulating layer 200 exposes a portion of the upper surface of the reflective pattern 140 and exposes the surface of the first semiconductor layer 110. The formation of the first insulating layer 200 is the same as described with reference to FIG. 13. Therefore we use it.

18 is a cross-sectional view of the plan view of FIG. 18 taken along the direction D-D '. In the sectional view, the line D-D 'is discontinuous on the dotted line and is formed by connecting solid lines. Therefore, the dotted line portion is not reflected in the sectional view, but only the solid line portion is reflected in the sectional view.

The reflective pattern 140 is exposed in some areas, and the first semiconductor layer 110 is exposed in the mesa area 150. In addition, in the region where the reflective pattern 140 is not exposed, the first insulating layer 200 completely shields the reflective pattern 140.

In addition, in FIG. 18, the mesa region 150 of the hole type is exaggerated for the convenience of description. Therefore, according to the embodiment, the number and shape of the hole-type mesa regions 150 may be sufficiently changed.

Referring to FIG. 19, a conductive reflective layer 210 is formed on the first insulating layer 200. The conductive reflective layer 210 is formed of a conductive material. In addition, the conductive reflective layer 210 exposes a portion of the reflective pattern 140.

The conductive reflective layer 210 may include Al. Therefore, the first semiconductor layer 110 and the conductive reflective layer 210 are electrically connected, and the reflective pattern 140 is electrically insulated from the conductive reflective layer 210 by the first insulating layer 200.

This can be seen from the bottom cross section. That is, the reflective pattern 140 is exposed in the cross section that crosses the two exposed reflective patterns 140 in the DD 'line, and the reflective pattern 140 is exposed in the cross section that crosses the region buried only by the conductive reflective layer 210. The first insulating layer 200 is formed on the conductive layer 200, and the conductive reflective layer 210 is formed on the first insulating layer 200. In addition, the conductive reflective layer 210 is formed on the surface of the first semiconductor layer 110 exposed in the form of a hole in FIG. 19.

Since the conductive reflective layer 210 includes an Al material, the conductive reflective layer 210 may reflect light formed in the active layer. Thus, the conductive reflective layer 210 has a function as a reflective layer that reflects light while achieving electrical contact with the first semiconductor layer 110.

Prior to the formation of the conductive reflective layer 210, a bonding layer having the same shape as the conductive reflective layer 210 may be formed separately. The bonding layer comprises Ti, Cr or Ni. The ohmic bonding is easily formed between the conductive reflective layer 210 and the first semiconductor layer 110 through the publication of the bonding layer.

In addition, a passivation layer may be formed on the conductive reflective layer 210. The passivation layer may be a single layer of Ni, Cr or Au, or a composite layer thereof. The passivation layer is preferably a composite layer of Ti / Al / Ti / Ni / Au.

Referring to FIG. 20, a second insulating layer 220 is formed. A portion of the conductive reflective layer 210 is exposed through the second insulating layer 220, and a portion of the reflective pattern 140 is also exposed. The reflective pattern 140 is electrically connected to the second semiconductor layer 130, and the conductive reflective layer 210 is electrically connected to the first semiconductor layer 110. Therefore, the electrical path between the first semiconductor layer 110 and the second semiconductor layer 130 is opened through the second insulating layer 220.

The material and the formation of the second insulating layer 220 are the same as described with reference to FIG. 15. Therefore, this is used.

Subsequently, as illustrated in FIG. 16, the first pad 230 and the second pad 240 are formed. The first pad 230 is electrically connected to the conductive reflective layer 210 exposed in FIG. 20. Thus, the first pad 230 and the first semiconductor layer 110 are electrically connected. This means that the first semiconductor layer 110 is electrically connected to an external power source or power supply line through the first pad 230. In addition, the second pad 240 is electrically connected to the reflective pattern 140 exposed in FIG. 20. Thus, the second pad 240 and the second semiconductor layer 130 are electrically connected. This means that the second semiconductor layer 130 is electrically connected to an external power source or power supply line through the second pad 240.

Through the above-described process, a stress relaxation layer may be introduced into the reflective pattern, the first semiconductor layer may be exposed in a hole type, and a light emitting diode module may be formed by achieving electrical contact.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, This is possible.

100 substrate 110 first semiconductor layer
120: active layer 130: second semiconductor layer
140: reflection pattern 141: ohmic bonding layer
142: reflective metal layer 143: stress relaxation layer
144 conductive barrier layer 150 mesa region
200: first insulating layer 210: conductive reflective layer
220: second insulating layer 230: first pad
240: second pad

Claims (21)

  1. Board;
    A first semiconductor layer formed on the substrate;
    An active layer formed on the first semiconductor layer and forming light;
    A second semiconductor layer formed on the active layer and having a conductivity type complementary to the first semiconductor layer; And
    And a reflective pattern formed on the second semiconductor layer and reflecting light formed in the active layer, the reflective pattern absorbing stress generated by a difference in coefficient of thermal expansion between dissimilar metal films.
  2. The method of claim 1,
    And said substrate is a patterned substrate having recesses recessed from a surface thereof.
  3. The light emitting diode of claim 2, wherein the depression has a hemispherical shape, a triangle shape, or a trapezoid shape.
  4. Light-emitting diodes, characterized in that the anti-reflection layer formed on the substrate between the depressions.
  5. The method of claim 1,
    The reflective pattern may include a reflective metal layer formed on the second semiconductor layer and reflecting light;
    A stress relaxation layer formed on the reflective metal layer to absorb stress generated by the difference in thermal expansion coefficient; And
    And a conductive barrier layer formed on the stress relaxation layer and shielding side surfaces of the reflective metal layer and the stress relaxation layer.
  6. The method of claim 5,
    The thermal expansion coefficient of the said stress relaxation layer is more than the thermal expansion coefficient of the said conductive barrier layer, and is less than the thermal expansion coefficient of the said reflective metal layer, The light emitting diode characterized by the above-mentioned.
  7. The method of claim 5,
    The reflective metal layer is a light emitting diode comprising Al, Al alloys, Ag or an alloy of Ag.
  8. The method of claim 7, wherein
    The conductive barrier layer includes W, TiW, Mo, Ti, Cr, Pt, Rh, Pd or Ni.
  9. 9. The method of claim 8,
    When the reflective metal layer comprises Al or Al alloy and the conductive barrier layer comprises W, TiW or Mo, the stress relaxation layer is a single layer of Ag, Cu, Ni, Pt, Ti, Rh, Pd or Cr. Or a composite layer of Cu, Ni, Pt, Ti, Rh, Pd, or Au.
  10. 9. The method of claim 8,
    When the reflective metal layer comprises Al or Al alloy and the conductive barrier layer comprises Ti, Cr, Pt, Rh, Pd or Ni, the stress relaxation layer is a single layer of Ag or Cu, or Ni, Au, A light emitting diode comprising a composite layer of Cu or Ag.
  11. 9. The method of claim 8,
    When the reflective metal layer comprises Ag or Ag alloy and the conductive barrier layer comprises W, TiW or Mo, the stress relaxation layer is a single layer of Cu, Ni, Pt, Ti, Rh, Pd or Cr, or A light emitting diode comprising a composite layer of Cu, Ni, Pt, Ti, Rh, Pd, Cr or Au.
  12. 9. The method of claim 8,
    When the reflective metal layer comprises Ag or Ag alloy and the conductive barrier layer comprises Pt or Ni, the stress relaxation layer is a single layer of Cu, Cr, Rh, Pd, TiW or Ti, Ni, Au or A light emitting diode comprising a composite layer of Cu.
  13. The method of claim 5,
    The reflective pattern further comprises an ohmic junction layer formed under the reflective metal layer.
  14. The method of claim 13,
    The ohmic bonding layer includes Ni, Pt, ITO or ZnO.
  15. The method of claim 1,
    The side profile of the active layer and the second semiconductor layer is characterized in that the inclined 20 to 70 degrees with respect to the surface of the first semiconductor layer.
  16. Sequentially forming a first semiconductor layer, an active layer, and a second semiconductor layer on the substrate;
    Etching the second semiconductor layer and the active layer to form a mesa region exposing a surface of the first semiconductor layer; And
    Forming a reflective pattern formed on the second semiconductor layer, reflecting light formed in the active layer, and absorbing a stress generated by a difference in thermal expansion coefficient between dissimilar metal films; .
  17. 17. The method of claim 16,
    The forming of the reflective pattern may include forming a photoresist pattern on the mesa region;
    Forming a reflective metal layer on the second semiconductor layer through a space opened by the photoresist pattern;
    Forming a stress relaxation layer on the reflective metal layer to absorb stresses generated by a difference in thermal expansion coefficient;
    Forming a conductive barrier layer surrounding the top and side surfaces of the stress relief layer and surrounding the side surface of the reflective metal layer; And
    And removing the photoresist pattern.
  18. 18. The method of claim 17,
    The photoresist pattern is a method of forming a light emitting diode, characterized in that the width of the upper overhang structure than the width of the lower.
  19. 18. The method of claim 17,
    And the reflective metal layer and the stress relaxation layer are formed through anisotropic deposition, and the barrier layer is formed through isotropic deposition.
  20. 17. The method of claim 16,
    And the mesa region is a stripe type.
  21. 17. The method of claim 16,
    The mesa region is a method of forming a light emitting diode, characterized in that the hole type.
KR1020120052722A 2012-05-17 2012-05-17 Light emitting diode of having stress buffering layer and method of forming the same KR20130128747A (en)

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KR1020120052722A KR20130128747A (en) 2012-05-17 2012-05-17 Light emitting diode of having stress buffering layer and method of forming the same

Applications Claiming Priority (21)

Application Number Priority Date Filing Date Title
KR1020120052722A KR20130128747A (en) 2012-05-17 2012-05-17 Light emitting diode of having stress buffering layer and method of forming the same
EP18158047.3A EP3361517A1 (en) 2011-09-16 2012-09-14 Light emitting diode
PCT/KR2012/007358 WO2013039344A2 (en) 2011-09-16 2012-09-14 Light emitting diode and method of manufacturing same
EP12832213.8A EP2757598B1 (en) 2011-09-16 2012-09-14 Light emitting diode
CN201610702797.9A CN106098889B (en) 2011-09-16 2012-09-14 Light emitting diode and the method for manufacturing the light emitting diode
CN201280045164.5A CN103828073B (en) 2011-09-16 2012-09-14 Light emitting diode and the method manufacturing this light emitting diode
CN201610701610.3A CN106129195B (en) 2011-09-16 2012-09-14 Light emitting diode and the method for manufacturing the light emitting diode
DE202012013620.8U DE202012013620U1 (en) 2011-09-16 2012-09-14 led
EP17165501.2A EP3223320A1 (en) 2011-09-16 2012-09-14 Light emitting diode
CN201610701538.4A CN106058000B (en) 2011-09-16 2012-09-14 Light emitting diode and the method for manufacturing the light emitting diode
JP2014530591A JP5869678B2 (en) 2011-09-16 2012-09-14 Light emitting diode and method of manufacturing the same
US14/345,382 US20140361327A1 (en) 2011-09-15 2012-09-14 Light emitting diode and method of manufacturing the same
CN201610702369.6A CN106067499B (en) 2011-09-16 2012-09-14 Light emitting diode and the method for manufacturing the light emitting diode
EP18166240.4A EP3364467B1 (en) 2011-09-16 2012-09-14 Light emitting diode
US14/671,491 US9634193B2 (en) 2011-09-16 2015-03-27 Light emitting diode and method of manufacturing the same
US14/920,790 US10297720B2 (en) 2011-09-15 2015-10-22 Light emitting diode and method of manufacturing the same
JP2016001347A JP6262778B2 (en) 2011-09-16 2016-01-06 Light emitting diode and method of manufacturing the same
US15/132,887 US10319884B2 (en) 2011-09-16 2016-04-19 Light emitting diode
US15/226,304 US10439105B2 (en) 2011-09-16 2016-08-02 Light emitting diode and light emitting diode package
JP2017239232A JP2018078310A (en) 2011-09-16 2017-12-14 Light emitting diode and method of manufacturing the same
US16/571,604 US20200013928A1 (en) 2011-09-16 2019-09-16 Light emitting diode and light emitting diode package

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160000122A (en) * 2014-06-24 2016-01-04 주식회사 아이디 Led cell, led array and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160000122A (en) * 2014-06-24 2016-01-04 주식회사 아이디 Led cell, led array and manufacturing method thereof

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