CN107808029A - A kind of analysis method of efficiently light emitting diode (LED) chip with vertical structure n-electrode pattern - Google Patents
A kind of analysis method of efficiently light emitting diode (LED) chip with vertical structure n-electrode pattern Download PDFInfo
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Abstract
The invention belongs to LED technical field, discloses a kind of analysis method of efficiently light emitting diode (LED) chip with vertical structure n-electrode pattern.Methods described is：(1) light emitting diode (LED) chip with vertical structure dummy substrate, p-electrode layer, epitaxial layer are built using Tracepro softwares successively, draws n-electrode pattern, structure contact target surface, material parameter and light source are set, the light extraction efficiency of LED chip model is analyzed, collects record data, optimizes pattern parameter；(2) the light emitting diode (LED) chip with vertical structure model of multiple Different electrodes patterns is built according to above-mentioned steps, the light data of each model of comparative analysis, obtains the optimal electrode pattern of external quantum efficiency；(3) n-electrode pattern is formed on light emitting diode (LED) chip with vertical structure surface；(4) performance test, the Comparative result with simulation, it was therefore concluded that.The method of the present invention is efficient, just can draw n-electrode pattern corresponding to the LED chip of excellent performance within a short period of time, save the time, reduced cost.
Description
Technical field
The present invention relates to a kind of analysis method of efficient light emitting diode (LED) chip with vertical structure n-electrode pattern, more particularly to by difference
Prepared by the Tracepro analogue simulations and LED chip of n-electrode figure combines, and provides a kind of efficiently vertical structure LED core
The analysis method of piece n-electrode pattern.
Background technology
LED has energy-saving and environmental protection, longevity, safety low-voltage and moulding can be used as a kind of New Solid illuminating source
Multifarious advantage, traditional LED is the horizontal structure LED prepared on a sapphire substrate, because Sapphire Substrate is non-conductive,
Therefore its electric current lateral transport in epitaxial layer, its p-electrode and n-electrode are in homonymy, it is necessary to etch p-GaN preparation p-electrodes, this
Sample not only reduces light-emitting area, simultaneously because the presence of metal electrode increases shading-area, considerably reduces going out for LED
Light efficiency.Therefore, in order to solve the above problems, researcher uses substrate transfer technology, by the LED epitaxial layers in growth substrates
The methods of by being bonded, electroplating, is transferred in the more preferable metal of photoelectric properties, highly doped conductive silicon or flexible substrate, then using sharp
Photospallation removes sapphire growth substrate, makes LED chip so need not only carry out carrying out p-GaN again from n-GaN faces light extraction
Etch and reduce light-emitting area, while n-electrode and p-electrode is ranked respectively in upper and lower two surfaces so that electric current is in Vertical Square
To transmission, light emitting diode (LED) chip with vertical structure is obtained.Shading-area of the light emitting diode (LED) chip with vertical structure due to reducing electrode, improves LED
The luminous efficiency of chip, it is a kind of chip structure for being highly suitable for preparing great power LED.
However, different n-electrode patterns can cause different CURRENT DISTRIBUTIONs to influence, the distribution of electric current is distributed to light-emitting area
There is decisive role.The electric current of light emitting diode (LED) chip with vertical structure can also upload in the horizontal direction except transmitting in vertical direction
Defeated, therefore, n-electrode pattern is an important influence factor for influenceing vertical structure LED external quantum efficiency, and is contrasted different
N-electrode pattern, it is most important to design new n-electrode pattern.
Tracepro softwares are a to be commonly used to illuminator, optical analysis, radiometric analysis and the light of photometric analysis
Line simulation softward.It can imitate all types of display systems (from back light system, to preceding light, light pipe, optical fiber, display panel and
LCD optical projection systems), figure shows, visualized operation can be carried out, and the database of 3D physical models is provided, possessing has processing
The ability of complex geometry, millions of light of definable and tracking, effective and accurately analysis is carried out to light, available for vertical
Structure LED n-electrode design and comparative analysis.
The content of the invention
It is an object of the invention to provide a kind of analysis method for being concisely and efficiently light emitting diode (LED) chip with vertical structure n-electrode pattern.
The present invention prepares different n-electrode figure light emitting diode (LED) chip with vertical structure by the simulation of Tracepro simulation softwares, can be in the short period
The external quantum efficiency of different n-electrode pattern light emitting diode (LED) chip with vertical structure is contrasted, the light emitting diode (LED) chip with vertical structure n saved in real process
The proving time of electrode pattern and preparation cost, obtain the light emitting diode (LED) chip with vertical structure n-electrode pattern of high external quantum efficiency.
The purpose of the present invention is achieved through the following technical solutions：
A kind of analysis method for being concisely and efficiently light emitting diode (LED) chip with vertical structure n-electrode pattern, comprises the following steps：
(1) light emitting diode (LED) chip with vertical structure dummy substrate is built：Lining is gone out using the 3D modeling formation function of Tracepro softwares
Bottom, the substrate are preferably the as broad as long cuboid transfer substrate in bottom surface；
The substrate is senior staff officer's conductive silicon, high-conductive metal (such as copper, aluminium, gold, nickel), flexible conductive substrates (PET, stone
Black alkene, PMMA etc.)；
(2) light emitting diode (LED) chip with vertical structure model p-electrode layer is built：Using the 3D modeling function of Tracepro softwares in substrate
On build bonded layer, p-electrode protective layer, speculum successively；The bonded layer, p-electrode protective layer, speculum are both preferably bottom surface
For the cuboid of square；
(3) light emitting diode (LED) chip with vertical structure model epitaxial layer is built：Using the 3D modeling function of Tracepro softwares in p-electrode
P-GaN epitaxial layers, quantum well layer, n-GaN epitaxial layers are built on layer successively；The p-GaN epitaxial layers, quantum well layer, outside n-GaN
It is square rectangular-shape to prolong the preferred bottom surface of layer；
(4) n-electrode pattern is drawn：Using the modeling function and Boolean calculation function of Tracepro softwares in n-GaN extensions
Layer painted on top n-electrode pattern, i.e., built needed for pattern using the modeling function of Tracepro softwares on n-GaN epitaxial layers
Solid, and by the Boolean calculation function of Tracepro softwares, obtain required pattern；The n-electrode pattern is patterned
Ti/Al/Ti layers, Ti layers, Al layers, Ti layers are built successively；
(5) light emitting diode (LED) chip with vertical structure model n-electrode light receiver target is built：Using the modeling function of Tracepro softwares
And Boolean calculation function builds light contacts target surface, the target surface and vertical structure LED core above LED chip model n-electrode
N-GaN faces are corresponding in piece；
(6) material parameter is set：Light emitting diode (LED) chip with vertical structure dummy substrate, p-electrode layer, epitaxial layer, n-electrode are set respectively
Layer material parameter and various optical property parameters；
(7) light source is set：Function is set using Tracepro softwares area source, one is respectively set in quantum well layer upper and lower surface
Individual surface source of light attribute；The surface source of light characteristic rink corner is distributed as the luminous field patterns of Lambertian, and transmitting circular cone radius is
30°；Wavelength distribution is Gaussian Profile, centre wavelength 465nm, half a width of 100nm；Transmitting form is luminous flux, and emission measure is
1000 lumens；The minimum light of each surface source of light is 10, total light number 10000, is scaled 1；
(8) light extraction efficiency of LED chip model is analyzed：Using the ray tracing function of Tracepro softwares, obtain and receive
The radiometric analysis figure of target surface；
(9) record data is collected：The proportional numerical value of the exit luminous flux and total light flux below illumination figure is recorded, and is recorded
The total light flux of required target surface；Recording figure forming area and pattern modelling simultaneously；
(10) pattern parameter is optimized：The pattern parameter includes pattern area and pattern modelling；
(11) the light emitting diode (LED) chip with vertical structure model of multiple Different electrodes patterns is built according to step (1)~(10), it is then right
Than the light data for analyzing light emitting diode (LED) chip with vertical structure model corresponding to each electrode pattern, the optimal electricity of external quantum efficiency is obtained
Pole figure case.
(12) negative photo offset plate is prepared, the negative photo offset plate contains pattern, and the pattern is simulated with Tracepro
The preferably several patterns of obtained external quantum efficiency are corresponding；
(13) standard photolithography process is utilized, on the light emitting diode (LED) chip with vertical structure surface without n-electrode, using negative photoresist
Spin coating, develop, expose, the pattern that now negative photoresist is formed is corresponding with n-electrode pattern；It is deposited again by electron beam evaporation platform
N-electrode metal；Next negtive photoresist stripping means (lift-off methods) is used, removes photoresist and the gold on photoresist surface
Category, n-electrode pattern are formed；
(14) technique is surveyed on schedule in the enterprising rower of point measurement machine, obtain the optical output power and EQE and core under several patterns
Piece illuminated diagram, compared with the result of Tracepro softwares simulation, it was therefore concluded that.
The parameter of the length, width and height of the transfer substrate of rectangle described in step (1) is generally：(50~200um) × (50~
200um) × (50~100um)
Bonded layer is AuSn eutectics, AuSi eutectics or NiSn eutectics etc. in p-electrode layer described in step (2)；
P-electrode protective layer is Cr/Pt, Cr/Pt/Au or Cr/Pt/Au/Pt etc. in p-electrode layer described in step (2)；It is described
Cr layers are close to speculum.
Described in step (2) in p-electrode layer speculum be Ag, Al, Ni/Ag, Ti/Al, Ni/Ag/Pt, Ni/Ag/Au or
Ti/Al/Au etc.；If being multilayer, last layer of metal is built on the protection layer, such as：Ni/Ag/Pt, then Pt structures are in protective layer
On.
Optical property parameter described in step (6) includes lambda1-wavelength, refractive index, absorptivity, extinction coefficient；
Light emitting diode (LED) chip with vertical structure dummy substrate, p-electrode layer, epitaxial layer, n-electrode layer material are set described in step (6) respectively
Expect parameter and various optical property parameters, be specially：Vertical stratification is set respectively using curve-fitting method or by the way of directly inputting
LED chip dummy substrate, p-electrode layer, epitaxial layer, n-electrode layer material parameter and various optical property parameters.
Optimizing pattern parameter described in step (10) is specially：Compare the upper luminous flux and luminous flux/hair of each n-electrode pattern
Irradiating luminous flux ratio, corresponding pattern is optimal during light extraction efficiency highest.
Step (13) the negative photo plate is that the negative photoresist of light area can be cured, and above, evaporation obtains
Metal film can remove in lift-off techniques.
Prior art is compared, and the present invention has advantages below and beneficial effect：
(1) present invention can simulate n-electrode pattern to vertical junction using the powerful ray tracing function of Tracepro softwares
The outgoing light homogeneity of structure LED chip, lighting area, the influence of external quantum efficiency；
(2) present invention supports the comparative analysis of more patterns, compared to the mode for directly preparing a large amount of different pattern photolithography plates, leads to
Cross Tacepro ray tracings and obtain optimal value, then carry out actual preparation, can significantly reduce the sample size of required preparation, be one
Inexpensive, the efficient comparative analysis mode of kind；
(3) present invention does not have to carry out cumbersome physical mathematics analysis, and the light that direct simulation obtains LED chip n-electrode face leads to
Amount, the method that the present invention uses is simple, strong applicability；
(4) present invention is by simulating luminous flux, the external quantum efficiency of various light emitting diode (LED) chip with vertical structure n-electrode patterns, pair sets
Counting new n-electrode pattern has significant directive significance.
Brief description of the drawings
Fig. 1 is the flow chart of the comparative analysis of the light emitting diode (LED) chip with vertical structure model n-electrode figure of the present invention；
Fig. 2 is the structural representation of the light emitting diode (LED) chip with vertical structure model of the present invention, and 1- shifts substrate layer, 2- bonded layers, 3-
P-electrode protective layer, 4- speculums, 5- epitaxial layers, 6-n electrode layers；
Fig. 3 is light emitting diode (LED) chip with vertical structure model n-type electrode pattern in embodiment 1, and n-type electrode pattern is sun floral pattern,
It is um that numerical value unit is marked in figure；
Fig. 4 is light emitting diode (LED) chip with vertical structure model n-type electrode pattern in embodiment 2, and n-type electrode pattern is quatrefoil pattern,
It is um that numerical value unit is marked in figure；
Fig. 5 is the reception target illumination figure that light emitting diode (LED) chip with vertical structure model obtains after clearing off in embodiment 1；
Fig. 6 is the reception target illumination figure that light emitting diode (LED) chip with vertical structure model obtains after clearing off in embodiment 2.
Embodiment
With reference to embodiment, the present invention is described in further detail, but the implementation of the present invention is not limited to this.
The analysis process flow chart of the light emitting diode (LED) chip with vertical structure n-electrode pattern of the present invention is as shown in figure 1, vertical structure LED
Chip model structural representation is as shown in Figure 2.
The light emitting diode (LED) chip with vertical structure model of the present invention includes transfer substrate layer 1, p-electrode layer, epitaxial layer 5, n-electrode layer 6；
The p-electrode layer includes bonded layer 2, p-electrode protective layer 3, speculum 4.
Embodiment 1
A kind of analysis method of efficiently light emitting diode (LED) chip with vertical structure n-electrode pattern, comprises the following steps：
(1) substrate of LED chip model is built：Si substrates, substrate are constructed using the modeling function of Tracepro softwares
Size is 120um × 80um × 120um, in rectangular-shape；A height of 80um；
(2) light emitting diode (LED) chip with vertical structure model p-electrode layer is built：Served as a contrast using the 3D modeling function of Tracepro softwares in silicon
Bottom builds bonded layer, p-electrode protective layer, speculum successively on (the long face equal with width)：Bonded layer size is 120um × 5um
× 120um, the size of p-electrode plate protective layer are 120um × 10um × 120um, the size of speculum be 120um × 300nm ×
120um；Each size refers to long × high × wide；
(3) light emitting diode (LED) chip with vertical structure model epitaxial layer is built：It is (long in speculum using Tracepro software modelings function
With wide equal face) on build p-GaN epitaxial layers, quantum well layer, n-GaN epitaxial layers successively：P-GaN epitaxial layer sizes are
120um × 200nm × 120um, quantum well layer size be 120um × 75nm × 120um, n-GaN epitaxial layer size be 120um ×
2um × 120um, in rectangular-shape；Each size refers to long × high × wide；
(4) n-electrode pattern is drawn：Using the modeling function and Boolean calculation function of Tracepro softwares in n-GaN extensions
Layer painted on top n-electrode pattern, electrode pattern are divided into tri- layers of Ti/Al/Ti, drawn upwards successively by n-GaN faces, three layer pattern phases
Together and overlap each other, the superiors are Ti electrode layers, and lower floor is Ti electrode layers；Such as：The n-electrode pattern be sun floral pattern (such as
Shown in Fig. 3) when, first center build a 110um × 50nm × 110um cuboids, then build 108um × 50nm ×
108um cuboids (for two cuboid length to length, wide to width, height is to height), Boolean calculation takes difference set；Then a diameter of 30um is built,
Thickness is 50nm cylinders；Then two 80um × 50nm × 3um cuboids are built, two cuboids are disposed vertically (mould above
Type is using two cuboids herein as symmetry axis)；Two 112um × 50nm × 3um cuboids are built again, vertically and with previous step
Two rectangular body Models are into 45 degree of angles；Above-mentioned all figures are taken into common factor with Boolean calculation, the pattern of acquisition is as Ti electrode layers；Together
Reason, two layers of remaining Al/Ti obtain analogue pattern according to above-mentioned steps, wherein the thickness of Al layers be 150nm, the thickness of remaining Ti layers
Spend for 200nm；
(5) light emitting diode (LED) chip with vertical structure model n-electrode light receiver target is built：Using Tracepro modeling functions in n-electrode
Simultaneously build the cuboid that size is 123um × 84um × 123um, n-electrode as cuboid while, then build chi
The very little cuboid (for two cuboid length to length, wide to width, height is to height) for 122um × 83um × 122um, utilize Tracepro softwares
Two cuboids are taken difference set by Boolean calculation function, are obtained a hollow rectangular body Model, are taken inner surface corresponding to n-GaN faces
As light receiver target surface, light receiver target surface size is 122um × 122um, the size for receiving target and chip n-GaN faces
Size it is identical；
(6) material parameter is set：Light emitting diode (LED) chip with vertical structure dummy substrate, p-electrode layer, epitaxial layer, n-electrode are set respectively
Layer material parameter and various optical property parameters；The material selection Si of substrate, refractive index are arranged to 4.5340 in the present embodiment；p-
GaN epitaxial layer, quantum well layer, n-GaN epitaxial layers select GaN material, and refractive index is arranged to 2.471；N-electrode pattern is graphical
Ti/Al/Ti layers, Al is as material, refractive index 0.66689, extinction coefficient 5.4754；Ti layers refractive index is 1.5142,
Extinction coefficient is 3.0072；Layers of material is for the blue light that wavelength is 465nm, temperature setting 300K；In addition to electrode pattern,
The extinction coefficient and extinction of other materials are not considered；Bonded layer is AuSn eutectics, AuSi eutectics or NiSn eutectics etc.；P-electrode is protected
Sheath is Cr/Pt, Cr/Pt/Au or Cr/Pt/Au/Pt etc.；The Cr layers are close to speculum；Speculum be Ag, Al, Ni/Ag,
Ti/Al, Ni/Ag/Pt, Ni/Ag/Au or Ti/Al/Au etc.；
(7) light source is set：Function is set using Tracepro softwares area source：Each area source characteristic rink corner is distributed as
Lambertian lights field pattern, and transmitting circular cone radius is 30 °；Wavelength distribution is Gaussian Profile, centre wavelength 465nm, half-breadth
For 100nm；Transmitting form is luminous flux, and emission measure is 1000 lumens；In quantum well layer upper and lower surface, one above-mentioned table is respectively set
Area source attribute, each minimum light of surface source of light are 10, total light number 10000, are scaled 1；
(8) light extraction efficiency of the LED chip of Si substrates is analyzed：Using the ray tracing function of Tracepro softwares, obtain
The radiometric analysis figure of target is received corresponding to n-GaN；Specially：System is cleared off using Tracepro softwares, to LED chip mould
Type carries out ray tracing, and the luminous flux data of target surface is obtained from the radiometric analysis figure obtained using Tracepro softwares；
(9) record data is collected：Record the proportional numerical value number of the exit luminous flux and total light flux below each illumination figure
Value, and record the required total light flux for receiving target；Recording figure forming area and pattern modelling simultaneously；
(10) optimize pattern parameter, analyze the radiometric analysis figure of same electrode pattern, analyze the upper reception target of the pattern
Luminous flux and luminous flux/emitting light flux ratio, corresponding pattern parameter value is the pattern parameter when optical property is optimal
Optimal value；
(11) the light emitting diode (LED) chip with vertical structure model of multiple Different electrodes patterns is built according to step (1)~(10), it is then right
Than the light data for analyzing light emitting diode (LED) chip with vertical structure model corresponding to each electrode pattern, the optimal electricity of external quantum efficiency is obtained
Pole figure case；
(12) negative photo offset plate is prepared, the negative photo offset plate contains pattern, and the pattern is simulated with Tracepro
The preferably several patterns of obtained external quantum efficiency are corresponding；
(13) standard photolithography process is utilized, on the light emitting diode (LED) chip with vertical structure surface without n-electrode, using negative photoresist
Spin coating, develop, expose, the pattern that now negative photoresist is formed is corresponding with preferably n-electrode pattern；Pass through electron beam evaporation again
Platform evaporating n electrode metal；Next negtive photoresist stripping means (lift-off methods) is used, removes photoresist and photoresist surface
Metal, n-electrode pattern formed；
(14) technique and semi-conductor test instrument test are surveyed on schedule in the enterprising rower of point measurement machine, obtain the light under several patterns
Power output and EQE and chip light emitting figure, compared with the result of Tracepro softwares simulation, it was therefore concluded that.
Analog result is consistent with actually measured result, determines optimal electrode pattern.
When the light emitting diode (LED) chip with vertical structure model n-type electrode pattern of the present embodiment is sun floral pattern, its figure such as Fig. 3 institutes
Show, it is um that numerical value unit is marked in figure.The reception target illumination that light emitting diode (LED) chip with vertical structure model obtains after clearing off in the present embodiment
Figure is as shown in Figure 5.
Embodiment 2
A kind of analysis method of efficiently light emitting diode (LED) chip with vertical structure n-electrode pattern, comprises the following steps：
(1) substrate of LED chip model is built：Si substrates, substrate are constructed using the modeling function of Tracepro softwares
Size is 120um × 80um × 120um, in rectangular-shape；A height of 80um；
(2) light emitting diode (LED) chip with vertical structure model p-electrode layer is built：Served as a contrast using the 3D modeling function of Tracepro softwares in silicon
Bottom builds bonded layer, p-electrode protective layer, speculum successively on (the long face equal with width)：Bonded layer size is 120um × 5um
× 120um, the size of p-electrode plate protective layer are 120um × 10um × 120um, the size of speculum be 120um × 300nm ×
120um；Each size refers to long × high × wide；
(3) light emitting diode (LED) chip with vertical structure model epitaxial layer is built：It is (long in speculum using Tracepro software modelings function
With wide equal face) on build p-GaN epitaxial layers, quantum well layer, n-GaN epitaxial layers successively：P-GaN epitaxial layer sizes are
120um × 200nm × 120um, quantum well layer size be 120um × 75nm × 120um, n-GaN epitaxial layer size be 120um ×
2um × 120um, in rectangular-shape；Each size refers to long × high × wide；
(4) n-electrode pattern is drawn：Using the modeling function and Boolean calculation function of Tracepro softwares in n-GaN extensions
Layer painted on top n-electrode pattern, electrode pattern are divided into tri- layers of Ti/Al/Ti, drawn upwards successively by n-GaN faces, three layer pattern phases
Together and overlap each other, the superiors are Ti electrode layers, and lower floor is Ti electrode layers；Such as：The n-electrode pattern is quatrefoil shape pattern
When (as shown in Figure 4), first center build a 115um × 50nm × 115um cuboids, then build 113um ×
50nm × 113um cuboids (for two cuboid length to length, wide to width, height is to height), Boolean calculation takes difference set；A 15um is built again
× 50nm × 10um cuboids, center X：- 48um, Z：- 50.5um, then the cuboid is rotated into 180 ° of duplications around Y-axis；Connect
It is 15um one radius of structure, and thickness is 50nm cylinders, bottom position X：12um, Z：12um, bottom turn to 90 °, then structure
It is 14um to build a radius, and thickness is 50nm cylinders, bottom position X：12um, Z：12um, bottom turn to 90 °, two cylinders
Body takes difference set to obtain a circular model；Circular model is replicated around Y-axis, duplication one is often rotated by 90 °, obtains four ring-types
Model, take union；Then a 40um × 50nm × 40um cuboids are built, by the cuboid and four ring moulds obtained in the previous step
Type takes difference set, obtains quatrefoil shape model；Then a 32um × 50nm × 2um cuboids, the cuboid center are built
X：30um, Z：36um, rotate X：180 °, Y：45 °, Z：180 °, then by the cuboid around 180 ° of swivel replications of Y-axis；Finally will be upper
All models for stating to obtain take union, obtain patterning Ti electrode layers；Similarly, remaining Al/Ti is obtained for two layers according to above-mentioned steps
Analogue pattern, the thickness of wherein Al layers is 150nm, the thickness of remaining Ti layers is 200nm；
(5) light emitting diode (LED) chip with vertical structure model n-electrode light receiver target is built：Using Tracepro software modeling functions in n
The cuboid that electrode one side structure size is 123um × 84um × 123um, n-electrode as cuboid while, then structure
The cuboid (for two cuboid length to length, wide to width, height is to height) that size is 122um × 83um × 122um is built, utilizes Tracepro
Two cuboids are taken difference set by software Boolean calculation function, obtain a hollow rectangular body Model, are taken in corresponding to n-GaN faces
As light receiver target surface, light receiver target surface size is 122um × 122um on surface, the size for receiving target and chip n-
The size in GaN faces is identical；
(6) material parameter is set：Light emitting diode (LED) chip with vertical structure dummy substrate, p-electrode layer, epitaxial layer, n-electrode are set respectively
Layer material parameter and various optical property parameters；The material selection Si of substrate, refractive index are arranged to 4.5340 in the present embodiment；p-
GaN epitaxial layer, quantum well layer, n-GaN epitaxial layers select GaN material, and refractive index is arranged to 2.471；N-electrode pattern is graphical
Ti/Al/Ti layers, Al is as material, refractive index 0.66689, extinction coefficient 5.4754；Ti layers refractive index is 1.5142,
Extinction coefficient is 3.0072；Layers of material is for the blue light that wavelength is 465nm, temperature setting 300K；In addition to electrode pattern,
The extinction coefficient and extinction of other materials are not considered；Bonded layer is AuSn eutectics, AuSi eutectics or NiSn eutectics etc.；P-electrode is protected
Sheath is Cr/Pt, Cr/Pt/Au or Cr/Pt/Au/Pt etc.；The Cr layers are close to speculum；Speculum be Ag, Al, Ni/Ag,
Ti/Al, Ni/Ag/Pt, Ni/Ag/Au or Ti/Al/Au etc.；
(7) light source is set：Function is set using Tracepro softwares area source：Each area source characteristic rink corner is distributed as
Lambertian lights field pattern, and transmitting circular cone radius is 30 °；Wavelength distribution is Gaussian Profile, centre wavelength 465nm, half-breadth
For 100nm；Transmitting form is luminous flux, and emission measure is 1000 lumens；In quantum well layer upper and lower surface, one above-mentioned table is respectively set
Area source attribute, each minimum light of surface source of light are 10, total light number 10000, are scaled 1；
(8) light extraction efficiency of the LED chip of Si substrates is analyzed：Using the ray tracing function of Tracepro softwares, obtain
The radiometric analysis figure of target is received corresponding to n-GaN；Specially：System is cleared off using Tracepro softwares, to LED chip mould
Type carries out ray tracing, and the luminous flux data of target surface is obtained from the radiometric analysis figure obtained using Tracepro softwares；
(9) record data is collected：Record the proportional numerical value number of the exit luminous flux and total light flux below each illumination figure
Value, and record the required total light flux for receiving target；Recording figure forming area and pattern modelling simultaneously；
(10) optimize pattern parameter, analyze the radiometric analysis figure of same electrode pattern, analyze the upper reception target of the pattern
Luminous flux and luminous flux/emitting light flux ratio, corresponding pattern parameter value is the pattern parameter when optical property is optimal
Optimal value；
(11) the light emitting diode (LED) chip with vertical structure model of multiple Different electrodes patterns is built according to step (1)~(10), it is then right
Than the light data for analyzing light emitting diode (LED) chip with vertical structure model corresponding to each electrode pattern, the optimal electricity of external quantum efficiency is obtained
Pole figure case；
(12) negative photo offset plate is prepared, the negative photo offset plate contains pattern, and the pattern is simulated with Tracepro
The preferably several patterns of obtained external quantum efficiency are corresponding；
(13) standard photolithography process is utilized, on the light emitting diode (LED) chip with vertical structure surface without n-electrode, using negative photoresist
Spin coating, develop, expose, the pattern that now negative photoresist is formed is corresponding with preferably n-electrode pattern；Pass through electron beam evaporation again
Platform evaporating n electrode metal；Next negtive photoresist stripping means (lift-off methods) is used, removes photoresist and photoresist surface
Metal, n-electrode pattern formed；
(14) technique is surveyed on schedule in the enterprising rower of point measurement machine, obtain the optical output power and EQE and core under several patterns
Piece illuminated diagram, compared with the result of Tracepro softwares simulation, it was therefore concluded that.
Analog result is consistent with actually measured result, determines optimal electrode pattern.
When the light emitting diode (LED) chip with vertical structure model n-type electrode pattern of the present embodiment is quatrefoil pattern, its figure such as Fig. 4 institutes
Show, it is um that numerical value unit is marked in figure.Reception target illumination figure such as Fig. 6 institutes that the present embodiment chips model obtains after clearing off
Show.
Above-described embodiment is the preferable embodiment of the present invention, but embodiments of the present invention are not by the embodiment
Limitation, other any Spirit Essences without departing from the present invention with made under principle change, modification, replacement, combine, simplification,
Equivalent substitute mode is should be, is included within protection scope of the present invention.
Claims (6)
- A kind of 1. analysis method of efficiently light emitting diode (LED) chip with vertical structure n-electrode pattern, it is characterised in that：Comprise the following steps：(1) light emitting diode (LED) chip with vertical structure dummy substrate is built：Substrate is gone out using the 3D modeling formation function of Tracepro softwares；(2) light emitting diode (LED) chip with vertical structure model p-electrode layer is built：Using the 3D modeling function of Tracepro softwares on substrate according to Secondary structure bonded layer, p-electrode protective layer, speculum；(3) light emitting diode (LED) chip with vertical structure model epitaxial layer is built：Using the 3D modeling function of Tracepro softwares on p-electrode layer P-GaN epitaxial layers, quantum well layer, n-GaN epitaxial layers are built successively；(4) n-electrode pattern is drawn：Using the modeling function and Boolean calculation function of Tracepro softwares on n-GaN epitaxial layers Iso-surface patch n-electrode pattern, i.e., the geometry needed for pattern is built on n-GaN epitaxial layers using the modeling function of Tracepro softwares Body, and by the Boolean calculation function of Tracepro softwares, obtain required pattern；(5) light emitting diode (LED) chip with vertical structure model n-electrode light receiver target is built：Using the modeling function and cloth of Tracepro softwares Your calculation function build light contacts target surface above LED chip model n-electrode, in the target surface and light emitting diode (LED) chip with vertical structure N-GaN faces are corresponding；(6) material parameter is set：Light emitting diode (LED) chip with vertical structure dummy substrate, p-electrode layer, epitaxial layer, n-electrode layer material are set respectively Expect parameter and various optical property parameters；(7) light source is set：Function is set using Tracepro softwares area source, one table is respectively set in quantum well layer upper and lower surface Area source attribute；The surface source of light characteristic rink corner is distributed as the luminous field patterns of Lambertian, and transmitting circular cone radius is 30 °；Ripple Length is distributed as Gaussian Profile, centre wavelength 465nm, half a width of 100nm；Transmitting form is luminous flux, and emission measure is 1000 streams It is bright；The minimum light of each surface source of light is 10, total light number 10000, is scaled 1；(8) light extraction efficiency of LED chip model is analyzed：Using the ray tracing function of Tracepro softwares, obtain and receive target surface Radiometric analysis figure；(9) record data is collected：The proportional numerical value of the exit luminous flux and total light flux below illumination figure is recorded, and needed for record The total light flux of target surface；Recording figure forming area and pattern modelling simultaneously；(10) pattern parameter is optimized：The pattern parameter includes pattern area and pattern modelling；(11) the light emitting diode (LED) chip with vertical structure model of multiple Different electrodes patterns is built according to step (1)~(10), then to score The light data of light emitting diode (LED) chip with vertical structure model corresponding to each electrode pattern are analysed, obtain the optimal electrode figure of external quantum efficiency Case.(12) negative photo offset plate is prepared, the negative photo offset plate contains pattern, and the pattern simulates to obtain with Tracepro External quantum efficiency preferably several patterns it is corresponding；(13) standard photolithography process is utilized, on the light emitting diode (LED) chip with vertical structure surface without n-electrode, using negative photoresist spin coating, Development, exposure, the pattern that now negative photoresist is formed are corresponding with n-electrode pattern；Pass through electron beam evaporation platform evaporating n electrode again Metal；Next negtive photoresist stripping means (lift-off methods) is used, removes photoresist and the metal on photoresist surface, n electricity Pole figure case is formed；(14) technique is surveyed on schedule in the enterprising rower of point measurement machine, obtain the optical output power and EQE and chip hair under several patterns Light figure, compared with the result of Tracepro softwares simulation, it was therefore concluded that.
- 2. the analysis method of efficient light emitting diode (LED) chip with vertical structure n-electrode pattern according to claim 1, it is characterised in that：Step (1) substrate described in is that the as broad as long cuboid in bottom surface shifts substrate；Substrate described in step (1) is senior staff officer's conductive silicon, high-conductive metal, flexible conductive substrates.
- 3. the analysis method of efficient light emitting diode (LED) chip with vertical structure n-electrode pattern according to claim 1, it is characterised in that：Step (2) bonded layer described in, p-electrode protective layer, speculum are cuboid of the bottom surface for square；P-GaN described in step (3) Epitaxial layer, quantum well layer, n-GaN epitaxial layers are that bottom surface is square cuboid.
- 4. the analysis method of efficient light emitting diode (LED) chip with vertical structure n-electrode pattern according to claim 1, it is characterised in that：Step (4) n-electrode pattern described in is patterned Ti/Al/Ti layers, and Ti layers, Al layers, Ti layers are built successively.
- 5. the analysis method of efficient light emitting diode (LED) chip with vertical structure n-electrode pattern according to claim 1, it is characterised in that：Step (2) bonded layer is AuSn eutectics, AuSi eutectics or NiSn eutectics in p-electrode layer described in；P-electrode protective layer is Cr/Pt, Cr/Pt/Au or Cr/Pt/Au/Pt etc. in p-electrode layer described in step (2)；The Cr layers Close to speculum；Speculum is Ag, Al, Ni/Ag, Ti/Al, Ni/Ag/Pt, Ni/Ag/Au or Ti/Al/ in p-electrode layer described in step (2) Au。
- 6. the analysis method of efficient light emitting diode (LED) chip with vertical structure n-electrode pattern according to claim 1, it is characterised in that：Step (6) optical property parameter described in includes lambda1-wavelength, refractive index, absorptivity, extinction coefficient.
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