WO2015062283A1 - Led patterning substrate having primary and secondary patterns, and led chip - Google Patents

Led patterning substrate having primary and secondary patterns, and led chip Download PDF

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Publication number
WO2015062283A1
WO2015062283A1 PCT/CN2014/079925 CN2014079925W WO2015062283A1 WO 2015062283 A1 WO2015062283 A1 WO 2015062283A1 CN 2014079925 W CN2014079925 W CN 2014079925W WO 2015062283 A1 WO2015062283 A1 WO 2015062283A1
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pattern
substrate
led
main
patterns
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PCT/CN2014/079925
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French (fr)
Chinese (zh)
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李国强
林志霆
何攀贵
乔田
周仕忠
王海燕
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华南理工大学
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Publication of WO2015062283A1 publication Critical patent/WO2015062283A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds

Definitions

  • the invention relates to an LED and an LED chip, in particular to an LED patterned substrate and an LED chip having a main and a double double pattern.
  • GaN-based LEDs have been widely used in traffic lights, LCD backlights, full color displays, and general lighting because of their high brightness, low power consumption, and long life.
  • the critical angle of total reflection is only about 24 degrees, which causes the light to undergo significant total reflection inside the chip and cannot be emitted.
  • LEDs greatly reduce the light extraction rate of LEDs.
  • improvements were proposed for this problem, such as the introduction of Bragg reflection layer, photonic crystal, surface roughening and substrate patterning.
  • the patterned substrate technology can not only improve the light extraction rate, but also improve the internal quantum efficiency.
  • the pattern on the substrate changes the trajectory of the light by refraction and reflection, so that the incident angle of light exiting at the interface becomes smaller (less than the critical angle of total reflection), thereby being transmitted and improving the extraction rate of light;
  • the pattern can also cause lateral epitaxial effect of subsequent GaN growth, reduce crystal defects, and improve internal quantum efficiency.
  • the key to graphical substrate technology is the design of the substrate pattern, which plays a decisive role in the light extraction efficiency of the LED.
  • the types of patterns have been updated several times. From the initial groove shape to hexagonal, tapered, prismatic, etc., the application effect of the patterned substrate technology has been recognized.
  • S. Experiments by Suihkonen et al. have shown that a hexagonal pattern with a large height enhances the reflection and scattering of light, and the angle of inclination of the tapered pattern with a pointed pyramid-shaped convex structure is opposite to that of the LED. The light has a greater impact.
  • Lee et al. used ICP etching to obtain a cone-shaped patterned sapphire substrate.
  • Pattern design of the patterned substrate technology has been limited to a regular arrangement of a single type of pattern, such as a rectangular or hexagonal arrangement of a single pattern such as a cone, a hexagonal pyramid, a triangular pyramid, or a hemisphere.
  • the pattern pitch cannot be reduced without limit, so the pattern has a limited minimum density.
  • this portion of the gap has a space for further increasing the light extraction rate of the patterned substrate LED.
  • an object of the present invention is to provide an LED patterned substrate and an LED chip having a main and a double double pattern, which greatly improves the light extraction rate of the LED.
  • An LED patterned substrate having a main and a double pattern, the pattern on the substrate being composed of a main pattern and a sub pattern arranged on a surface of the substrate; the volume of the sub pattern being smaller than the volume of the main pattern; The cloth is in the gap of the main pattern.
  • the main pattern is in a rectangular arrangement.
  • the main pattern adopts a hexagonal arrangement.
  • the main pattern adopts a diamond arrangement.
  • the main pattern adopts a circumferential distribution arrangement.
  • An LED chip comprising the above-described LED patterned substrate having a primary and secondary double pattern.
  • the present invention has the following advantages and benefits:
  • the pattern of the LED patterned substrate of the present invention adopts a main pattern and a sub pattern arranged on the surface of the substrate, the sub pattern is arranged in the gap of the main pattern, and the volume of the sub pattern is smaller than the volume of the main pattern, and the scheme is relative to a single type
  • the pattern of the patterned substrate, the pattern on the substrate is more dense, which is more favorable for more light to be emitted from the LED chip, especially for more light to be emitted from the top of the chip, greatly improving the LED light extraction rate, for the patterned substrate Technology provides new directions for research and application.
  • FIG. 1 is a schematic view of an LED chip of Embodiment 1 of the present invention.
  • FIG. 2 is a schematic view of an LED patterned substrate having a primary and secondary double pattern according to Embodiment 1 of the present invention.
  • Fig. 3 is a schematic view showing a main pattern of Embodiment 1 of the present invention.
  • FIG. 4 is a schematic view of an LED patterned substrate having a primary and secondary double pattern according to Embodiment 2 of the present invention.
  • Fig. 5 is a schematic view showing a main pattern of a second embodiment of the present invention.
  • Fig. 6 is a schematic view showing a sub pattern of a second embodiment of the present invention.
  • Figure 7 is a schematic illustration of an LED patterned substrate having a primary and secondary dual pattern in accordance with a third embodiment of the present invention.
  • Fig. 8 is a schematic view showing a main pattern of a third embodiment of the present invention.
  • Fig. 9 is a schematic view showing a sub pattern of a third embodiment of the present invention.
  • FIG. 1 is a schematic view of an LED chip of the present embodiment, which is composed of an LED patterned substrate 11 having a main and a double pattern, an N-type GaN layer 12, an MQW quantum well layer 13, and a P-type GaN layer 14 which are sequentially arranged.
  • the pattern on the substrate is composed of the main pattern 15 and the sub pattern 16 arranged on the surface of the substrate; the main pattern and the main pattern of the sub pattern use the same pattern, i.e., a conical pattern; wherein 2 to 3, the bottom surface of the main pattern cone radius r 1 of 1.5 m, angle ⁇ 1 is 60 °, the center distance between adjacent main pattern is 5.0 m, The arrangement is hexagonal; the bottom of the sub-pattern cone has a radius of 0.7 ⁇ m and an inclination of 45°, which is arranged in the gap of the main pattern cone.
  • the optical substrate analysis software TracePro is used to simulate the patterned substrate of the LED chip of the present invention.
  • the simulation test process is as follows:
  • Substrate construction The substrate was fabricated using the modeling function of TracePro, and the substrate size was 120 ⁇ m ⁇ 120 ⁇ m ⁇ 100 ⁇ m, which was in the shape of a rectangular parallelepiped.
  • the main pattern is arranged in a hexagonal arrangement, and the sub pattern is arranged in the gap of the main pattern, as shown in FIG.
  • the N-type GaN layer, the MQW quantum well layer and the P-type GaN layer are fabricated by using TracePro's own modeling function.
  • the size of the N-type GaN layer is 120 ⁇ m ⁇ 120 ⁇ m ⁇ 4 ⁇ m.
  • the MQW quantum well layer has a size of 120 ⁇ m ⁇ 120 ⁇ m ⁇ 75 nm
  • the P-type GaN layer has a size of 120 ⁇ m ⁇ 120 ⁇ m ⁇ 0.2 ⁇ m, and each has a rectangular parallelepiped shape.
  • Target surface construction The production of six-layer target surface is realized by the modeling function of TracePro.
  • the six-layer target surface is placed on the upper, lower, front, back, left and right directions of the LED chip, and the upper and lower targets are respectively placed.
  • the surface size was 120 ⁇ m ⁇ 120 ⁇ m ⁇ 0.01 ⁇ m
  • the front, rear, left, and right target surface dimensions were 100 ⁇ m ⁇ 104.275 ⁇ m ⁇ 0.01 ⁇ m.
  • Corresponding pattern construction of the N-type GaN layer and the patterned substrate contact surface inserting the pattern layer established by SolidWorks on the substrate layer, and using the difference set function of TracePro to realize the corresponding pattern construction of the N-GaN layer.
  • the refractive index of the sapphire substrate is 1.67
  • the refractive indices of the N-type GaN, MQW quantum well and P-type GaN are 2.45, all of which are for 450.
  • the light of nm is set to 300K, regardless of the influence of absorption and extinction coefficient.
  • Quantum well layer surface light source setting a surface light source property is set on each of the upper and lower surfaces of the quantum well layer, the emission form is luminous flux, the field angle distribution is Lambertian luminous field type, the luminous flux is 5000a.u., and the total number of rays is 3,000. The minimum number of rays is 10.
  • the top luminous flux increased by 172%
  • the bottom luminous flux increased by 163%
  • the side luminous flux increased by 147%
  • the total luminous flux increased by 158%.
  • the top luminous flux is increased by 80%
  • the bottom luminous flux is increased by 63%
  • the side luminous flux is increased by 34%
  • the total luminous flux is increased by 66%. It can be seen that the LED patterned substrate having the main and double double patterns can greatly improve the LED light extraction rate.
  • the LED chip of this embodiment is composed of an LED patterned substrate having a main and a double pattern, an N-type GaN layer, an MQW quantum well layer, and a P-type GaN layer.
  • the pattern on the substrate is composed of the main pattern 25 and the sub-pattern 26 arranged on the surface of the substrate; the main pattern 25 and the sub-pattern 26
  • the main pattern uses a different pattern.
  • the main pattern adopts a regular hexagonal pyramid pattern.
  • the positive hexagonal pyramid pattern has an inclination angle ⁇ 2 of 60°, a side length a 2 of 1.0 ⁇ m, a pitch of adjacent positive hexagonal pyramids of 3.2 ⁇ m, and a hexagonal arrangement.
  • the sub-pattern is a hemisphere, and the radius of the bottom surface is 2 ⁇ m, which is arranged in the gap of the main pattern.
  • the optical substrate analysis software TracePro is used to simulate the patterned substrate of the LED chip of the present invention.
  • the simulation test process is as follows:
  • Substrate construction The substrate was fabricated using the modeling function of TracePro, and the substrate size was 120 ⁇ m ⁇ 120 ⁇ m ⁇ 100 ⁇ m, which was in the shape of a rectangular parallelepiped.
  • Sub-pattern production The hemispherical pattern is produced by the drawing function of SolidWorks: the radius of the bottom surface of the hemisphere is 0.5 ⁇ m.
  • Pattern arrangement The main pattern is arranged in a hexagonal arrangement, and the sub pattern is arranged in the gap of the main pattern, as shown in FIG.
  • the N-type GaN layer, the MQW quantum well layer and the P-type GaN layer are fabricated by using TracePro's own modeling function.
  • the size of the N-type GaN layer is 120 ⁇ m ⁇ 120 ⁇ m ⁇ 4 ⁇ m.
  • the MQW quantum well layer has a size of 120 ⁇ m ⁇ 120 ⁇ m ⁇ 75 nm
  • the P-type GaN layer has a size of 120 ⁇ m ⁇ 120 ⁇ m ⁇ 0.2 ⁇ m, and each has a rectangular parallelepiped shape.
  • Target surface construction The production of six-layer target surface is realized by the modeling function of TracePro.
  • the six-layer target surface is placed on the upper, lower, front, back, left and right directions of the LED chip, and the upper and lower targets are respectively placed.
  • the surface size was 120 ⁇ m ⁇ 120 ⁇ m ⁇ 0.01 ⁇ m
  • the front, rear, left, and right target surface dimensions were 100 ⁇ m ⁇ 104.275 ⁇ m ⁇ 0.01 ⁇ m.
  • Corresponding pattern construction of the N-type GaN layer and the patterned substrate contact surface inserting the pattern layer established by SolidWorks on the substrate layer, and using the difference set function of TracePro to realize the corresponding pattern construction of the N-GaN layer.
  • the refractive index of the sapphire substrate is 1.67
  • the refractive indices of the N-type GaN, MQW quantum well and P-type GaN are 2.45, all of which are for 450.
  • the light of nm is set to 300K, regardless of the influence of absorption and extinction coefficient.
  • Quantum well layer surface light source setting a surface light source property is set on each of the upper and lower surfaces of the quantum well layer, the emission form is luminous flux, the field angle distribution is Lambertian luminous field type, the luminous flux is 5000a.u., and the total number of rays is 3,000. The minimum number of rays is 10.
  • the top luminous flux increased by 219%
  • the bottom luminous flux increased by 176%
  • the side luminous flux increased by 104%
  • the total luminous flux increased by 153%.
  • the top luminous flux is increased by 85%
  • the bottom luminous flux is increased by 62%
  • the side luminous flux is increased by 33%
  • the total luminous flux is increased by 67%. It can be seen that the LED patterned substrate with the main and double patterns can greatly improve the LED light extraction rate, and the optimization effect on the top light flux is remarkable.
  • the LED chip of this embodiment is composed of an LED patterned substrate having a main and a double pattern, an N-type GaN layer, an MQW quantum well layer, and a P-type GaN layer.
  • the LED patterned substrate having the main and sub-double patterns of the present embodiment the pattern on the substrate is composed of the main pattern 35 and the sub-pattern 36 arranged on the surface of the substrate; the main pattern 35 and the sub-pattern 36
  • the main pattern uses a different pattern.
  • the positive triangular pyramid has a dip angle ⁇ 3 of 45°
  • the positive triangular pyramid side length a 3 is 2.0 ⁇ m
  • the adjacent main pattern has a pitch of 5.0 ⁇ m
  • the arrangement is a rectangular arrangement
  • the sub-pattern adopts a regular hexagonal pyramid
  • the inclination angle ⁇ 4 is 55°
  • the regular hexagonal pyramid side length a 4 is 0.5 ⁇ m, which is arranged in the gap of the main pattern triangular pyramid.
  • the optical substrate analysis software TracePro is used to simulate the patterned substrate of the LED chip of the present invention.
  • the simulation test process is as follows:
  • Substrate construction The substrate was fabricated using the modeling function of TracePro, and the substrate size was 120 ⁇ m ⁇ 120 ⁇ m ⁇ 100 ⁇ m, which was in the shape of a rectangular parallelepiped.
  • the triangular pyramid pattern is realized by the drawing function of SolidWorks: the inclination angle of the regular triangular pyramid is 45°, the length of the bottom side is 2.0 ⁇ m, and the distance between the centers of adjacent positive triangular pyramids is 5.0 ⁇ m.
  • Sub-pattern production The hex pyramid pattern is realized by the drawing function of SolidWorks: the bottom side of the regular hexagonal pyramid is 0.5 ⁇ m and the inclination angle is 55°.
  • the arrangement of the hexagonal pyramids of the main pattern is a rectangular arrangement, and the sub-patterns are arranged in the gap of the main pattern, as shown in FIG.
  • the N-type GaN layer, the MQW quantum well layer and the P-type GaN layer are fabricated by using TracePro's own modeling function.
  • the size of the N-type GaN layer is 120 ⁇ m ⁇ 120 ⁇ m ⁇ 4 ⁇ m.
  • the MQW quantum well layer has a size of 120 ⁇ m ⁇ 120 ⁇ m ⁇ 75 nm
  • the P-type GaN layer has a size of 120 ⁇ m ⁇ 120 ⁇ m ⁇ 0.2 ⁇ m, and each has a rectangular parallelepiped shape.
  • Target surface construction The production of six-layer target surface is realized by the modeling function of TracePro.
  • the six-layer target surface is placed on the upper, lower, front, back, left and right directions of the LED chip, and the upper and lower targets are respectively placed.
  • the surface size was 120 ⁇ m ⁇ 120 ⁇ m ⁇ 0.01 ⁇ m
  • the front, rear, left, and right target surface dimensions were 100 ⁇ m ⁇ 104.275 ⁇ m ⁇ 0.01 ⁇ m.
  • Corresponding pattern construction of the N-type GaN layer and the patterned substrate contact surface inserting the pattern layer established by SolidWorks on the substrate layer, and using the difference set function of TracePro to realize the corresponding pattern construction of the N-GaN layer.
  • the refractive index of the sapphire substrate is 1.67
  • the refractive indices of the N-type GaN, MQW quantum well and P-type GaN are 2.45, all of which are for 450.
  • the light of nm is set to 300K, regardless of the influence of absorption and extinction coefficient.
  • Quantum well layer surface light source setting a surface light source property is set on each of the upper and lower surfaces of the quantum well layer, the emission form is luminous flux, the field angle distribution is Lambertian luminous field type, the luminous flux is 5000a.u., and the total number of rays is 3,000. The minimum number of rays is 10.
  • the top luminous flux is increased by 252%
  • the bottom luminous flux is increased by 31%
  • the side luminous flux is increased by 248%
  • the total luminous flux is increased by 191%.
  • the top luminous flux is increased by 88%
  • the bottom luminous flux is reduced by 21%
  • the side luminous flux is increased by 121%
  • the total luminous flux is increased by 74%. It can be seen that the LED patterned substrate with the main and double patterns can greatly improve the LED light extraction rate, and the optimization effect on the top light flux is remarkable.
  • the above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited by the embodiments.
  • the main pattern and the sub-pattern of the present invention may also be selected from other commonly used patterns, and the main pattern may also adopt a diamond shape.
  • the arrangement of the circumference, the distribution of the circumference, and the like, any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principles of the present invention are equivalent replacement means, and are included in the scope of protection of the present invention. within.

Abstract

An LED patterning substrate having primary and secondary patterns, and an LED chip comprising the LED patterning substrate having primary and secondary patterns. Patterns on a substrate (11) are composed of primary patterns (15) and secondary patterns (16), which are arranged on the surface of the substrate (11); the volume of the secondary patterns (16) is less than that of the primary patterns (15); and the secondary patterns (16) are arranged in the gaps among the primary patterns (15). Compared with an ordinary LED patterning substrate, the patterns on the substrate are denser, so that it is beneficial for more light rays to be emitted from an LED chip, particularly, it is beneficial for more light rays to be emitted from the top of the chip, thereby greatly increasing the light extraction rate of an LED, and providing a new research and application direction for the patterning substrate technology.

Description

[根据细则37.2由ISA制定的发明名称]　具有主副双图案的LED图形化衬底及LED芯片[Name of invention by ISA according to Rule 37.2] LED patterned substrate and LED chip with main and double patterns
技术领域Technical field
本发明涉及LED及LED芯片，特别涉及一种具有主副双图案的LED图形化衬底及LED芯片。The invention relates to an LED and an LED chip, in particular to an LED patterned substrate and an LED chip having a main and a double double pattern.
背景技术Background technique
近年来，GaN基LED因具有亮度高、能耗低、寿命长等诸多优点，被广泛应用于交通指示灯、LCD背光源、全彩显示器和通用照明领域等。然而，GaN材料的折射率（n=2.45）与空气（n=1.0）之间存在巨大差异，全反射临界角仅为24度左右，这导致光线在芯片内部发生显著的全反射现象而无法射出LED，大大降低了LED的光提取率。后来针对这一问题提出了改善方案，如引入布拉格反射层、光子晶体，表面粗化和衬底图形化等。其中，图形化衬底技术不仅能提高光提取率，还能提高内量子效率。一方面，衬底上的图案通过折射和反射改变光的轨迹，使光在界面出射的入射角变小（小于全反射临界角），从而得以透射而出，提高光的提取率；另一方面，图案还可以使得后续的GaN生长出现侧向磊晶的效果，减少晶体缺陷，提高内量子效率。In recent years, GaN-based LEDs have been widely used in traffic lights, LCD backlights, full color displays, and general lighting because of their high brightness, low power consumption, and long life. However, there is a huge difference between the refractive index of GaN material (n=2.45) and air (n=1.0). The critical angle of total reflection is only about 24 degrees, which causes the light to undergo significant total reflection inside the chip and cannot be emitted. LEDs greatly reduce the light extraction rate of LEDs. Later, improvements were proposed for this problem, such as the introduction of Bragg reflection layer, photonic crystal, surface roughening and substrate patterning. Among them, the patterned substrate technology can not only improve the light extraction rate, but also improve the internal quantum efficiency. On the one hand, the pattern on the substrate changes the trajectory of the light by refraction and reflection, so that the incident angle of light exiting at the interface becomes smaller (less than the critical angle of total reflection), thereby being transmitted and improving the extraction rate of light; The pattern can also cause lateral epitaxial effect of subsequent GaN growth, reduce crystal defects, and improve internal quantum efficiency.
图形化衬底技术的关键在于对衬底图案的设计，其对LED的出光效率起着决定性作用。为满足器件性能的要求，图案的种类已几番更新，从最初的槽形到六角形、锥形、棱台型等，图形化衬底技术的应用效果已受到认可。S. Suihkonen 等人的实验证明: 具有较大高度的六角形图案增强了对光线的反射、散射作用，并且具有尖锥状凸起结构的锥形图案的倾斜角对LED 的出光有较大的影响。Lee等人使用ICP刻蚀获得圆锥体图形化蓝宝石衬底，在20mA电流的驱动下，获得的LED的输出功率提高了35%；Su等人分别在蓝宝石衬底上制造出纳米级圆孔图案和微米级圆孔图案，其结果显示，纳米级图案相比微米级图案有更好的出光效率。C.C.Wang等人认为单位面积内图形尺度的减小能够增加反射面从而提高光线的出射几率。 The key to graphical substrate technology is the design of the substrate pattern, which plays a decisive role in the light extraction efficiency of the LED. In order to meet the performance requirements of the device, the types of patterns have been updated several times. From the initial groove shape to hexagonal, tapered, prismatic, etc., the application effect of the patterned substrate technology has been recognized. S. Experiments by Suihkonen et al. have shown that a hexagonal pattern with a large height enhances the reflection and scattering of light, and the angle of inclination of the tapered pattern with a pointed pyramid-shaped convex structure is opposite to that of the LED. The light has a greater impact. Lee et al. used ICP etching to obtain a cone-shaped patterned sapphire substrate. Under the driving of 20 mA, the output power of the obtained LED was increased by 35%. Su et al. respectively fabricated a nano-scale circular pattern on a sapphire substrate. And the micron-scale circular hole pattern, the results show that the nano-scale pattern has better light-emitting efficiency than the micro-scale pattern. C.C. Wang et al. believe that the reduction of the graphical scale per unit area can increase the reflective surface and increase the probability of light emission.
目前的研究已经证明随着衬底上相邻图案之间距离的缩小，LED芯片的光提取率明显增加。其原因在于，图案之间的距离缩小使单位面积的衬底表面上可以排布更多的图案，图案更加密集，从而能够更大限度地提高LED的光提取率。一直以来，图形化衬底技术的图案设计都仅限于对于单一种类图案的规则排布，如圆锥、六棱锥、三棱锥、半球等单一图案的矩形或六角排布。在这种传统的衬底图案设计中，图案间距不可能无极限地缩小，因此图案存着一个有限的最密排布度。但是，即使在最密排布的图案中，相邻图案之间仍然存在较多间隙，这部分间隙存在着进一步提升图形化衬底LED光提取率的空间。 Current research has shown that as the distance between adjacent patterns on the substrate is reduced, the light extraction rate of the LED chip is significantly increased. The reason for this is that the distance between the patterns is reduced so that more patterns can be arranged on the surface of the substrate per unit area, and the pattern is denser, so that the light extraction rate of the LED can be increased to a greater extent. Pattern design of the patterned substrate technology has been limited to a regular arrangement of a single type of pattern, such as a rectangular or hexagonal arrangement of a single pattern such as a cone, a hexagonal pyramid, a triangular pyramid, or a hemisphere. In this conventional substrate pattern design, the pattern pitch cannot be reduced without limit, so the pattern has a limited minimum density. However, even in the most closely arranged pattern, there are still many gaps between adjacent patterns, and this portion of the gap has a space for further increasing the light extraction rate of the patterned substrate LED.
发明内容Summary of the invention
为了克服现有技术的上述缺点与不足，本发明的目的在于提供一种具有主副双图案的LED图形化衬底及LED芯片，大大提高了LED的光提取率。In order to overcome the above disadvantages and disadvantages of the prior art, an object of the present invention is to provide an LED patterned substrate and an LED chip having a main and a double double pattern, which greatly improves the light extraction rate of the LED.
本发明的目的通过以下技术方案实现：The object of the invention is achieved by the following technical solutions:
一种具有主副双图案的LED图形化衬底，衬底上的图案由排列在衬底表面的主图案和副图案组成；所述副图案的体积小于主图案的体积；所述副图案排布在主图案的间隙中。An LED patterned substrate having a main and a double pattern, the pattern on the substrate being composed of a main pattern and a sub pattern arranged on a surface of the substrate; the volume of the sub pattern being smaller than the volume of the main pattern; The cloth is in the gap of the main pattern.
所述主图案采用矩形排布方式。The main pattern is in a rectangular arrangement.
所述主图案采用六角排布方式。The main pattern adopts a hexagonal arrangement.
所述主图案采用菱形排布方式。The main pattern adopts a diamond arrangement.
所述主图案采用圆周分布排布方式。The main pattern adopts a circumferential distribution arrangement.
一种LED芯片，包含上述的具有主副双图案的LED图形化衬底。An LED chip comprising the above-described LED patterned substrate having a primary and secondary double pattern.
与现有技术相比，本发明具有以下优点和有益效果：Compared with the prior art, the present invention has the following advantages and benefits:
本发明的LED图形化衬底的图案采用排列在衬底表面的主图案和副图案，副图案排布在主图案的间隙中，副图案的体积小于主图案的体积，该方案相对于单一种类图案的图形化衬底，衬底上的图案更加密集，有利于更多的光线射出LED芯片，尤其有利于更多的光线从芯片顶部射出，大大提高了LED光提取率，为图形化衬底技术提供了新的研究与应用方向。The pattern of the LED patterned substrate of the present invention adopts a main pattern and a sub pattern arranged on the surface of the substrate, the sub pattern is arranged in the gap of the main pattern, and the volume of the sub pattern is smaller than the volume of the main pattern, and the scheme is relative to a single type The pattern of the patterned substrate, the pattern on the substrate is more dense, which is more favorable for more light to be emitted from the LED chip, especially for more light to be emitted from the top of the chip, greatly improving the LED light extraction rate, for the patterned substrate Technology provides new directions for research and application.
附图说明DRAWINGS
图1为本发明的实施例1的LED芯片的示意图。1 is a schematic view of an LED chip of Embodiment 1 of the present invention.
图2为本发明的实施例1的具有主副双图案的LED图形化衬底的示意图。2 is a schematic view of an LED patterned substrate having a primary and secondary double pattern according to Embodiment 1 of the present invention.
图3为本发明的实施例1的主图案的示意图。Fig. 3 is a schematic view showing a main pattern of Embodiment 1 of the present invention.
图4为本发明的实施例2的具有主副双图案的LED图形化衬底的示意图。4 is a schematic view of an LED patterned substrate having a primary and secondary double pattern according to Embodiment 2 of the present invention.
图5为本发明的实施例2的主图案的示意图。Fig. 5 is a schematic view showing a main pattern of a second embodiment of the present invention.
图6为本发明的实施例2的副图案的示意图。Fig. 6 is a schematic view showing a sub pattern of a second embodiment of the present invention.
图7为本发明的实施例3的具有主副双图案的LED图形化衬底的示意图。Figure 7 is a schematic illustration of an LED patterned substrate having a primary and secondary dual pattern in accordance with a third embodiment of the present invention.
图8为本发明的实施例3的主图案的示意图。Fig. 8 is a schematic view showing a main pattern of a third embodiment of the present invention.
图9为本发明的实施例3的副图案的示意图。Fig. 9 is a schematic view showing a sub pattern of a third embodiment of the present invention.
具体实施方式detailed description
下面结合实施例，对本发明作进一步地详细说明，但本发明的实施方式不限于此。The present invention will be further described in detail below with reference to the embodiments, but the embodiments of the present invention are not limited thereto.
实施例1Example 1
图1为本实施例的LED芯片的示意图，由依次排列的具有主副双图案的LED图形化衬底11，N型GaN层12，MQW量子阱层13，P型GaN层14组成。1 is a schematic view of an LED chip of the present embodiment, which is composed of an LED patterned substrate 11 having a main and a double pattern, an N-type GaN layer 12, an MQW quantum well layer 13, and a P-type GaN layer 14 which are sequentially arranged.
如图2所示，本实施例的具有主副双图案的LED图形化衬底，衬底上的图案由排列在衬底表面的主图案15和副图案16组成；主图案和副图案主图案采用同一种图案，即圆锥图案；其中，如图2~3所示，主图案圆锥的底面圆半径r1为1.5μm，倾角α1为60°，相邻主图案中心的间距为5.0μm，排布方式为六角排布；副图案圆锥的底面圆半径为0.7μm，倾角为45°，排布在主图案圆锥的间隙中。As shown in FIG. 2, in the LED patterned substrate having the main and double double patterns of the embodiment, the pattern on the substrate is composed of the main pattern 15 and the sub pattern 16 arranged on the surface of the substrate; the main pattern and the main pattern of the sub pattern use the same pattern, i.e., a conical pattern; wherein 2 to 3, the bottom surface of the main pattern cone radius r 1 of 1.5 m, angle α 1 is 60 °, the center distance between adjacent main pattern is 5.0 m, The arrangement is hexagonal; the bottom of the sub-pattern cone has a radius of 0.7 μm and an inclination of 45°, which is arranged in the gap of the main pattern cone.
采用光学分析软件TracePro对本发明的LED芯片的图形化衬底做模拟测试，模拟测试过程如下：The optical substrate analysis software TracePro is used to simulate the patterned substrate of the LED chip of the present invention. The simulation test process is as follows:
（1）衬底构建：采用TracePro自带的建模功能实现衬底的制作，衬底尺寸为120μm×120μm×100μm，呈长方体状。(1) Substrate construction: The substrate was fabricated using the modeling function of TracePro, and the substrate size was 120 μm × 120 μm × 100 μm, which was in the shape of a rectangular parallelepiped.
（2）主图案制作：采用SolidWorks的作图功能实现圆锥图案的制作，圆锥的倾角为60°，底面半径为1.5μm，相邻圆锥中心的间距为5.0μm。(2) Main pattern production: The pattern of the SolidWorks is used to realize the production of the conical pattern. The inclination angle of the cone is 60°, the radius of the bottom surface is 1.5 μm, and the distance between the centers of the adjacent cones is 5.0 μm.
（3）副图案制作：圆锥的底面圆半径为0.7μm，倾角为45°。(3) Sub-patterning: The radius of the bottom surface of the cone is 0.7 μm and the inclination angle is 45°.
（4）图案的排布：主图案圆锥排布方式为六角排布，副图案排布在主图案的间隙之中，如图2所示。(4) Arrangement of patterns: The main pattern is arranged in a hexagonal arrangement, and the sub pattern is arranged in the gap of the main pattern, as shown in FIG.
（5）外延层构建：采用TracePro自带的建模功能实现N型GaN层、MQW量子阱层、P型GaN层的制作，N型GaN层尺寸为120μm×120μm×4μm， MQW量子阱层尺寸为120μm×120μm×75nm，P型GaN层尺寸为120μm×120μm×0.2μm，均呈长方体状。(5) Epitaxial layer construction: The N-type GaN layer, the MQW quantum well layer and the P-type GaN layer are fabricated by using TracePro's own modeling function. The size of the N-type GaN layer is 120 μm×120 μm×4 μm. The MQW quantum well layer has a size of 120 μm × 120 μm × 75 nm, and the P-type GaN layer has a size of 120 μm × 120 μm × 0.2 μm, and each has a rectangular parallelepiped shape.
（6）靶面构建：采用TracePro自带的建模功能实现六层靶面的制作，六层靶面分别置于LED芯片的上、下、前、后、左、右方向，上、下靶面尺寸为120μm×120μm×0.01μm，前、后、左、右靶面尺寸为100μm×104.275μm×0.01μm。(6) Target surface construction: The production of six-layer target surface is realized by the modeling function of TracePro. The six-layer target surface is placed on the upper, lower, front, back, left and right directions of the LED chip, and the upper and lower targets are respectively placed. The surface size was 120 μm × 120 μm × 0.01 μm, and the front, rear, left, and right target surface dimensions were 100 μm × 104.275 μm × 0.01 μm.
（7）N型GaN层与图形化衬底接触面相应图案构建：插入SolidWorks建立的图案层于衬底层之上，采用TracePro的差集功能实现N-GaN层相应图案构建。(7) Corresponding pattern construction of the N-type GaN layer and the patterned substrate contact surface: inserting the pattern layer established by SolidWorks on the substrate layer, and using the difference set function of TracePro to realize the corresponding pattern construction of the N-GaN layer.
（8）各材料层的参数设定：蓝宝石衬底的折射率为1.67，N型GaN、MQW量子阱、P型GaN材质折射率均为2.45，四者均针对450 nm的光，温度设置为300K，不考虑吸收与消光系数的影响。(8) Parameter setting of each material layer: the refractive index of the sapphire substrate is 1.67, and the refractive indices of the N-type GaN, MQW quantum well and P-type GaN are 2.45, all of which are for 450. The light of nm is set to 300K, regardless of the influence of absorption and extinction coefficient.
（9）量子阱层表面光源设定：量子阱层上下表面各设置一个表面光源属性，发射形式为光通量，场角分布为Lambertian发光场型，光通量为5000a.u.，总光线数3000条，最少光线数10条。(9) Quantum well layer surface light source setting: a surface light source property is set on each of the upper and lower surfaces of the quantum well layer, the emission form is luminous flux, the field angle distribution is Lambertian luminous field type, the luminous flux is 5000a.u., and the total number of rays is 3,000. The minimum number of rays is 10.
（10）光线追迹：利用软件附带的扫光系统，对上述构建的LED芯片模型进行光线追踪，分别获取顶部、底部、侧面的光通量数据。(10) Ray tracing: Using the scanning system attached to the software, the ray tracing of the LED chip model constructed above is performed, and the luminous flux data of the top, bottom and side are respectively obtained.
测试结果如下：顶部光通量1993a.u.，底部光通量2324a.u.，侧面光通量3332a.u.，总光通量7649a.u.。与无图案衬底相比，顶部光通量提升172%，底部光通量提升163%，侧面光通量提升147%，总光通量提升158%。与单图案（仅有本实施例的主图案）衬底相比，顶部光通量提升80%，底部光通量提升63%，侧面光通量提升34%，总光通量提升66%。可知具有主副双图案的LED图形化衬底可大幅度提升LED光提取率。The test results are as follows: top luminous flux 1993a.u., bottom luminous flux 2324a.u., side luminous flux 3332a.u., total luminous flux 7649a.u. Compared with the unpatterned substrate, the top luminous flux increased by 172%, the bottom luminous flux increased by 163%, the side luminous flux increased by 147%, and the total luminous flux increased by 158%. Compared with the single pattern (only the main pattern of this embodiment) substrate, the top luminous flux is increased by 80%, the bottom luminous flux is increased by 63%, the side luminous flux is increased by 34%, and the total luminous flux is increased by 66%. It can be seen that the LED patterned substrate having the main and double double patterns can greatly improve the LED light extraction rate.
实施例2Example 2
本实施例的LED芯片由依次排列的具有主副双图案的LED图形化衬底，N型GaN层，MQW量子阱层，P型GaN层组成。The LED chip of this embodiment is composed of an LED patterned substrate having a main and a double pattern, an N-type GaN layer, an MQW quantum well layer, and a P-type GaN layer.
如图4所示，本实施例的具有主副双图案的LED图形化衬底，衬底上的图案由排列在衬底表面的主图案25和副图案26组成；主图案25和副图案26主图案采用不同种图案。如图4~5所示，主图案采用正六棱锥图案，正六棱锥图案的倾角α2为60°，边长a2为1.0μm，相邻正六棱锥中心的间距为3.2μm，排布方式为六角排布；如图4、6所示，副图案为半球，底面圆半径r2为0.5μm，排布在主图案的间隙中。As shown in FIG. 4, in the LED patterned substrate having the main and sub-double patterns of the present embodiment, the pattern on the substrate is composed of the main pattern 25 and the sub-pattern 26 arranged on the surface of the substrate; the main pattern 25 and the sub-pattern 26 The main pattern uses a different pattern. As shown in Figures 4 to 5, the main pattern adopts a regular hexagonal pyramid pattern. The positive hexagonal pyramid pattern has an inclination angle α 2 of 60°, a side length a 2 of 1.0 μm, a pitch of adjacent positive hexagonal pyramids of 3.2 μm, and a hexagonal arrangement. As shown in FIGS. 4 and 6, the sub-pattern is a hemisphere, and the radius of the bottom surface is 2 μm, which is arranged in the gap of the main pattern.
采用光学分析软件TracePro对本发明的LED芯片的图形化衬底做模拟测试，模拟测试过程如下：The optical substrate analysis software TracePro is used to simulate the patterned substrate of the LED chip of the present invention. The simulation test process is as follows:
（1）衬底构建：采用TracePro自带的建模功能实现衬底的制作，衬底尺寸为120μm×120μm×100μm，呈长方体状。(1) Substrate construction: The substrate was fabricated using the modeling function of TracePro, and the substrate size was 120 μm × 120 μm × 100 μm, which was in the shape of a rectangular parallelepiped.
（2）主图案制作：采用SolidWorks的作图功能实现六棱锥图案的制作：正六棱锥的倾角为60°，底面边长为1.0μm，相邻正六棱锥中心的间距为3.2μm。(2) Main pattern creation: The hex pyramid pattern was created by the drawing function of SolidWorks: the inclination angle of the regular hexagonal pyramid was 60°, the length of the bottom side was 1.0 μm, and the distance between the centers of adjacent regular hexagonal pyramids was 3.2 μm.
（3）副图案制作：采用SolidWorks的作图功能实现半球图案的制作：半球的底面圆半径为0.5μm。(3) Sub-pattern production: The hemispherical pattern is produced by the drawing function of SolidWorks: the radius of the bottom surface of the hemisphere is 0.5 μm.
（4）图案的排布：主图案的排布方式为六角排布，副图案排布在主图案的间隙之中，如图4所示。(4) Pattern arrangement: The main pattern is arranged in a hexagonal arrangement, and the sub pattern is arranged in the gap of the main pattern, as shown in FIG.
（5）外延层构建：采用TracePro自带的建模功能实现N型GaN层、MQW量子阱层、P型GaN层的制作，N型GaN层尺寸为120μm×120μm×4μm， MQW量子阱层尺寸为120μm×120μm×75nm，P型GaN层尺寸为120μm×120μm×0.2μm，均呈长方体状。(5) Epitaxial layer construction: The N-type GaN layer, the MQW quantum well layer and the P-type GaN layer are fabricated by using TracePro's own modeling function. The size of the N-type GaN layer is 120 μm×120 μm×4 μm. The MQW quantum well layer has a size of 120 μm × 120 μm × 75 nm, and the P-type GaN layer has a size of 120 μm × 120 μm × 0.2 μm, and each has a rectangular parallelepiped shape.
（6）靶面构建：采用TracePro自带的建模功能实现六层靶面的制作，六层靶面分别置于LED芯片的上、下、前、后、左、右方向，上、下靶面尺寸为120μm×120μm×0.01μm，前、后、左、右靶面尺寸为100μm×104.275μm×0.01μm。(6) Target surface construction: The production of six-layer target surface is realized by the modeling function of TracePro. The six-layer target surface is placed on the upper, lower, front, back, left and right directions of the LED chip, and the upper and lower targets are respectively placed. The surface size was 120 μm × 120 μm × 0.01 μm, and the front, rear, left, and right target surface dimensions were 100 μm × 104.275 μm × 0.01 μm.
（7）N型GaN层与图形化衬底接触面相应图案构建：插入SolidWorks建立的图案层于衬底层之上，采用TracePro的差集功能实现N-GaN层相应图案构建。(7) Corresponding pattern construction of the N-type GaN layer and the patterned substrate contact surface: inserting the pattern layer established by SolidWorks on the substrate layer, and using the difference set function of TracePro to realize the corresponding pattern construction of the N-GaN layer.
（8）各材料层的参数设定：蓝宝石衬底的折射率为1.67，N型GaN、MQW量子阱、P型GaN材质折射率均为2.45，四者均针对450 nm的光，温度设置为300K，不考虑吸收与消光系数的影响。(8) Parameter setting of each material layer: the refractive index of the sapphire substrate is 1.67, and the refractive indices of the N-type GaN, MQW quantum well and P-type GaN are 2.45, all of which are for 450. The light of nm is set to 300K, regardless of the influence of absorption and extinction coefficient.
（9）量子阱层表面光源设定：量子阱层上下表面各设置一个表面光源属性，发射形式为光通量，场角分布为Lambertian发光场型，光通量为5000a.u.，总光线数3000条，最少光线数10条。(9) Quantum well layer surface light source setting: a surface light source property is set on each of the upper and lower surfaces of the quantum well layer, the emission form is luminous flux, the field angle distribution is Lambertian luminous field type, the luminous flux is 5000a.u., and the total number of rays is 3,000. The minimum number of rays is 10.
（10）光线追迹：利用软件附带的扫光系统，对上述构建的LED芯片模型进行光线追踪，分别获取顶部、底部、侧面的光通量数据。(10) Ray tracing: Using the scanning system attached to the software, the ray tracing of the LED chip model constructed above is performed, and the luminous flux data of the top, bottom and side are respectively obtained.
测试结果如下：顶部光通量2357a.u.，底部光通量2472a.u.，侧面光通量3009a.u.，总光通量7838a.u.。与无图案衬底相比，顶部光通量提升219%，底部光通量提升176%，侧面光通量提升104%，总光通量提升153%。与单图案（仅有本实施例的主图案）衬底相比，顶部光通量提升85%，底部光通量提升62%，侧面光通量提升33%，总光通量提升67%。可知具有主副双图案的LED图形化衬底可大幅度提升LED光提取率，尤其对顶部光通量的优化效果十分显著。The test results are as follows: top luminous flux 2357a.u., bottom luminous flux 2472a.u., side luminous flux 3009a.u., total luminous flux 7838a.u. Compared with the unpatterned substrate, the top luminous flux increased by 219%, the bottom luminous flux increased by 176%, the side luminous flux increased by 104%, and the total luminous flux increased by 153%. Compared with the single pattern (only the main pattern of this embodiment) substrate, the top luminous flux is increased by 85%, the bottom luminous flux is increased by 62%, the side luminous flux is increased by 33%, and the total luminous flux is increased by 67%. It can be seen that the LED patterned substrate with the main and double patterns can greatly improve the LED light extraction rate, and the optimization effect on the top light flux is remarkable.
实施例3Example 3
本实施例的LED芯片由依次排列的具有主副双图案的LED图形化衬底，N型GaN层，MQW量子阱层，P型GaN层组成。The LED chip of this embodiment is composed of an LED patterned substrate having a main and a double pattern, an N-type GaN layer, an MQW quantum well layer, and a P-type GaN layer.
如图7所示，本实施例的具有主副双图案的LED图形化衬底，衬底上的图案由排列在衬底表面的主图案35和副图案36组成；主图案35和副图案36主图案采用不同种图案。如图7~8所示，主图案采用的正三棱锥的倾角α3为45°，正三棱锥边长a3为2.0μm，相邻主图案的间距为5.0μm，排布方式为矩形排布；如图7、9所示，副图案采用正六棱锥，倾角α4为55°，正六棱锥边长a4为0.5μm，排布在主图案三棱锥的间隙中。As shown in FIG. 7, the LED patterned substrate having the main and sub-double patterns of the present embodiment, the pattern on the substrate is composed of the main pattern 35 and the sub-pattern 36 arranged on the surface of the substrate; the main pattern 35 and the sub-pattern 36 The main pattern uses a different pattern. As shown in FIGS. 7-8, the positive triangular pyramid has a dip angle α 3 of 45°, the positive triangular pyramid side length a 3 is 2.0 μm, the adjacent main pattern has a pitch of 5.0 μm, and the arrangement is a rectangular arrangement; As shown in Figs. 7 and 9, the sub-pattern adopts a regular hexagonal pyramid, the inclination angle α 4 is 55°, and the regular hexagonal pyramid side length a 4 is 0.5 μm, which is arranged in the gap of the main pattern triangular pyramid.
采用光学分析软件TracePro对本发明的LED芯片的图形化衬底做模拟测试，模拟测试过程如下：The optical substrate analysis software TracePro is used to simulate the patterned substrate of the LED chip of the present invention. The simulation test process is as follows:
（1）衬底构建：采用TracePro自带的建模功能实现衬底的制作，衬底尺寸为120μm×120μm×100μm，呈长方体状。(1) Substrate construction: The substrate was fabricated using the modeling function of TracePro, and the substrate size was 120 μm × 120 μm × 100 μm, which was in the shape of a rectangular parallelepiped.
（2）主图案制作：采用SolidWorks的作图功能实现三棱锥图案的制作：正三棱锥的倾角为45°，底面边长为2.0μm，相邻正三棱锥中心的间距为5.0μm。(2) Main pattern production: The triangular pyramid pattern is realized by the drawing function of SolidWorks: the inclination angle of the regular triangular pyramid is 45°, the length of the bottom side is 2.0 μm, and the distance between the centers of adjacent positive triangular pyramids is 5.0 μm.
（3）副图案制作：采用SolidWorks的作图功能实现六棱锥图案的制作：正六棱锥的底面边长为0.5μm，倾角为55°。(3) Sub-pattern production: The hex pyramid pattern is realized by the drawing function of SolidWorks: the bottom side of the regular hexagonal pyramid is 0.5 μm and the inclination angle is 55°.
（4）图案的排布：主图案六棱锥的排布方式为矩形排布，副图案排布在主图案的间隙之中，如图7所示。(4) Arrangement of patterns: The arrangement of the hexagonal pyramids of the main pattern is a rectangular arrangement, and the sub-patterns are arranged in the gap of the main pattern, as shown in FIG.
（5）外延层构建：采用TracePro自带的建模功能实现N型GaN层、MQW量子阱层、P型GaN层的制作，N型GaN层尺寸为120μm×120μm×4μm， MQW量子阱层尺寸为120μm×120μm×75nm，P型GaN层尺寸为120μm×120μm×0.2μm，均呈长方体状。(5) Epitaxial layer construction: The N-type GaN layer, the MQW quantum well layer and the P-type GaN layer are fabricated by using TracePro's own modeling function. The size of the N-type GaN layer is 120 μm×120 μm×4 μm. The MQW quantum well layer has a size of 120 μm × 120 μm × 75 nm, and the P-type GaN layer has a size of 120 μm × 120 μm × 0.2 μm, and each has a rectangular parallelepiped shape.
（6）靶面构建：采用TracePro自带的建模功能实现六层靶面的制作，六层靶面分别置于LED芯片的上、下、前、后、左、右方向，上、下靶面尺寸为120μm×120μm×0.01μm，前、后、左、右靶面尺寸为100μm×104.275μm×0.01μm。(6) Target surface construction: The production of six-layer target surface is realized by the modeling function of TracePro. The six-layer target surface is placed on the upper, lower, front, back, left and right directions of the LED chip, and the upper and lower targets are respectively placed. The surface size was 120 μm × 120 μm × 0.01 μm, and the front, rear, left, and right target surface dimensions were 100 μm × 104.275 μm × 0.01 μm.
（7）N型GaN层与图形化衬底接触面相应图案构建：插入SolidWorks建立的图案层于衬底层之上，采用TracePro的差集功能实现N-GaN层相应图案构建。(7) Corresponding pattern construction of the N-type GaN layer and the patterned substrate contact surface: inserting the pattern layer established by SolidWorks on the substrate layer, and using the difference set function of TracePro to realize the corresponding pattern construction of the N-GaN layer.
（8）各材料层的参数设定：蓝宝石衬底的折射率为1.67，N型GaN、MQW量子阱、P型GaN材质折射率均为2.45，四者均针对450 nm的光，温度设置为300K，不考虑吸收与消光系数的影响。(8) Parameter setting of each material layer: the refractive index of the sapphire substrate is 1.67, and the refractive indices of the N-type GaN, MQW quantum well and P-type GaN are 2.45, all of which are for 450. The light of nm is set to 300K, regardless of the influence of absorption and extinction coefficient.
（9）量子阱层表面光源设定：量子阱层上下表面各设置一个表面光源属性，发射形式为光通量，场角分布为Lambertian发光场型，光通量为5000a.u.，总光线数3000条，最少光线数10条。(9) Quantum well layer surface light source setting: a surface light source property is set on each of the upper and lower surfaces of the quantum well layer, the emission form is luminous flux, the field angle distribution is Lambertian luminous field type, the luminous flux is 5000a.u., and the total number of rays is 3,000. The minimum number of rays is 10.
（10）光线追迹：利用软件附带的扫光系统，对上述构建的LED芯片模型进行光线追踪，分别获取顶部、底部、侧面的光通量数据。(10) Ray tracing: Using the scanning system attached to the software, the ray tracing of the LED chip model constructed above is performed, and the luminous flux data of the top, bottom and side are respectively obtained.
测试结果如下：顶部光通量2760a.u.，底部光通量1163a.u.，侧面光通量4695a.u.，总光通量8618a.u.。与无图案衬底相比，顶部光通量提升252%，底部光通量提升31%，侧面光通量提升248%，总光通量提升191%。与单图案（仅有本实施例的主图案）衬底相比，顶部光通量提升88%，底部光通量降低21%，侧面光通量提升121%，总光通量提升74%。可知具有主副双图案的LED图形化衬底可大幅度提升LED光提取率，尤其对顶部光通量的优化效果十分显著。The test results are as follows: top luminous flux 2760a.u., bottom luminous flux 1163a.u., side luminous flux 4695a.u., total luminous flux 8618a.u. Compared to the unpatterned substrate, the top luminous flux is increased by 252%, the bottom luminous flux is increased by 31%, the side luminous flux is increased by 248%, and the total luminous flux is increased by 191%. Compared with the single pattern (only the main pattern of this embodiment) substrate, the top luminous flux is increased by 88%, the bottom luminous flux is reduced by 21%, the side luminous flux is increased by 121%, and the total luminous flux is increased by 74%. It can be seen that the LED patterned substrate with the main and double patterns can greatly improve the LED light extraction rate, and the optimization effect on the top light flux is remarkable.
上述实施例为本发明较佳的实施方式，但本发明的实施方式并不受所述实施例的限制，本发明的主图案、副图案还可选用其它常用的图案，主图案还可采用菱形、圆周分布等排布方式,其他的任何未背离本发明的精神实质与原理下所作的改变、修饰、替代、组合、简化，均应为等效的置换方式，都包含在本发明的保护范围之内。The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited by the embodiments. The main pattern and the sub-pattern of the present invention may also be selected from other commonly used patterns, and the main pattern may also adopt a diamond shape. The arrangement of the circumference, the distribution of the circumference, and the like, any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principles of the present invention are equivalent replacement means, and are included in the scope of protection of the present invention. within.

Claims (6)

  1. 一种具有主副双图案的LED图形化衬底，其特征在于，衬底上的图案由排列在衬底表面的主图案和副图案组成；所述副图案的体积小于主图案的体积；所述副图案排布在主图案的间隙中。 An LED patterned substrate having a main and a double double pattern, wherein the pattern on the substrate is composed of a main pattern and a sub pattern arranged on a surface of the substrate; the volume of the sub pattern is smaller than the volume of the main pattern; The sub-patterns are arranged in the gaps of the main patterns.
  2. 根据权利要求1所述的具有主副双图案的LED图形化衬底，其特征在于，所述主图案采用矩形排布方式。The LED patterned substrate having a primary and secondary double pattern according to claim 1, wherein the main pattern is in a rectangular arrangement.
  3. 根据权利要求1所述的具有主副双图案的LED图形化衬底，其特征在于，所述主图案采用六角排布方式。The LED patterned substrate having a primary and secondary double pattern according to claim 1, wherein the main pattern is in a hexagonal arrangement.
  4. 根据权利要求1所述的具有主副双图案的LED图形化衬底，其特征在于，所述主图案采用菱形排布方式。The LED patterned substrate having a primary and secondary double pattern according to claim 1, wherein the main pattern is in a diamond arrangement.
  5. 根据权利要求1所述的具有主副双图案的LED图形化衬底，其特征在于，所述主图案采用圆周分布排布方式。The LED patterned substrate having a primary and secondary double pattern according to claim 1, wherein the main pattern is arranged in a circumferentially distributed manner.
  6. 一种LED芯片，其特征在于，包含权利要求1~5任一项所述的具有主副双图案的LED图形化衬底。An LED chip comprising the LED patterned substrate having a primary and secondary double pattern according to any one of claims 1 to 5.
PCT/CN2014/079925 2013-10-30 2014-06-16 Led patterning substrate having primary and secondary patterns, and led chip WO2015062283A1 (en)

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