TW202230832A - Light-emitting element and manufacturing method thereof - Google Patents

Abstract

A light-emitting device is disclosed. The light-emitting device comprises a semiconductor stack including a first semiconductor layer, a second semiconductor layer and an active layer formed therebetween; one or more via-like exposed regions formed within the semiconductor stack and exposing the first semiconductor layer; a first insulating layer formed on the semiconductor stack and including one or more first openings corresponding to the one or more via-like exposed regions and one or more second openings on the second semiconductor; one or more first conductive layers corresponding to the one or more via-like exposed regions and electrically connected to the first semiconductor layer through the one or more first openings; one or more second conductive layers formed on the second semiconductor and electrically connected to the second semiconductor layer through the one or more second openings; a first electrode layer formed on the one or more first conductive layers and electrically connected to the first semiconductor layer; a bonding layer formed on the first electrode layer; a conductive substrate, wherein the semiconductor stack is located on one side of the bonding layer, and the conductive substrate is located on an opposite side of the bonding layer; an exposed region formed on a side or a corner of the light-emitting device and not overlapping with the semiconductor stack; and a wire-bonding pad formed on the exposed region and electrically connected to the one or more first conductive layers or the one or more second conductive layers.

Description

Light-emitting element and method of manufacturing the same

The present invention relates to a light-emitting element and a manufacturing method thereof, and more specifically, to a light-emitting element with high brightness.

Light-emitting diodes (LEDs) are optoelectronic components composed of P-type semiconductors and N-type semiconductors, which emit light through the combination of P-N junction carriers, and have small size, low power consumption, and long life. , fast response and other advantages, widely used in optical display devices, traffic signs, data storage devices, communication devices, lighting devices and medical equipment.

A light-emitting element, comprising: a semiconductor stack having a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; one or more hole exposure areas located in In the semiconductor stack, the first semiconductor layer is exposed; a first insulating layer is located on the semiconductor stack and includes one or more first openings corresponding to one or more hole exposure regions, and one or more second openings on the second semiconductor layer; one or more first conductive layers, corresponding to one or more exposed regions of the holes, electrically connected to the first semiconductor layer through one or more first openings; one or more second The conductive layer is located on the second semiconductor layer and is electrically connected to the second semiconductor layer through one or more second openings; a first electrode layer is located on the one or more first conductive layers and is connected to the first semiconductor layer The layers are electrically connected; a bonding layer is located on the first electrode layer; a conductive substrate, wherein the semiconductor stack is located on one side of the bonding layer, and the conductive substrate is located on the other side of the bonding layer relative to the semiconductor stack; an exposed area, a side or a corner of the light-emitting element, not overlapping with the semiconductor stack; and a wire bonding pad, located on the exposed area, electrically connected to the one or more first conductive layers or the one or more second conductive layers .

Embodiments of the present application will be described in detail and drawn in the drawings, and identical or similar parts will appear in the various drawings and descriptions with the same numerals.

No. 11B shows a light-emitting element 1 disclosed in an embodiment of the present application; Figures 1A to 11B show a manufacturing method of the light-emitting element 1 of the present application.

As shown in the top view of FIG. 1A and the cross-sectional view of FIG. 1B along line AA' of FIG. 1A, the manufacturing method of the light-emitting device 1 includes a step of forming a platform, which includes providing a growth substrate 11; and forming a semiconductor The stack 10 is on the growth substrate 11 . The semiconductor stack 10 includes a first semiconductor layer 101 , a second semiconductor layer 102 , and an active layer 103 located between the first semiconductor layer 101 and the second semiconductor layer 102 . The semiconductor stack 10 removes part of the second semiconductor layer 102 and the active layer 103 by means of lithography and etching to expose the sidewalls of the first semiconductor layer 101 , the second semiconductor layer 102 and the active layer 103 to form a plurality of exposed area. The exposed regions include a surrounding exposed region 15 located around the semiconductor stack 10 and one or more hole exposed regions 17 located inside the semiconductor stack 10 . From the top view, the wider area surrounding the exposed area 15 is an area E1. In this embodiment, in addition to the removal of the second semiconductor layer 102 and the active layer 103 in a part of the region, a part of the first semiconductor layer 101 is further removed to form a first surface S1 in the surrounding exposed region 15 and in the The hole exposed region 17 forms a second surface S2. The sidewalls of the first semiconductor layer 101 , the second semiconductor layer 102 and the active layer 103 constitute the sidewalls surrounding the exposed region 15 and the one or more hole exposed regions 17 ; the first surface S1 exposed by the first semiconductor layer 101 once constitutes Surrounding the bottom surface of the exposed region 15 , the second surface S2 constitutes the bottom surface of the hole exposed region 17 . From the top view, the surrounding exposed region 15 surrounds all the active layers 103 and the second semiconductor layer 102 . The first surface S1 and the second surface S2 can be formed in the same etching process, so the first surface S1 and the second surface S2 have the same depth with respect to the top surface 102s of the semiconductor stack 10 . The shape of the hole exposure area 17 includes a circle, an ellipse, a rectangle, a polygon, or any shape. In this embodiment, there are a plurality of hole exposure areas 17 , and the shape of the hole exposure area 17 is a strip. The configuration, quantity and size of the exposed regions 17 can be designed differently according to the requirements of current distribution and the size of the light-emitting element.

In one embodiment of the present application, the semiconductor stack 10 may include only the surrounding exposed region 15 but not the hole exposed region 17 .

In the embodiment of the present application, the size of the growth substrate 11 includes a wafer-level substrate or a die-level substrate, and the semiconductor stack 10 includes a wafer-level semiconductor stack or a die-level semiconductor stack. Wafers referred to here are not limited to circular shapes, but include polygonal or irregular shapes. The wafer referred to here can be divided into a plurality of light-emitting elements at the die level in the subsequent process; it is also possible to directly form light-emitting elements without dividing. In each embodiment of this application, for the convenience of description, the structures of each step shown in the drawings, such as the growth substrate 11 and the semiconductor stack 10 are represented by a single light-emitting element, but the embodiment is not limited to this , the platform formation step and subsequent processes can be completed at the wafer level.

In one embodiment of the present application, the growth substrate 11 includes a gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP), or a sapphire (Al) wafer for growing indium gallium nitride (InGaN) ₂ O ₃ ) wafer, gallium nitride (GaN) wafer or silicon carbide (SiC) wafer. The growth substrate 11 may have a patterned structure (not shown) on the surface on which the semiconductor stack 10 is to be formed. In addition, the growth substrate 11 can be formed by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), vapor deposition or ion plating with optoelectronic properties. The semiconductor stack 10 is, for example, a light-emitting stack.

In one embodiment of the present application, before forming the semiconductor stack 10 , a buffer layer (not shown) may be formed on the growth substrate 11 first. The buffer layer can alleviate the mismatch of lattice constants between the growth substrate 11 and the semiconductor stack 10 to improve the epitaxial quality.

In one embodiment of the present application, the first semiconductor layer 101 and the second semiconductor layer 102 have different conductivity, electrical property, polarity or dopant to provide holes and electrons, respectively. The polarity can be n-type or p-type, so that electrons and holes can recombine in the active layer 103 to generate light. For example, the first semiconductor layer 101 can be an n-type semiconductor layer, and the second semiconductor layer 102 can be a p-type semiconductor layer. The material of the semiconductor stack 10 includes Group III-V semiconductor materials, such as AlxInyGa(1- _{xy )} N or _AlxInyGa (1- _{xy )} P, where 0≦ _x , y≦1; (x +y)≦1. According to the material of the active layer, when the material of the semiconductor stack 10 is AlInGaP series material, it can emit red light with wavelengths between 610 nm and 650 nm, and green light with wavelengths between 530 nm and 570 nm. When the material of the stack 10 is InGaN series materials, it can emit blue light with a wavelength between 450 nm and 490 nm, or when the material of the semiconductor stack 10 is AlGaN, AlGaInN series materials, it can emit blue light with a wavelength between 400 nm and 250 nm. UV light between nm. The active layer 103 may be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well structure (multi-quantum well, MQW). The active layer material can be an undoped, p-doped or n-doped semiconductor.

Following the step of forming the platform, as shown in the top view of FIG. 2A and the cross-sectional view along line AA′ of FIG. 2A in FIG. The first insulating layer 20 can form an insulating material layer on the semiconductor stack 10 by means of evaporation or deposition, and then pattern the insulating material layer by means of lithography and etching to obtain the first insulating layer 20 covering the surrounding exposure. The bottom surface S1 of the region 15 and the hole portion expose the bottom surface S2 of the region 17 and cover the sidewall of the semiconductor stack 10 . The first insulating layer 20 includes a first insulating layer surrounding area 20a, covering the first surface S1 of the first semiconductor layer 101 surrounding the exposed area 15 and the sidewall of the semiconductor stack 10; and a first insulating layer covering area 20b, Covering the second surface S2 of the first semiconductor layer 101 and the sidewall of the semiconductor stack 10 in the exposed region 17 of the hole portion. The first insulating layer covering regions 20b are separated from each other and correspond to the plurality of hole exposure regions 17 respectively. The first insulating layer 20 may have a single-layer or multi-layer structure. When the first insulating layer 20 is a single-layer film, the first insulating layer 20 can protect the sidewalls of the semiconductor stack 10 to prevent the active layer 103 from being damaged by subsequent processes. When the first insulating layer 20 is a multi-layer film, in addition to protecting the sidewall of the semiconductor stack 10, the first insulating layer 20 may further comprise two or more materials with different refractive indices stacked alternately to form a Bragg reflector (DBR) A structure that selectively reflects light of specific wavelengths. The first insulating layer 20 is formed of non-conductive materials, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin) ), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), or fluorine Carbon polymer (Fluorocarbon Polymer), or inorganic materials, such as silica gel (Silicone), glass (Glass), or dielectric materials, such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ).

In an embodiment of the present invention, following the first insulating layer forming step, as shown in the top view of FIG. 3A and the cross-sectional view of FIG. 3B along line AA' of FIG. 3A, the light-emitting element 1 The manufacturing method includes a step of forming the current dispersion layer 18 . The current dispersion layer 18 can be formed on the second semiconductor layer 102 not covered by the first insulating layer 20 by means of evaporation or deposition, and is in electrical contact with the second semiconductor layer 102. The current dispersion layer 18 can be a metal or It is a transparent conductive material, wherein the metal can be selected from a thin metal layer with light transmittance, and the transparent conductive material is transparent to the light emitted by the active layer 103, including indium tin oxide (ITO), aluminum oxide zinc (AZO), oxide Gallium zinc (GZO), or indium zinc oxide (IZO) and other materials.

In one embodiment of the present application, after the step of forming the platform, the step of forming the current dispersion layer 18 may be performed first, and then the step of forming the first insulating layer 20 may be performed.

In an embodiment of the present application, after the step of forming the platform, the step of forming the first insulating layer 20 may be omitted, and the step of forming the current dispersion layer 18 may be directly performed.

Continuing the current dispersion layer forming step, as shown in the top view of FIG. 4A and the cross-sectional view along line A-A' of FIG. 4A in FIG. The reflective structure 16 can be composed of a reflective layer (not shown) and/or a barrier layer (not shown), and can be directly formed on the current dispersion layer 18 by evaporation or deposition, wherein the reflective layer is located on the current dispersion layer 18. between the dispersion layer 18 and the barrier layer (not shown). In the embodiment of the present application, as shown in the top view of FIG. 4A , the outer edge of the reflective structure 16 can be disposed on the inner side, the outer side of the outer edge of the current dispersion layer 18 , or be aligned with the outer edge of the current dispersion layer 18 . The outer edge of the layer may be positioned inside, outside, or aligned with the outer edge of the reflective layer. In another embodiment of the present application, the current dispersion layer 18 can be omitted, and the reflective structure 16 can be directly formed on the second semiconductor layer 102 .

The reflective layer can be one or a multilayer structure, and the multilayer structure is, for example, a Bragg reflector (DBR) structure. The material of the reflective layer includes metal materials with high reflectivity, such as silver (Ag), aluminum (Al), gold (Au), titanium (Ti), copper (Cu), platinum (Pt), nickel (Ni) or rhodium (Rh) and other metals or alloys of the above materials. The high reflectivity mentioned herein refers to having a reflectivity of more than 80% for the wavelength of light emitted by the active layer 103 . In one embodiment of the present application, the barrier layer coats the reflective layer to prevent surface oxidation of the reflective layer from deteriorating the reflectivity of the reflective layer. The material of the barrier layer includes metal materials, such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), chromium (Cr), Or zinc (Zn) and other metals or alloys of the above materials. The barrier layer may have one or more layers, such as titanium (Ti)/aluminum (Al), and/or titanium (Ti)/tungsten (W).

Following the step of forming the reflective structure, as shown in the top view of FIG. 5A and the cross-sectional view along A-A' of FIG. 5A in FIG. The second insulating layer 50 can form an insulating material layer on the semiconductor stack 10 by means of evaporation or deposition, and then pattern the insulating material layer by means of lithography and etching to form the second insulating layer 50 . A first group of second insulating layer openings 501 are included to expose the first semiconductor layer 101 , and a second group of second insulating layer openings 502 are included to expose the reflective structure 16 . During the patterning process, the first insulating layer covering region 20b covering the first insulating layer surrounding region 20a surrounding the exposed region 15 and the hole exposed region 17 is partially etched in the aforementioned first insulating layer 20 forming step removed to expose the first surface S1 and the second surface S2 of the first semiconductor layer 101 to form a first group of the second insulating layer openings 501 , the first insulating layer surrounding region 20a ′ and the first insulating layer Coverage area 20b'. In this embodiment, as shown in the top view of FIG. 5A , the second insulating layer openings 501 of the first group and the second insulating layer openings 502 of the second group have different widths and numbers. The shapes of the second insulating layer openings 501 of the first group and the second insulating layer openings 502 of the second group include a circle, an ellipse, a rectangle, a polygon, a ring, or any shape. In this embodiment, as shown in FIG. 5A , the second insulating layer openings 501 of the first group are elongated, separated from each other and corresponding to the plurality of hole exposed regions 17 respectively, and the second insulating layer openings 501 of the second group are elongated. The layer openings 502 are circular, separated from each other, distributed around the second insulating layer openings 501 of the first group, and arranged in a matrix.

When the second insulating layer 50 is a single-layer film, the second insulating layer 50 can protect the sidewalls of the semiconductor stack 10 to prevent the active layer 103 from being damaged by subsequent processes. When the second insulating layer 50 is a multi-layer film, the second insulating layer 50 can protect the sidewall of the semiconductor stack 10, and can include two or more materials with different refractive indices stacked alternately to form a Bragg reflector (DBR) structure, Selectively reflect specific wavelengths of light. The second insulating layer 50 is formed of non-conductive materials, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin) ), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), or fluorine Carbon polymer (Fluorocarbon Polymer), or inorganic materials, such as Silicone, glass (Glass), or dielectric materials, such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), niobium oxide (Nb ₂ O ₅ ), or magnesium fluoride (MgF _x ).

Continuing with the second insulating layer forming step, as shown in the top view of FIG. 6A and the cross-sectional view along the line AA' of FIG. 6A in FIG. 6B , the manufacturing method of the light-emitting element 1 includes a step of forming a conductive layer 60 . The conductive layer 60 can form a conductive material layer on the first semiconductor layer 101 and the second semiconductor layer 102 by means of evaporation or deposition, and then pattern the conductive material layer by means of lithography and etching to form the conductive layer 60 . As shown in FIG. 6A, the conductive layer 60 includes a first conductive region 60a and a second conductive region 60b, which are spatially separated from each other by an annular gap 60c. The first conductive region 60a of the conductive layer 60 contacts the first semiconductor layer 101 (ie, the first surface S1 ) in the surrounding exposed region 15 , and simultaneously exposes the region 17 through the first group of the second insulating layer openings 501 and all the holes. The first semiconductor layer 101 (ie, the second surface S2 ) is in contact, and extends to cover the sidewalls surrounding the exposed region 15 and the exposed region 17 of the hole to a part of the upper surface of the second insulating layer 50 . The first surface S1 of the region E1 includes a part of the surface that is not covered by the first conductive region 60a, which is a region S3. In this embodiment, from the top view, the outline of the semiconductor stack 10 is a rectangle, and the region S3 is disposed along one side of the rectangle. In another embodiment of the present application, the area E1 and the area S3 may be located at one or more corners of the rectangle. The second conductive regions 60b of the conductive layer 60 are respectively filled into the second insulating layer openings 502 of the second groups to contact the reflective structure 16 . In this embodiment, the second conductive regions 60b are in contact with the barrier layer of the reflective structure 16 . , and cover another part of the upper surface of the second insulating layer 50 . In this way, the first conductive region 60a is electrically connected to the first semiconductor layer 101, and is electrically insulated from the second semiconductor layer 102 by the second insulating layer 50, and the second conductive region 60b is electrically isolated from the second semiconductor layer 102. Make electrical connections. The material of the conductive layer 60 includes metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), Or platinum (Pt) or other metals or alloys or laminates of the above materials.

In one embodiment of the present application, the area of the conductive layer 60 is larger than that of all the active layers 103 when viewed from above.

In an embodiment of the present application, when the light-emitting element 1 has both the surrounding exposed region 15 and the one or more hole-exposed regions 17, and an external current is injected into the light-emitting element 1, the current is simultaneously conducted through the first conductive region 60a. To the first semiconductor layer 101 in the surrounding exposed region 15 and in the hole exposed region 17 , by dispersing one or more hole exposed regions 17 , and surrounding the surrounding exposed region 15 around the hole exposed region 17 , the The light field distribution of the light emitting element 1 is uniform, and the forward voltage of the light emitting element can be reduced.

In one embodiment of the present application, when the semiconductor stack 10 does not have one or more hole exposed regions 17 , the first conductive region 60 a can still be achieved by contacting the first semiconductor layer 101 in the surrounding exposed region 15 . Electrical connection. When an external current is injected into the light-emitting element 1, the current is conducted to the first semiconductor layer 101 surrounding the exposed region 15 through the first conductive region 60a, that is, the current injection region is equivalent to surrounding the semiconductor stack 10, so that the light-emitting element can be The light field distribution of 1 is uniform, and the forward voltage of the light-emitting element can be reduced.

Following the step of forming the conductive layer, as shown in FIG. 7A top view and FIG. 7B is a cross-sectional view along line A-A' in FIG. The electrode layer 30 can form a conductive material layer on the first semiconductor layer 101 and the second semiconductor layer 102 by means of evaporation or deposition, and then pattern the conductive material layer by means of lithography and etching to form the electrode layer 30 . As shown in FIG. 7A, the electrode layer 30 includes an electrode pad 30a, a ring electrode layer 30b extending from the electrode pad, and a connection electrode layer 30c spaced apart from the electrode pad 30a and the ring electrode layer 30b. . The electrode pads 30 a and the annular electrode layer 30 b are disposed along the surrounding exposed area 15 , and have a shape substantially corresponding to the surrounding exposed area 15 . More specifically, the ring electrode layer 30b is formed on the first conductive region 60a in the surrounding exposed region 15, and contacts the first conductive region 60a, that is, the ring electrode layer 30b contacts the first conductive region when viewed from above Around the 60a; the electrode pad 30a is formed on the region S3 and contacts the first semiconductor layer 101 in the region S3. One side of the electrode pad 30a adjacent to the semiconductor stack 10 is in contact with and overlaps the edge of the first conductive region 60a. In this way, the electrode pad 30a and the annular electrode layer 30b are electrically connected to the first semiconductor layer 101 . In this embodiment, the electrode pad 30 a is a single long rectangle and is disposed on one side of the substrate 11 from the top view. The electrode pad 30 a and the annular electrode layer 30 b form a closed pattern, and the closed pattern corresponds to surrounding the exposed area 15 . . A plurality of connection electrode layers 30c are correspondingly formed on each of the second conductive regions 60b, and the area of the connection electrode layers 30c is smaller than that of the second conductive regions 60b and does not exceed the range of each of the second conductive regions 60b. The material of the electrode layer 30 includes metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), or platinum (Pt) and other metals or alloys or laminates of the above materials.

In an embodiment of the present application, the electrode layer 30 may include one or more electrode pads 30 a, and the one or more electrode pads 30 a may be disposed on one or more corners of the substrate 11 .

In an embodiment of the present application, the electrode pad 30a, the ring electrode layer 30b and the connection electrode layer 30c can be formed simultaneously, and the electrode pad 30a, the ring electrode layer 30b and the connection electrode layer 30c have the same material.

In an embodiment of the present application, the electrode pad 30a and the ring electrode layer 30b can be formed first, and then the connection electrode layer 30c can be formed; The pad 30a, the ring electrode layer 30b and the connection electrode layer 30c may have different materials.

Following the electrode layer forming step, the manufacturing method of the light-emitting element 1 includes a third insulating layer 70 forming step. After the third insulating layer 70 forming step is completed, the top view shown in FIG. 8A and FIG. 8B are formed along the lines. Laminate 1' shown in the cross-sectional view of line AA' in Fig. 8A. The third insulating layer 70 can form an insulating material layer on the stack 1' by evaporation or deposition, and cover the electrode layer 30 and the conductive layer 60, and then pattern the insulating material layer by lithography and etching. , to form a first group of third insulating layer openings 701 in the third insulating layer 70 . The third insulating layer openings 701 of the first group are correspondingly formed on the second insulating layer openings 502 and the second conductive region 60b of the second group to expose the connection electrode layer 30c and the second conductive region 60b. The width of the third insulating layer openings 701 of the first group is not larger than the width of the second conductive region 60b and not smaller than the width of the connecting electrode layers 30c, so that each connecting electrode layer 30c can be insulated by the third insulating layer of the first group. The layer opening 701 is completely exposed. Like the second insulating layer 50 , the third insulating layer 70 may have a single-layer or multi-layer structure. When the third insulating layer 70 is a multilayer film, two or more materials with different refractive indices can be alternately stacked to form a Bragg reflector (DBR) structure to selectively reflect light of a specific wavelength.

In an embodiment of the present application, the electrode layer may not have the connecting electrode layer 30c. When the electrode layer 30 does not have the connection electrode layer 30c, each of the second conductive regions 60b is exposed by the third insulating layer openings 701 of the first group.

Following the third insulating layer forming step, the manufacturing method of the light-emitting element 1 includes a bonding step. As shown in the cross-sectional views of FIGS. 9A and 9B, a first metal layer 26a is formed on the third insulating layer 70, and then forming a first bonding layer 28a on the first metal layer 26a; and providing a conductive substrate 12, forming a second metal layer 26b on the conductive substrate 12, and then forming a second bonding layer 28b on the second metal layer 26b . The first bonding layer 28a and the second bonding layer 28b are bonded together at a heating temperature higher than room temperature. In this embodiment, the heating temperature is lower than 200°C. The material of the conductive substrate 12 may include semiconductor materials such as silicon (Si), or metal materials such as copper (Cu), molybdenum (Mo), tungsten (W), or alloys or composite materials of the foregoing materials. The material of the first metal layer 26a includes a metal material with a relatively high melting point, such as nickel (Ni), titanium (Ti), copper (Cu), gold (Au), platinum (Pt), and rhodium (Rh). The material of the second metal layer 26b includes a metal material with a lower melting point, such as cadmium (Cd), tin (Sn), and indium (In). In an embodiment of the present application, the metal material with a lower melting point refers to a metal material with a melting point lower than 200° C., such as indium (In). The metal material with a higher melting point refers to a metal material with a melting point higher than 200° C., such as titanium (Ti) and gold (Au). The bonding method can be reversed and positioned on the conductive substrate 12, or the conductive substrate 12 can be reversed and bonded on the stacked layer 1'. After the bonding step is completed, the first metal layer 26a, the first bonding layer 28a, the second metal layer 26b and the second bonding layer 28b form a bonding structure 28', as shown in FIG. 9B. The bonding structure 28' fills the first group of the third insulating layer openings 701, and is in contact with the connection electrode layer 30c and the second conductive region 60b. In this way, the conductive substrate 12 is electrically connected to the second conductive region 60b and the second semiconductor layer 102 through the first group of the third insulating layer openings 701 .

In one embodiment of the present application, the size of the conductive substrate 12 includes a wafer-level substrate or a die-level substrate. Wafers referred to here are not limited to circular shapes, but include polygonal or irregular shapes. The wafer referred to here can be divided into a plurality of light-emitting elements at the die level in the subsequent process; it is also possible to directly form light-emitting elements without dividing.

When the first metal layer 26a and the first bonding layer 28a are formed, the connection electrode layer 30c can reduce the height difference formed in the third insulating layer openings 701 of the first group due to the thickness of the third insulating layer 70, so as to improve the Bonding yield. In an embodiment of the present application, the electrode layer 30 does not have the connection electrode layer 30c, and the first metal layer 26a fills the first group of the third insulating layer openings 701 and contacts the second conductive region 60b. After the bonding step is completed, the conductive substrate 12 can also be electrically connected to the second conductive region 60b and the second semiconductor layer 102 .

In an embodiment of the present application, in the step of forming the first metal layer 26a, it can be achieved by forming metal materials in different regions on the stack 1' in stages. For example, as shown in FIG. 18 , when the thickness difference of each layer structure in the stack 1 ′ is too large, especially around the edge of the exposed area 15 and the adjacent area of the electrode pad 30 a , the height difference of the first metal layer 26 a is likely to occur Therefore, a thick metal material 261 can be formed on the entire third insulating layer 70 first, and then in the region where the height difference of the thick metal material 261 is large, the metal materials 262 and 263 are formed in stages to form a relatively flat The first metal layer 26a improves the yield of the bonding step. The graded metal materials may be the same material or different materials.

Following the bonding step, the manufacturing method of the light-emitting element 1 includes a step of removing the growth substrate 11 , as shown in the cross-sectional view of FIG. 10A , in this embodiment, after the laminate 1 ′ is inverted and bonded to the conductive substrate 12 , and then using, for example, In the laser lift-off process, a laser (not shown) is provided from the backside of the growth substrate 11 , that is, the surface of the growth substrate 11 away from the conductive substrate 12 , to remove the growth substrate 11 and expose the semiconductor stack 10's surface 10s.

In an embodiment of the present application, following the step of removing the growth substrate, the manufacturing method of the light-emitting device 1 may include a roughening step. As shown in the cross-sectional view of FIG. 10B , an etchant is provided to etch the surface 10s of the semiconductor stack 10 to form a roughened structure TS on the surface 10s, which can improve the light extraction efficiency of the light-emitting element. The roughened structure TS can be a regular or irregular rough surface. The material of the etching solution may include an alkaline solution, such as potassium hydroxide (KOH) or sodium hydroxide (NaOH).

In an embodiment of the present application, after the growth substrate 11 is removed, dry etching, wet etching or a combination of both can be used to remove the buffer layer (not shown) remaining on the surface 10s, and then roughen it. step.

In an embodiment of the present application, while the buffer layer (not shown) remaining on the surface 10s is removed, the roughened structure TS can be formed by adjusting the etching process conditions.

Following the roughening step, the manufacturing method of the light-emitting element 1 includes a step of forming a wire bonding pad 36 . First, as shown in the cross-sectional view of FIG. 11A, the electrode pad 30a may be removed from the surface 10s of the semiconductor stack 10 or the roughened structure TS by dry etching and/or wet etching before or after the roughening step The upper part of the first semiconductor layer 101 exposes the electrode pad 30a. The exposed area can be regarded as a non-closed opening 38, the shape of which is roughly corresponding to the electrode pad 30a when viewed from above. Before the non-closed opening 38 is formed, the first surface S1 in the surrounding exposed area 15 has a width W1. W1 is greater than a width W2 of the non-closed opening 38. Therefore, after the surrounding exposed area 15 and the non-closed opening 38 are formed successively, the electrode pad 30a is connected to the side of the first surface S1, and is formed in the surrounding exposed area 15 and not connected to the non-closed opening 38. Corresponding to the closed opening 38, the electrode pad 30a has a width W3 greater than W2. From the top view, the electrode pad 30a is disposed on one side of the light-emitting element 1; when the electrode layer 30 includes one or more electrode pads 30a, the electrode pad 30a It can be arranged at one or more corners of the light-emitting element 1 . The upper surface 301 of the electrode pad 30a has a contact region 301a connected to the first surface S1 of the first semiconductor layer 101. In one embodiment, the contact region 301a is connected to the first surface of the first semiconductor layer 101 through the first conductive region 60a S1; In another embodiment, in addition to being electrically connected to the first surface S1 through the first conductive region 60a, the contact region 301a may further include a region directly connected to the first surface S1 of the first semiconductor layer 101; the electrode pad 30a The upper surface 301 further has an exposed region 301 b exposed by the non-closed opening 38 and does not overlap with the semiconductor stack 10 . The thickness of the first semiconductor layer 101 can be between 3 μm and 4 μm, and can be divided into a first portion 101 a and a second portion 101 b. The thickness of the first portion 101a corresponds to the depth of the non-closed opening 38, about 1.5-3 μm, and the thickness of the second portion 101b corresponds to the surrounding exposed area 15, and is about 1-1.5 μm. The electrode pads 30 a can be electrically connected to the first semiconductor layer 101 but are not formed on the light-emitting surface, so that the light of the light-emitting element 1 will not be shielded.

In an embodiment of the present application, while removing a part of the first semiconductor layer 101 above the electrode pad 30 a to form the non-closed opening 38 , other parts of the first semiconductor layer 101 may be further etched and removed to expose a part of the first semiconductor layer 101 . The third insulating layer 70 serves as a dicing line for subsequent dicing steps. The position and size of each light-emitting element 1 are defined by a plurality of cutting lines.

Next, as shown in FIG. 11B , a wire bonding pad 36 is formed on the exposed region 301 b , and there is a gap between the wire bonding pad 36 and the adjacent semiconductor stack 10 without directly contacting the semiconductor stack 10 . From the top view, the shape of the wire bonding pad 36 is substantially the same as that of the electrode pad 30a, and the width and area of the wire bonding pad 36 are smaller than those of the electrode pad 30a. In subsequent wire bonding operations, solder balls (not shown in the figure) can be placed above the wire bonding pads 36 to connect the light-emitting element 1 to an external power source or other electronic components.

Following the step of forming the wire bonding pad, as shown in the cross-sectional view of FIG. 11B , the manufacturing method of the light-emitting element 1 includes a step of forming a protective layer 80 . The protective layer 80 can be formed on the light-emitting element 1 by evaporation or deposition, covering the surface of the light-emitting element 1 relative to the conductive substrate 12, and then patterned by lithography and etching to form the protective layer opening 801 , the bonding pad 36 is exposed. The protective layer 80 covers the surface and sidewalls of the semiconductor stack 10, and covers the gap between the wire bonding pad 36 and the semiconductor stack 10, so as to provide protection for the light-emitting element 1 and prevent the light-emitting element 1 from being affected by the temperature, humidity and static electricity of the external environment. adversely affect its performance. In an embodiment of the present application, the conductive substrate 12 and the semiconductor stack 10 are at the wafer level. After the protective layer 80 is formed, the wafer-level conductive substrate 12 can be cut. The layer 80 , the conductive substrate 12 and the bonding structure 28 ′ are cut to form a plurality of light emitting elements 1 . The scribe line is formed by removing the first semiconductor layer 101 by etching in the above-mentioned forming step of the non-closed opening 38 . Cutting methods include cutting knife or laser cutting.

FIG. 12 is a cross-sectional view of a light-emitting element 1a disclosed in an embodiment of the present application. The difference from the light-emitting element 1 is that after the protective layer 80 is formed, a wavelength conversion layer 42 can be selectively formed on the protective layer. 80 , the wavelength conversion layer 42 can be a phosphor layer or a quantum dot material, and the wavelength of the light emitted by the semiconductor stack 10 can be converted into light of different wavelengths through the wavelength conversion layer 42 . The step of forming the wavelength conversion layer 42 is completed before the step of cutting.

In the light-emitting element 1 formed by the manufacturing method of this embodiment, as shown in FIG. 11B , when an external current is injected into the light-emitting element 1 from the wire bonding pad 36 and the conductive substrate 12 , the current is first transmitted to the electrode pad 30 a and the ring-shaped electrode layer 30 b , and then diffused through the first conductive region 60 a , and simultaneously conducted to the first semiconductor layer 101 in the surrounding exposed region 15 and the exposed region 17 of the hole portion. In this way, the current can be uniformly distributed in the semiconductor stack 10 , thereby making the light field distribution of the light emitting element 1 uniform, and reducing the forward voltage of the light emitting element 1 . In addition, the third insulating layer 70 can insulate the electrode pad 30a and the ring electrode layer 30b from the second semiconductor layer 102 and the active layer 103, and the electrode pad 30a, the ring electrode layer 30b and the active layer 103 are located in the horizontal direction of the light-emitting element 1 11B, the semiconductor stack 10 is inverted on the conductive substrate 12, so the active layer 103 is located above the reflective structure 16 and the second conductive region 60b as a whole; the wire bonding pads 36 are disposed on the non-closed openings 38 Among them, corresponding to the position of the electrode pad 30a, there is no electrode structure on the light-emitting surface of the light-emitting element 1 corresponding to the active layer 103; therefore, the light emitted by the active layer 103 will not be shielded by the electrode structure of the light-emitting element 1, which improves the light emission efficiency.

No. 17B shows a light-emitting element 2 disclosed in an embodiment of the present application; Figures 13A to 17B show a method for manufacturing the light-emitting element 2 of the present application.

The manufacturing method of the light-emitting element 2 includes a mesa formation step, a first insulating layer 20 formation step, a current dispersion layer 18 formation step, and a reflection structure 16 formation step. The above steps and the structure of each layer are the same as those described in the above-mentioned manufacturing method of the light-emitting element 1 , and thus will not be repeated here.

As shown in the top view of FIG. 13A and the cross-sectional view along AA' of FIG. 13A, the manufacturing method of the light-emitting element 2 includes the formation of a second insulating layer 50' after the above-mentioned steps of forming the reflective structure are completed. step. The steps of forming the second insulating layer 50 ′ are similar to the above-mentioned manufacturing method of the light-emitting element 1 , except that the second insulating layer 50 ′ further includes a second insulating layer protrusion 503 extending toward the region E1 surrounding the exposed region 15 and formed in the on the first surface S1 surrounding the exposed region 15 . The area of the second insulating layer 50 ′ with two more second insulating layer protrusions 503 covering the first surface S1 surrounding the exposed region 15 is compared to the second insulating layer without the second insulating layer protrusions 503 having a rectangular outline The area of the layer covering the first surface S1 surrounding the exposed region 15 is large. The area E1 surrounding the exposed area 15 has a wider width, and the first surface S1 of the area E1 includes an area S3 whose surface is not covered by the first insulating layer 20 and the second insulating layer 50'. In this embodiment, the semiconductor stack 10 is a rectangle, and the region S3 is disposed along one side of the rectangle. In another embodiment of the present application, the area S3 may be located at one or more corners of the rectangle.

Similar to the manufacturing method of the light-emitting unit 1 , in the process of patterning the second insulating layer 50 ′, in the aforementioned first insulating layer 20 forming step, the first insulating layer surrounding region 20 a and the hole portion surrounding the exposed region 15 are covered. The first insulating layer covering region 20b in the exposed region 17 is partially etched and removed to expose the first surface S1 and the second surface S2 of the first semiconductor layer 101 to form a first group of second insulating layer openings 501 , a first insulating layer surrounding area 20a' and a first insulating layer covering area 20b'. The first insulating layer surrounding region 20a' just below the second insulating layer protrusion 503 is reserved, as shown in FIG. 13B.

Following the step of forming the second insulating layer 50', as shown in the top view of FIG. 14A and the cross-sectional view along the line AA' of FIG. 14A in FIG. 14A, the manufacturing method of the light-emitting element 2 includes a conductive layer 60 ' Formation step. The steps of forming the conductive layer 60' are similar to the manufacturing method of the aforementioned light-emitting element 1, except that, as shown in FIG. 14A, the conductive layer 60' includes a first conductive region 60a', a second conductive region 60b' and a third conductive region 60d' are spatially separated from each other by a slit 60c'. In the present embodiment, the first conductive region 60 a ′ has a discontinuous annular strip pattern, including a U-shaped strip pattern surrounding three sides of the semiconductor stack 10 and a straight strip adjacent to surrounding the region E1 in the exposed region 15 . shape pattern. The first conductive region 60a' contacts the first semiconductor layer 101 (ie, the first surface S1) surrounding the exposed region 15, is electrically connected to the first semiconductor layer 101, and covers the periphery of the second insulating layer 50', and is connected to the second insulating layer 50'. The semiconductor layer 102 is electrically insulating. The second conductive region 60b' is located above the second semiconductor layer 102, covers the upper surface of the second insulating layer 50' and fills the second insulating layer openings 502 of the second groups to contact the reflective structure 16 and the second semiconductor layer 102 is electrically connected. Wherein, as shown in FIG. 14A, the second conductive region 60b' includes a second conductive region protrusion 603 corresponding to the second insulating layer protrusion 503, and the second conductive region protrusion 603 extends from the second conductive region 60' out, cover and contact the second insulating layer protrusion 503, so that there is a second insulating layer protrusion 503 between the second conductive area protrusion 603 and the first surface S1, so the second conductive area protrusion 603 and the first surface S1 have the second insulating layer protrusion 503. A semiconductor layer 101 is electrically insulating. From the top view, except for the region of the second conductive region protrusion 603, the edge of the second conductive region 60b' does not exceed the range of the second semiconductor layer 102; in this embodiment, the two second conductive regions protrude The portion 603 is disposed at the discontinuity of the first conductive region 60a', that is, between the first conductive region 60a' of the U-shaped strip pattern and the first conductive region 60a' of the straight strip pattern. The third conductive region 60d' corresponds to the hole exposed region 17, and is in contact with the second surface S2 of the first semiconductor layer 101 through the first group of second insulating layer openings 501, and is electrically connected to the first semiconductor layer 101, and The second insulating layer 50 ′ near the exposed region 17 of the hole portion is covered. The material of the conductive layer 60' is the same as the material of the conductive layer 60 of the aforementioned light-emitting element 1, and thus will not be repeated.

In one embodiment of the present application, the area of the conductive layer 60' is larger than that of all the active layers 103 when viewed from above.

In one embodiment of the present application, when the light-emitting element 2 has both the hole-exposed regions 17 dispersedly arranged and the structure surrounding the hole-exposed region 17 surrounding the exposed region 15, when an external current is injected into the light-emitting element 2, the current A plurality of current injection regions can be formed by contacting the first conductive region 60a' with the first semiconductor layer 101 in the surrounding exposed region 15 and the first semiconductor layer 101 in the exposed region 17 of the hole, so that the injection current can be uniformly dispersed. , thereby reducing the forward voltage of the light-emitting element 2 and making the light field distribution of the light-emitting element 2 uniform.

In one embodiment of the present application, when the semiconductor stack 10 does not have one or more hole-exposed regions 17 , the first conductive region 60 a ′ can still be contacted with the first semiconductor layer 101 in the surrounding exposed region 15 and its exposed regions 15 . achieve electrical connection. When an external current is injected into the light-emitting element 1, the current is conducted to the first semiconductor layer 101 surrounding the exposed region 15 through the first conductive region 60a', that is, the current injection region is equivalent to surrounding the semiconductor stack 10, so that light can be emitted The light field distribution of the element 2 is uniform, and the forward voltage of the light-emitting element 2 can be reduced.

Following the conductive layer forming step, as shown in the top view of FIG. 15A and the cross-sectional view along line A-A' of FIG. 15B in FIG. 15A , the manufacturing method of the light-emitting element 2 includes a step of forming an electrode layer 30'. The steps of forming the electrode layer 30' are similar to the manufacturing method of the aforementioned light-emitting element 1. The difference is that, as shown in FIG. 15A, the electrode layer 30' includes an electrode pad 30a' and a ring-shaped electrode layer 30b that are spaced apart from each other. ' and a connecting electrode layer 30c'. The ring electrode layer 30b' is disposed along the surrounding exposed area 15, formed on the first conductive area 60a' in the surrounding exposed area 15, and contacts the first conductive area 60a', that is, the ring electrode is viewed from above. The layer 30b ′ and the first conductive region 60a ′ also have a discontinuous annular stripe pattern, including a U-shaped stripe pattern surrounding the three sides of the semiconductor stack 10 and a straight stripe pattern surrounding the region E1 in the exposed region 15 . pattern. The line width of the ring electrode layer 30b' is smaller than that of the first conductive region 60a'. The electrode pad 30a' is formed on the region S3 and contacts the first semiconductor layer 101 of the region S3. One side of the electrode pad 30a' adjacent to the semiconductor stack 10 has an electrode pad protrusion 303, which is opposite to the protrusion direction of the second conductive region protrusion 603 and overlaps and contacts with it. In the present embodiment, the electrode pad 30a' is disposed adjacent to the area E1 in the surrounding exposed area 15 when viewed from above. A plurality of connection electrode layers 30c' are correspondingly formed on each of the second conductive regions 60d', and the area of the connection electrode layers 30c' is smaller than that of the second conductive regions 60d' and does not exceed the range of each of the second conductive regions 60d'. The material of the electrode layer 30' includes metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), or platinum (Pt) ) or other metals or alloys or laminates of the above materials.

In an embodiment of the present application, the electrode layer 30' may include one or more electrode pads 30a', and the one or more electrode pads 30a' may be disposed on one or more corners of the substrate 11.

In an embodiment of the present application, the electrode pad 30a', the ring electrode layer 30b' and the connection electrode layer 30c' can be formed at the same time, and the electrode pad 30a', the ring electrode layer 30b' and the connection electrode layer 30c' have the same material.

In an embodiment of the present application, the electrode pad 30a' and the ring electrode layer 30b' may be formed first, and then the connection electrode layer 30c' may be formed; the connection electrode layer 30c' may also be formed first, and then the electrode pad 30a' and the ring electrode may be formed layer 30b', and the electrode pad 30a', the ring electrode layer 30b' and the connection electrode layer 30c' may have different materials.

Following the electrode layer forming step, the manufacturing method of the light-emitting element 2 includes a third insulating layer 70' forming step. After the step of forming the third insulating layer 70' is completed, the stack 2' is formed as shown in the top view of FIG. 16A and the cross-sectional view along the line AA' of FIG. 16B in FIG. 16B. The third The steps of forming the insulating layer 70' are similar to the manufacturing method of the aforementioned light-emitting element 1, except that, as shown in FIG. 16A, the third insulating layer 70' includes a first group of third insulating layer openings 701' and a Two groups of third insulating layer openings 702 . The first group of third insulating layer openings 701 ′ are correspondingly formed on the first conductive region 60 a ′. In this embodiment, from a top view, the first group of third insulating layer openings 701 ′ and the first The conductive region 60a' also has a discontinuous ring-shaped strip pattern, and the opening width of the third insulating layer openings 701' of the first group can be smaller than the width of the first conductive region 60a', so as to expose part of the first conductive region The region 60a' and the ring electrode layer 30b'. In another embodiment of the present application, the first group of third insulating layer openings 701 ′ can be correspondingly formed on the ring electrode layer 30b ′ to expose the ring electrode layer 30b ′; in another embodiment of the present application , the first group of third insulating layer openings 701 ′ exposes the first conductive region 60 a ′. The second group of third insulating layer openings 702 are correspondingly formed on the hole exposed region 17, exposing part of the third conductive region 60d' and the electrode connection layer 30c'.

In an embodiment of the present application, the electrode layer 30' may not have the connection electrode layer 30c'. When the electrode layer 30' does not have the connection electrode layer 30c', the third insulating layer openings 702 of the second group expose the third conductive regions 60d'.

Following the step of forming the third insulating layer 70', the manufacturing method of the light-emitting element 2 includes a step of bonding, a step of removing the growth substrate 11, and a step of roughening. The above steps and the bonding structure are the same as those described in the above-mentioned manufacturing method of the light-emitting element 1, and thus are not repeated here. In one embodiment of the present application, the size of the conductive substrate 12 includes a wafer-level substrate or a die-level substrate. Wafers referred to here are not limited to circular shapes, but include polygonal or irregular shapes. The wafer referred to here can be divided into a plurality of light-emitting elements at the die level in the subsequent process; it is also possible to directly form light-emitting elements without dividing. After the above steps are completed, as shown in FIG. 17A, the bonding structure 28' is filled into the third insulating layer openings 701' of the first group, and is in contact with the ring electrode layer 30b' and/or the first conductive region 60a', And the third insulating layer openings 702 filled in the second group are in contact with the connection electrode layer 30c' and/or the third conductive region 60d'. In this way, the conductive substrate 12 is electrically connected to the first semiconductor layer 101 .

When the bonding structure 28' is formed, the connection electrode layer 30c' can reduce the thickness of the third insulating layer 70', the conductive layer 60', the second insulating layer 50' and the reflective structure 16 in the second group of third insulating layers. The height difference formed by the layer opening 702 can improve the bonding yield. In an embodiment of the present application, the electrode layer 30' does not have the connecting electrode layer 30c', and the bonding structure 28' fills the second group of the third insulating layer openings 702, and is in direct contact with the third conductive region 60d'. After the bonding step is completed, the conductive substrate 12 is also electrically connected to the first semiconductor layer 101 .

Like the aforementioned method of manufacturing the light-emitting element 1, in an embodiment of the present application, in the step of forming the first metal layer 26a in the method of manufacturing the light-emitting element 2, the metal material can also be formed in different regions on the stack 2' by stages. to achieve.

As with the aforementioned manufacturing method of the light-emitting element 1, in an embodiment of the present application, the bonding method can be reversed and aligned on the conductive substrate 12, or the conductive substrate 12 can be inverted and aligned on the laminate 2'.

Following the roughening step, as shown in the cross-sectional view of FIG. 17A, the manufacturing method of the light-emitting element 2 includes a step of forming a wire bonding pad 36'. First, as in the aforementioned manufacturing method of the light-emitting unit 1, a non-closed opening 38 is formed first, the shape of which is roughly corresponding to the area of the electrode pad 30a' other than the electrode pad protrusion 303 when viewed from above. Before the non-closed opening 38 is formed, the first surface S1 in the surrounding exposed area 15 has a width W1. W1 is larger than a width W2 of the non-closed opening 38, so after the surrounding exposed area 15 and the non-closed opening 38 are formed successively, the electrode pad 30a' is connected to the first surface S1, and is formed in the surrounding exposed area 15 and not connected to the non-closed opening 38. Corresponding to the closed opening 38 , the electrode pad 30 a ′ has a width W3 greater than W2 at the electrode protrusion 303 . The electrode pad protrusion 303 directly contacts and connects to the second conductive region protrusion 603 and is electrically connected to the second semiconductor layer 102 ; the upper surface 301 ′ of the electrode pad 30 a ′ has an exposed area 301 b exposed by the non-closed opening 38 ', which does not overlap with the semiconductor stack 10 . The thickness of the first semiconductor layer 101 can be between 3 μm and 4 μm, and can be divided into a first portion 101 a and a second portion 101 b. The thickness of the first portion 101a corresponds to the depth of the non-closed opening 38, about 1.5-3 μm, and the thickness of the second portion 101b corresponds to the surrounding exposed area 15, and is about 1-1.5 μm. The electrode pads 30a' can be electrically connected to the second semiconductor layer 102 but are not formed on the light-emitting surface, so that the light of the light-emitting element 2 will not be shielded. In an embodiment of the present application, the electrode layer 30' may include one or more electrode pads 30a', and the one or more electrode pads 30a' may be disposed on one or more corners of the substrate 11.

In an embodiment of the present application, while removing a part of the first semiconductor layer 101 above the electrode pad 30 a ′ to form the non-closed opening 38 , other parts of the first semiconductor layer 101 may be further etched and removed, exposing the first semiconductor layer 101 . A portion of the third insulating layer 70' is used as a dicing line for the subsequent dicing step. The position and size of each light-emitting element 2 are defined by a plurality of cutting lines.

Next, as shown in FIG. 17B, a wire bonding pad 36 is formed on the exposed area 301b'. The structure, position, and function of the wire bonding pad 36 are the same as those described in the light-emitting element 1, and thus will not be repeated.

Following the step of forming the wire bonding pad 36, the manufacturing method of the light-emitting element 2 also includes the step of forming the protective layer 80, and the step of forming the protective layer 80, which can cut the wafer-level conductive substrate 12, and the cutting step includes cutting the protective layer 80, The conductive substrate 12 and the bonding structure 28 ′ are cut to form a plurality of light emitting elements 2 . The scribe line is formed by removing the first semiconductor layer 101 by etching in the above-mentioned forming step of the non-closed opening 38 . Cutting methods include cutting knife or laser cutting. In addition, the wavelength conversion layer 42 can also be selectively formed on the protective layer 80 before the cutting step.

In the light-emitting element 2 formed by the manufacturing method of this embodiment, as shown in FIG. 17B, when an external current is injected into the light-emitting element 2 from the wire bonding pad 36 and the conductive substrate 12, the current is first transmitted to the electrode pad 30a', and then passes through the electrode pad. The contact between the protruding portion 303 and the protruding portion 603 of the second conductive region is diffused in the second conductive region 60b ′ and conducted to the second semiconductor layer 102 . In addition, the annular first conductive region 60a' surrounds the third conductive region 60d' disposed therein, so that the current can be conducted to the first semiconductor layer 101 in the surrounding exposed region 15 and the hole exposed region 17 at the same time. In this way, the current can be uniformly distributed in the semiconductor stack 10 , thereby making the light field distribution of the light emitting element 2 uniform, and reducing the forward voltage of the light emitting element 2 . The third insulating layer 70 ′ can insulate the electrode pad 30 a ′ and the second conductive region 60 b ′ from the first semiconductor layer 102 , and the electrode pad 30 a ′, the ring electrode layer 30 b ′ and the active layer 103 are located between the horizontal direction of the light-emitting element 2 17B, the semiconductor stack 10 is inverted on the conductive substrate 12, so the active layer 103 is located above the reflective structure 16 and the second conductive region 60b' as a whole; the wire bonding pads 36 are disposed in the non-closed openings 38, corresponding to the position of the electrode pad 30a', no electrode structure is provided on the light-emitting surface of the light-emitting element 2 corresponding to the active layer 103; therefore, the light emitted by the active layer 103 will not be shielded by the electrode structure of the light-emitting element 2, Improve luminous efficiency.

However, the above-mentioned embodiments are merely illustrative to illustrate the principles and effects of the present application, and are not intended to limit the present application. Anyone with ordinary knowledge in the technical field to which this application pertains can make modifications and changes to the above embodiments without departing from the technical principles and spirit of this application. Therefore, the scope of protection of the right of this application is listed in the patent scope of the application described later.

1, 2: Light-emitting element 1', 2': Laminate 10: Semiconductor stack 11: Growth substrate 12: Conductive substrate 101: the first semiconductor layer 102: the second semiconductor layer 103: Active layer 10s: Surface of semiconductor stack 15: Surround the exposed area 16: Reflective Structure 17: Hole exposed area 18: Current Dispersion Layer 20: The first insulating layer 20a, 20a': the surrounding area of the first insulating layer 20b, 20b': first insulating layer coverage area 26a: first metal layer 261, 262, 263: Metal Materials 26b: second metal layer 28a: First bonding layer 28b: Second bonding layer 28': Engagement structure 30, 30': electrode layer 30a, 30a': electrode pads 30b, 30b': ring electrode layer 30c, 30c': connecting electrode layers 301, 301’: upper surface 301a: Contact area 301b, 301b': exposed area 303: Electrode pad protrusion 36: Line pad 38: Opening 42: wavelength conversion layer 50, 50': the second insulating layer 501: openings for the second insulating layer of the first group 502: the second insulating layer openings of the second group 503: the second insulating layer protrusion 60, 60': Conductive layer 60a, 60a': the first conductive area 60b, 60b': the second conductive area 60c, 60c': gap 60d': the third conductive area 603: the second conductive area protrusion 70, 70': the third insulating layer 701, 701': the third insulating layer openings of the first group 702: the third insulating layer opening of the second group 80: protective layer S1: first surface S2: Second surface S3: Region E1: Area around one of the exposed areas TS: Coarse Structure

[FIG. 1A to FIG. 12] are a method of manufacturing the light-emitting element 1 disclosed in an embodiment of the present invention. [FIG. 13 to FIG. 17B] are the manufacturing method of the light-emitting element 2 disclosed in an embodiment of the present invention. [FIG. 18] is a manufacturing method of the light-emitting element 1 disclosed in another embodiment of the present invention.

1: Light-emitting element

10: Semiconductor stack

12: Conductive substrate

15: Surround the exposed area

16: Reflective Structure

17: Hole exposed area

18: Current Dispersion Layer

20': first insulating layer

20a': Surrounding area of the first insulating layer

20b': first insulating layer coverage area

28': Engagement structure

30: Electrode layer

30a: Electrode pads

30b: Ring electrode layer

30c: connecting electrode layer

301b: Exposed areas

36: Line pad

50: Second insulating layer

501: openings for the second insulating layer of the first group

502: the second insulating layer openings of the second group

60: Conductive layer

70: The third insulating layer

701: the third insulating layer opening of the first group

S1: first surface

S2: Second surface

TS: Coarse Structure

Claims (10)

A light-emitting element, including: a semiconductor stack has a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; one or more hole-exposed regions within the semiconductor stack exposing the first semiconductor layer; a first insulating layer on the semiconductor stack, comprising one or more first openings corresponding to the one or more hole exposure regions, and one or more second openings on the second semiconductor layer; one or more first conductive layers, corresponding to the one or more hole exposed regions, are electrically connected to the first semiconductor layer through the one or more first openings; one or more second conductive layers located on the second semiconductor layer and electrically connected to the second semiconductor layer through the one or more second openings; a first electrode layer located on the one or more first conductive layers and electrically connected to the first semiconductor layer; a bonding layer on the first electrode layer; a second insulating layer located between the one or more second conductive layers and the bonding layer to electrically insulate the one or more second conductive layers and the bonding layer; a conductive substrate, wherein the semiconductor stack is located on one side of the bonding layer, and the conductive substrate is located on the other side of the bonding layer relative to the semiconductor stack; an exposed region located on a side or a corner of the light-emitting element, not overlapping the semiconductor stack; and A wire bonding pad is located on the exposed area and is electrically connected to the one or more first conductive layers or the one or more second conductive layers. The light-emitting element according to claim 1, wherein the first electrode layer comprises one or more connecting electrode layers corresponding to the one or more first conductive layers. The light-emitting device as claimed in claim 2, wherein the one or more connecting electrode layers are electrically connected to the bonding layer. The light-emitting device according to claim 2, wherein the area of the one or more connecting electrode layers is smaller than the area of the one or more first conductive layers. The light-emitting element as described in claim 1, further comprising a reflective structure and/or a current dispersion layer on the second semiconductor layer. The light-emitting element as described in claim 1, further comprising a ring-shaped electrode layer adjacent to a periphery of the light-emitting element. The light-emitting device as claimed in claim 1, wherein the one or more second conductive layers include a second conductive layer protruding portion beyond the edge of the second semiconductor layer, and the wire bonding pad is formed by the second conductive layer The protrusion is electrically connected to the second semiconductor layer. The light-emitting element of claim 1, wherein the one or more second conductive layers and the one or more first conductive layers are spatially separated from each other. The light-emitting device as described in claim 1, further comprising a protective layer covering a surface of the semiconductor stack relative to the conductive substrate, wherein the protective layer includes a protective layer opening to expose the wire bonding pad. The light-emitting device as claimed in claim 9, wherein the protective layer covers a gap between the wire bonding pad and the semiconductor stack.

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