為了使本發明之敘述更加詳盡與完備，請參照下列實施例之描述並配合相關圖示。惟，以下所示之實施例係用於例示本發明之發光元件，並非將本發明限定於以下之實施例。又，本說明書記載於實施例中的構成零件之尺寸、材質、形狀、相對配置等在沒有限定之記載下，本發明之範圍並非限定於此，而僅是單純之說明而已。且各圖示所示構件之大小
或位置關係等，會由於為了明確說明有加以誇大之情形。更且，於以下之描述中，為了適切省略詳細說明，對於同一或同性質之構件用同一名稱、符號顯示。
In order to make the description of the present invention more detailed and complete, please refer to the description of the following embodiments together with the relevant figures. However, the examples shown below are for illustrating the light-emitting device of the present invention, and the present invention is not limited to the following examples. In addition, the dimensions, materials, shapes, relative arrangements, etc. of the constituent parts described in the embodiments in this specification are not limited, and the scope of the present invention is not limited thereto, but is merely illustrative. And the size of the components shown in each diagram
Or positional relationship, etc., may be exaggerated for the sake of clarity. In addition, in the following description, in order to omit detailed description appropriately, the same name and symbol are used for the same or similar member.
第1圖係本發明一實施例中所揭示之一發光元件1的上視圖。第2圖係沿著第1圖之切線A-A’的剖面圖。第3圖係沿著第1圖之切線B-B’的剖面圖。第4圖係沿著第1圖之切線C-C’的剖面圖。第5圖係沿著第1圖之切線D-D’的剖面圖。第6圖係本發明一實施例中所揭示之發光元件1的部分上視圖。第7圖係沿著第6圖之切線E-E’的剖面圖。第8圖係本發明一實施例中所揭示之第1圖的X區域之剖面圖。
FIG. 1 is a top view of a light emitting element 1 disclosed in an embodiment of the present invention. Fig. 2 is a sectional view along the tangent line A-A' of Fig. 1. Fig. 3 is a sectional view along the tangent line B-B' of Fig. 1. Figure 4 is a sectional view along the tangent line C-C' of Figure 1. Figure 5 is a sectional view along the tangent line D-D' of Figure 1. Fig. 6 is a partial top view of the light-emitting element 1 disclosed in an embodiment of the present invention. Fig. 7 is a sectional view along the tangent line E-E' of Fig. 6. Fig. 8 is a cross-sectional view of area X in Fig. 1 disclosed in an embodiment of the present invention.
如第1圖及第6圖之上視圖，及第2圖~第5圖、第7圖、第8圖之剖面圖所示，發光元件1包含一半導體平台100t具有一半導體疊層100；一包含金屬材料之第一反射結構18位於半導體平台100t上；以及一包含絕緣材料之第二反射結構19位於第一反射結構18上。如第5圖及第7圖所示，第一反射結構18包含一第一開口180，第二反射結構19包含一第二開口192，其位置係相對於第一開口180的位置，第二反射結構19包覆第一開口180處的第一反射結構18，且第一開口180中露出第二開口192。換言之，第一開口180包含一寬度大於第二開口192之一寬度。
As shown in the top views of FIG. 1 and FIG. 6, and the cross-sectional views of FIG. 2 to FIG. 5, FIG. 7, and FIG. 8, the light-emitting element 1 includes a semiconductor platform 100t with a semiconductor stack 100; A first reflective structure 18 comprising metal material is located on the semiconductor platform 100t; and a second reflective structure 19 comprising insulating material is located on the first reflective structure 18 . As shown in Figure 5 and Figure 7, the first reflective structure 18 includes a first opening 180, the second reflective structure 19 includes a second opening 192, its position is relative to the position of the first opening 180, the second reflective The structure 19 covers the first reflective structure 18 at the first opening 180 , and the second opening 192 is exposed in the first opening 180 . In other words, the first opening 180 has a width greater than that of the second opening 192 .
如第1圖之上視圖所示，發光元件1可以具有矩形或正方形的外形，並如第2圖~第5圖之側視圖所示，發光元件1包含一基板10具有複數個側面10s位於發光元件1之一周圍以構成矩形或正方形的外形。由上視圖觀之，發光元件1的尺寸例如可以是1000μm×1000μm或700μm×700μm的正方形形狀或類似大小的矩形形狀，但不特別限定於此。
As shown in the top view of FIG. 1, the light-emitting element 1 can have a rectangular or square shape, and as shown in the side views of FIGS. One of the elements 1 is surrounded to form a rectangular or square shape. Viewed from the top view, the size of the light emitting element 1 may be, for example, a square shape of 1000 μm×1000 μm or 700 μm×700 μm or a rectangular shape of similar size, but is not particularly limited thereto.
如第2圖~第5圖所示，半導體疊層100包含一第一半導體層11，一第二半導體層12，以及一活性層13位於第一半導體層11及第二半導體層12之間。藉由改變半導體疊層100中一層或多層的物理及化學組成以調整發光元件1發出光線的波長。半導體疊層100之材料包含Ⅲ-V族半導體材料，例如AlxInyGa(1-x-y)N或AlxInyGa(1-x-y)P，其中0≦x，y≦1；(x+y)≦1。當半導體疊層100之材料為AlInGaP系列材料時，可發出波長介於610nm及650nm之間的紅光，或波長介於530nm及570nm之間的綠光。當半導體疊層100之材料為InGaN系列材料時，可發出波長介於400nm及490nm之間的藍光。當半導體疊層100之材料為AlGaN系列或AlInGaN系列材料時，可發出波長介於400nm及250nm之間的紫外光。
As shown in FIGS. 2-5 , the semiconductor stack 100 includes a first semiconductor layer 11 , a second semiconductor layer 12 , and an active layer 13 located between the first semiconductor layer 11 and the second semiconductor layer 12 . The wavelength of the light emitted by the light emitting element 1 is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack 100 . The material of the semiconductor stack 100 includes III-V group semiconductor materials, such as Al x In y Ga (1-xy) N or Al x In y Ga (1-xy) P, where 0≦x, y≦1; (x +y)≦1. When the material of the semiconductor stack 100 is an AlInGaP series material, it can emit red light with a wavelength between 610 nm and 650 nm, or green light with a wavelength between 530 nm and 570 nm. When the material of the semiconductor stack 100 is an InGaN series material, it can emit blue light with a wavelength between 400 nm and 490 nm. When the material of the semiconductor stack 100 is AlGaN series or AlInGaN series materials, it can emit ultraviolet light with a wavelength between 400 nm and 250 nm.
第一半導體層11和第二半導體層12可為包覆層(cladding layer)，兩者具有不同的導電型態、電性、極性，或依摻雜的元素以提供電子或電洞，例如第一半導體層11為n型電性的半導體，第二半導體層12為p型電性的半導體。活性層13形成在第一半導體層11和第二半導體層12之間，電子與電洞於一電流驅動下在活性層13複合，將電能轉換成光能，以發出一光線。活性層13可為單異質結構(single heterostructure,SH)，雙異質結構(double heterostructure,DH)，雙側雙異質結構(double-side double heterostructure,DDH)，或是多層量子井結構(multi-quantum well,MQW)。活性層13之材料可為中性、p型或n型電性的半導體。第一半導體層11、第二半導體層12、或活性層13可為單層或包含多個子層的結構。
The first semiconductor layer 11 and the second semiconductor layer 12 can be a cladding layer (cladding layer), both of which have different conductivity types, electric properties, polarities, or provide electrons or holes according to doped elements, such as the first The first semiconductor layer 11 is an n-type semiconductor, and the second semiconductor layer 12 is a p-type semiconductor. The active layer 13 is formed between the first semiconductor layer 11 and the second semiconductor layer 12 , electrons and holes recombine in the active layer 13 driven by a current, and convert electrical energy into light energy to emit a light. The active layer 13 can be single heterostructure (single heterostructure, SH), double heterostructure (double heterostructure, DH), double-side double heterostructure (double-side double heterostructure, DDH), or multi-layer quantum well structure (multi-quantum well, MQW). The material of the active layer 13 can be neutral, p-type or n-type semiconductor. The first semiconductor layer 11, the second semiconductor layer 12, or the active layer 13 may be a single layer or a structure including multiple sublayers.
如第2圖~第5圖、第7圖、第8圖之剖面圖所示，發光元件1包含一或複數個半導體平台100t，其中一或複數個半導體平台100t係由半導體疊層100所構成。於發明之一實施例中，各個半導體平台100t係藉由移除部分的第二半導體層12及活性層13，以形成包含第一半導體層11、第二半導體層12及活性層13的結
構。複數個半導體平台100t可以彼此分離以露出基板10或藉由第一半導體層11以彼此相連接。各個半導體平台100t包含一上表面及一下表面，活性層13包含一第一上表面及一第二下表面，其中半導體平台100t之上表面和活性層13之第一上表面之間包含一第一距離，半導體平台100t之下表面和活性層13之第二下表面之間包含一第二距離，且第二距離大於第一距離。
As shown in the sectional views of FIGS. 2 to 5, 7, and 8, the light-emitting element 1 includes one or a plurality of semiconductor platforms 100t, wherein one or a plurality of semiconductor platforms 100t is composed of semiconductor stacks 100 . In one embodiment of the invention, each semiconductor platform 100t is formed by removing part of the second semiconductor layer 12 and the active layer 13 to form a junction comprising the first semiconductor layer 11, the second semiconductor layer 12 and the active layer 13.
structure. The plurality of semiconductor platforms 100 t can be separated from each other to expose the substrate 10 or connected to each other through the first semiconductor layer 11 . Each semiconductor platform 100t includes an upper surface and a lower surface, and the active layer 13 includes a first upper surface and a second lower surface, wherein a first upper surface of the semiconductor platform 100t and the first upper surface of the active layer 13 include a first upper surface. The distance between the lower surface of the semiconductor platform 100t and the second lower surface of the active layer 13 includes a second distance, and the second distance is greater than the first distance.
第8圖係本發明一實施例中所揭示之第1圖的X區域之剖面圖。如第1圖及第8圖所示，發光元件1包含一環繞部100e以環繞一或複數個半導體平台100t之周圍，環繞部100e係位於一或複數個半導體平台100t之最外側。環繞部100e係藉由移除發光元件1周圍的第二半導體層12及活性層13而形成。環繞部100e的上視形狀包含矩形或多邊形環狀，其中矩形或多邊形之各角落可以圓弧化以避免電流局部集中於半導體平台100t之角落。
Fig. 8 is a cross-sectional view of area X in Fig. 1 disclosed in an embodiment of the present invention. As shown in FIG. 1 and FIG. 8, the light emitting device 1 includes a surrounding portion 100e to surround one or a plurality of semiconductor platforms 100t, and the surrounding portion 100e is located on the outermost side of one or a plurality of semiconductor platforms 100t. The surrounding portion 100e is formed by removing the second semiconductor layer 12 and the active layer 13 around the light emitting element 1 . The top-view shape of the surrounding portion 100e includes a rectangle or a polygon ring, wherein each corner of the rectangle or polygon can be rounded to prevent the current from locally concentrating on the corner of the semiconductor platform 100t.
於發明之一例中，如第8圖所示，環繞部100e包含一第一環繞部1001e。第一環繞部1001e係藉由移除半導體平台100t周圍的第二半導體層12及活性層13而形成，且包含第一半導體層11之一部分。換言之，第一環繞部1001e裸露出第一半導體層11之表面，且第一環繞部1001e不包含第二半導體層12及活性層13。於發明之另一例中，如第8圖所示，環繞部100e更包含一第二環繞部1002e位於第一環繞部1001e之周圍。相較於第一環繞部1001e，第二環繞部1002e更靠近基板10的側面10s。
In an example of the invention, as shown in FIG. 8, the surrounding portion 100e includes a first surrounding portion 1001e. The first surrounding portion 1001 e is formed by removing the second semiconductor layer 12 and the active layer 13 around the semiconductor platform 100 t and includes a part of the first semiconductor layer 11 . In other words, the first surrounding portion 1001 e exposes the surface of the first semiconductor layer 11 , and the first surrounding portion 1001 e does not include the second semiconductor layer 12 and the active layer 13 . In another example of the invention, as shown in FIG. 8, the surrounding portion 100e further includes a second surrounding portion 1002e located around the first surrounding portion 1001e. Compared with the first surrounding portion 1001e, the second surrounding portion 1002e is closer to the side surface 10s of the substrate 10 .
如第8圖所示，第二環繞部1002e位於半導體平台100t之周圍，第二環繞部1002e包含與半導體平台100t相同之結構。具體而言，第二環繞部1002e包含第一半導體層11、第二半導體層12及活性層13，第一環繞部1001e位於第二環
繞部1002e及半導體平台100t之間。半導體平台100t藉第一環繞部1001e以與第二環繞部1002e相隔一距離，其中第一環繞部1001e裸露出第一半導體層11之表面。
As shown in FIG. 8, the second surrounding portion 1002e is located around the semiconductor platform 100t, and the second surrounding portion 1002e includes the same structure as the semiconductor platform 100t. Specifically, the second surrounding portion 1002e includes the first semiconductor layer 11, the second semiconductor layer 12 and the active layer 13, and the first surrounding portion 1001e is located in the second ring
between the winding portion 1002e and the semiconductor platform 100t. The semiconductor platform 100t is separated from the second surrounding portion 1002e by a distance from the first surrounding portion 1001e, wherein the first surrounding portion 1001e exposes the surface of the first semiconductor layer 11 .
於發明之另一例中(圖未示)，環繞部100e包含複數個第一環繞部1001e及複數個第二環繞部1002e彼此交替排列以增加第二反射結構19與半導體疊層100之間的附著力，避免第二反射結構19自半導體疊層100的表面剝離。當環繞部100e包含複數個第一環繞部1001e及複數個第二環繞部1002e時，第一環繞部1001e可位於發光元件1之最外圍或是第二環繞部1002e位於發光元件1之最外圍。當第一環繞部1001e位於發光元件1之最外圍時，第一環繞部1001e包含具有一第一外側壁之第一半導體層11，所述第一外側壁與基板10之側面10s切齊或齊平，或是第一外側壁位於基板10之側面10s之內側，第一外側壁與基板10之側面10s相隔一距離以露出基板10之上表面。當第二環繞部1002e位於發光元件1之最外圍時，第二環繞部1002e包含具有一第二外側壁之半導體疊層100，所述第二外側壁與基板10之側面10s切齊或齊平，或是第二外側壁位於基板10之側面10s之內側，第二外側壁與基板10之側面10s相隔一距離以露出基板10之上表面。
In another example of the invention (not shown), the surrounding portion 100e includes a plurality of first surrounding portions 1001e and a plurality of second surrounding portions 1002e arranged alternately to increase the adhesion between the second reflective structure 19 and the semiconductor stack 100 force to prevent the second reflective structure 19 from peeling off from the surface of the semiconductor stack 100 . When the surrounding part 100e includes a plurality of first surrounding parts 1001e and a plurality of second surrounding parts 1002e, the first surrounding part 1001e can be located at the outermost periphery of the light emitting element 1 or the second surrounding part 1002e can be located at the outermost periphery of the light emitting element 1 . When the first surrounding portion 1001e is located at the outermost periphery of the light-emitting element 1, the first surrounding portion 1001e includes the first semiconductor layer 11 having a first outer wall, and the first outer wall is aligned or flush with the side surface 10s of the substrate 10 flat, or the first outer wall is located inside the side surface 10s of the substrate 10 , and the first outer wall and the side surface 10s of the substrate 10 are separated by a distance to expose the upper surface of the substrate 10 . When the second surrounding portion 1002e is located at the outermost periphery of the light-emitting element 1 , the second surrounding portion 1002e includes the semiconductor stack 100 having a second outer wall, the second outer wall is flush with or flush with the side surface 10s of the substrate 10 , or the second outer wall is located inside the side surface 10s of the substrate 10 , and the second outer wall is spaced from the side surface 10s of the substrate 10 by a distance to expose the upper surface of the substrate 10 .
發光元件1可包含一或複數個通孔100v為第二半導體層12及/或活性層13所環繞。通孔100v係藉由移除第二半導體層12及活性層13，以露出第一半導體層11之表面。通孔100v位於於半導體平台100t中，且為第二半導體層12及活性層13所環繞。通孔100v的上視形狀包含圓形、橢圓形、矩形、多邊形、或是任意形狀。複數個通孔100v可排列成複數列，任相鄰兩列或每相鄰兩列上的通孔100v可彼此對齊或是錯開。通孔100v的數目並不特別限定。如第1圖之上視圖所示，複數個通孔100v可以按照固定間隔呈固定圖案的方式配置，使電流可沿水平方向均勻地分散。
The light emitting device 1 may include one or a plurality of through holes 100 v surrounded by the second semiconductor layer 12 and/or the active layer 13 . The via hole 100v exposes the surface of the first semiconductor layer 11 by removing the second semiconductor layer 12 and the active layer 13 . The via hole 100v is located in the semiconductor platform 100t and is surrounded by the second semiconductor layer 12 and the active layer 13 . The top view shape of the through hole 100v includes a circle, an ellipse, a rectangle, a polygon, or any shape. A plurality of through holes 100v can be arranged in a plurality of rows, and the through holes 100v in any two adjacent rows or every two adjacent rows can be aligned with each other or staggered. The number of through holes 100v is not particularly limited. As shown in the upper view of FIG. 1 , a plurality of through holes 100v can be arranged in a fixed pattern at fixed intervals, so that the current can be uniformly dispersed in the horizontal direction.
於半導體疊層100的一側可以配置一基板10。基板10可以為一成長基板，包括用以磊晶成長磷化鋁鎵銦(AlGaInP)之砷化鎵(GaAs)晶圓，或用以成長氮化銦鎵(InGaN)之藍寶石(Al2O3)晶圓、氮化鎵(GaN)晶圓或碳化矽(SiC)晶圓。於另一實施例中，基板10可以為一支撐基板，原先用以磊晶成長半導體疊層100的成長基板可以依據應用的需要而選擇性地移除，再將半導體疊層100移轉至於前述之支撐基板。
A substrate 10 may be disposed on one side of the semiconductor stack 100 . The substrate 10 may be a growth substrate, including a gallium arsenide (GaAs) wafer for epitaxial growth of aluminum gallium indium phosphide (AlGaInP), or a sapphire (Al 2 O 3 ) wafer for growth of indium gallium nitride (InGaN). ) wafer, gallium nitride (GaN) wafer or silicon carbide (SiC) wafer. In another embodiment, the substrate 10 can be a supporting substrate, and the growth substrate originally used to epitaxially grow the semiconductor stack 100 can be selectively removed according to the needs of the application, and then the semiconductor stack 100 can be transferred to the aforementioned the supporting substrate.
於一實施例中，當半導體疊層100自成長基板被移轉至支撐基板時，各個半導體平台100t包含一上表面及一下表面，活性層13包含一第一上表面及一第二下表面，其中半導體平台100t之上表面及活性層13之第一上表面係分別較半導體平台100t之下表面及活性層13之第二下表面遠離於支撐基板，半導體平台100t之上表面和活性層13之第一上表面之間包含一第一距離，半導體平台100t之下表面和活性層13之第二下表面之間包含一第二距離，且第一距離大於第二距離。
In one embodiment, when the semiconductor stack 100 is transferred from the growth substrate to the support substrate, each semiconductor platform 100t includes an upper surface and a lower surface, and the active layer 13 includes a first upper surface and a second lower surface, Wherein the upper surface of the semiconductor platform 100t and the first upper surface of the active layer 13 are respectively farther away from the supporting substrate than the lower surface of the semiconductor platform 100t and the second lower surface of the active layer 13, the upper surface of the semiconductor platform 100t and the active layer 13 A first distance is included between the first upper surfaces, a second distance is included between the lower surface of the semiconductor platform 100t and the second lower surface of the active layer 13 , and the first distance is greater than the second distance.
支撐基板包括導電材料，例如矽(Si)、鋁(Al)、銅(Cu)、鎢(W)、鉬(Mo)、金(Au)、銀(Ag)，碳化矽(SiC)或上述材料之合金，或導熱材料，例如金剛石(diamond)、石墨(graphite)、或氮化鋁。並且，雖然圖未顯示，但是基板10與半導體疊層100相接的一面可以具有增加粗糙化的表面，粗糙化的表面可以為具有不規則形態的表面或具有規則形態的表面，例如具有多個半球形狀的面，具有多個圓錐形狀的面，或者具有多個多邊錐形狀的面。
The support substrate comprises a conductive material such as silicon (Si), aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), silicon carbide (SiC) or the above Alloys, or thermally conductive materials, such as diamond, graphite, or aluminum nitride. Moreover, although not shown in the figure, the side of the substrate 10 in contact with the semiconductor stack 100 may have an increased roughened surface, and the roughened surface may be a surface with an irregular shape or a surface with a regular shape, such as a surface with multiple A hemispherical surface, a plurality of conical surfaces, or a plurality of polygonal pyramidal surfaces.
於本發明之一實施例中，藉由有機金屬化學氣相沉積法(MOCVD)、分子束磊晶(MBE)、氫化物氣相沉積法(HVPE)、物理氣相沉積法(PVD)或離子電鍍方法以於基板10上形成具有光電特性之半導體疊層
100，例如發光(light-emitting)疊層，其中物理氣象沉積法包含濺鍍(Sputtering)或蒸鍍(Evoaporation)法。
In one embodiment of the present invention, by metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD) or ion Electroplating method to form a semiconductor laminate with optoelectronic properties on a substrate 10
100, such as a light-emitting (light-emitting) stack, wherein the physical vapor deposition method includes sputtering (Sputtering) or evaporation (Evoaporation) method.
於本發明之一實施例中，半導體疊層100還可包含一緩衝層(圖未示)位於第一半導體層11和基板10之間，用以釋放基板10和半導體疊層100之間因材料晶格不匹配而產生的應力，以減少差排及晶格缺陷，進而提升磊晶品質。緩衝層可為一單層或包含多個子層的結構。於一實施例中，可選用PVD氮化鋁(AlN)做為緩衝層，形成於半導體疊層100及基板10之間，用以改善半導體疊層100的磊晶品質。在一實施例中，用以形成PVD氮化鋁(AlN)的靶材係由氮化鋁所組成。在另一實施例中，係使用由鋁組成的靶材，於氮源的環境下與鋁靶材反應性地形成氮化鋁。
In one embodiment of the present invention, the semiconductor stack 100 may further include a buffer layer (not shown) located between the first semiconductor layer 11 and the substrate 10 to release the material between the substrate 10 and the semiconductor stack 100 The stress generated by lattice mismatch can reduce misalignment and lattice defects, thereby improving epitaxy quality. The buffer layer can be a single layer or a structure comprising multiple sublayers. In one embodiment, PVD aluminum nitride (AlN) may be used as a buffer layer formed between the semiconductor stack 100 and the substrate 10 to improve the epitaxial quality of the semiconductor stack 100 . In one embodiment, a target for forming PVD aluminum nitride (AlN) is composed of aluminum nitride. In another embodiment, a target composed of aluminum is used to form aluminum nitride reactively with the aluminum target in the presence of a nitrogen source.
參考第2圖~第5圖所示，於發明之一例中，發光元件1更包含一切割道10d位於半導體平台100t之周圍，於發明之一例中(圖未示)，環繞部100e位於切割道10d及半導體平台100t之間，切割道10d環繞環繞部100e之周圍。相較於環繞部100e，切割道10d係位於發光元件1之最外側。切割道10d係藉由移除第一半導體層11、第二半導體層12及活性層13，以露出基板10之表面。切割道10d的上視形狀包含矩形或多邊形環狀。於一實施例中，所述切割道10d露出基板10之表面係為一粗糙面。粗糙面可以為具有不規則形態的表面或具有規則形態的表面，例如具有多個半球形狀的面，具有多個圓錐形狀的面，或者具有多個多邊錐形狀的面。
Referring to Figures 2 to 5, in an example of the invention, the light-emitting element 1 further includes a dicing line 10d located around the semiconductor platform 100t, and in an example of the invention (not shown), the surrounding portion 100e is located in the dicing line Between 10d and the semiconductor platform 100t, the dicing line 10d surrounds the surrounding portion 100e. Compared with the surrounding portion 100e, the cutting line 10d is located at the outermost side of the light emitting element 1 . The dicing line 10d exposes the surface of the substrate 10 by removing the first semiconductor layer 11 , the second semiconductor layer 12 and the active layer 13 . The top view shape of the cutting line 10d includes a rectangle or a polygon ring. In one embodiment, the surface of the dicing line 10d exposed to the substrate 10 is a rough surface. The rough surface may be a surface with an irregular shape or a surface with a regular shape, such as a surface with multiple hemispherical shapes, a surface with multiple conical shapes, or a surface with multiple polygonal cone shapes.
半導體平台100t包含複數個外側壁S1及複數個內側壁S2，其中外側壁S1為第一半導體層11、第二半導體層12及活性層13之一側壁，外側壁S1之一端與第二半導體層12之一表面12S相連，外側壁S1之另一端與基板10之上表面相連。內側壁S2之一端與第二半導體層12之表面12S相連，內側壁
S2之另一端與第一半導體層11之一表面11s相連。複數個內側壁S2構成通孔100v之一側壁。如第2圖所示，內側壁S2與第一半導體層11的表面11s之間具有一銳角、一鈍角或一直角，外側壁S1與基板10的上表面之間具有一銳角、一鈍角或一直角。
The semiconductor platform 100t includes a plurality of outer sidewalls S1 and a plurality of inner sidewalls S2, wherein the outer sidewall S1 is a sidewall of the first semiconductor layer 11, the second semiconductor layer 12 and the active layer 13, and one end of the outer sidewall S1 is connected to the second semiconductor layer. One surface 12S of the substrate 12 is connected, and the other end of the outer side wall S1 is connected to the upper surface of the substrate 10 . One end of the inner sidewall S2 is connected to the surface 12S of the second semiconductor layer 12, and the inner sidewall
The other end of S2 is connected to a surface 11s of the first semiconductor layer 11 . A plurality of inner sidewalls S2 constitute one sidewall of the through hole 100v. As shown in FIG. 2, there is an acute angle, an obtuse angle or a right angle between the inner sidewall S2 and the surface 11s of the first semiconductor layer 11, and an acute angle, an obtuse angle or a right angle between the outer sidewall S1 and the upper surface of the substrate 10. right angle.
發光元件1包含一或複數個電流阻擋層15位於第二半導體層12上。電流阻擋層15係為非導電材料所形成，包含氧化鋁(Al2O3)、氮化矽(SiNx)、氧化矽(SiOx)、氧化鈦(TiOx)，或氟化鎂(MgFx)。電流阻擋層15可以包括分布式布拉格反射器(DBR)，其中分布式布拉格反射器具有不同折射率的絕緣材料彼此堆叠。電流阻擋層15對於活性層13所發出的光線具有80%以上的透光率或80%以上的光反射率。如第6圖所示，電流阻擋層15包含一或複數個阻擋墊151及一或複數個阻擋延伸部152，其中阻擋墊151的上視形狀包含多邊形、圓形或橢圓形，阻擋延伸部152的上視形狀包含矩形或多邊形。於相同方向的剖面圖中，阻擋墊151包含一寬度大於阻擋延伸部152之一寬度。電流阻擋層15具有一傾斜的側表面以降低自第二半導體層12剝離的風險，並增加後續疊層的覆蓋性。
The light emitting device 1 includes one or more current blocking layers 15 on the second semiconductor layer 12 . The current blocking layer 15 is formed of non-conductive materials, including aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ). The current blocking layer 15 may include a distributed Bragg reflector (DBR) in which insulating materials having different refractive indices are stacked on each other. The current blocking layer 15 has a light transmittance of more than 80% or a light reflectance of more than 80% for the light emitted by the active layer 13 . As shown in Figure 6, the current blocking layer 15 includes one or a plurality of blocking pads 151 and one or a plurality of blocking extensions 152, wherein the top view shape of the blocking pads 151 includes polygonal, circular or oval, and the blocking extensions 152 The top view shape for contains rectangles or polygons. In the cross-sectional view in the same direction, the barrier pad 151 has a width greater than that of the barrier extension 152 . The current blocking layer 15 has an inclined side surface to reduce the risk of detachment from the second semiconductor layer 12 and increase the coverage of subsequent stacked layers.
發光元件1包含一透明導電層14位於第二半導體層12及電流阻擋層15上，且透明導電層14覆蓋電流阻擋層15之一側壁。覆蓋於電流阻擋層15之上的透明導電層14的表面輪廓為對應電流阻擋層15之輪廓，例如對應阻擋墊151之多邊形、圓形或橢圓形，對應阻擋延伸部152之矩形或多邊形輪廓；透明導電層14自剖面觀之呈階梯狀輪廓，而不是平坦的輪廓。透明導電層14之材料包含對於活性層13所發出的光線為透明的材料，例如氧化銦錫(ITO)、或氧化銦鋅(IZO)。由於透明導電層14形成於第二半導體層12之大致整個面，並與第二半導體層12形成低電阻接觸，例如歐姆接觸，因此電流可以藉由透明導電層14以均勻地擴散
通過第二半導體層12。於一實施例中，透明導電層14包含一最外側，其與半導體平台100t之外側壁S1相隔一距離小於20μm，較佳小於10μm，更佳小於5μm。
The light emitting device 1 includes a transparent conductive layer 14 located on the second semiconductor layer 12 and the current blocking layer 15 , and the transparent conductive layer 14 covers a sidewall of the current blocking layer 15 . The surface profile of the transparent conductive layer 14 covering the current blocking layer 15 corresponds to the profile of the current blocking layer 15, for example, the polygonal, circular or oval corresponding to the blocking pad 151, and the rectangular or polygonal profile corresponding to the blocking extension 152; The transparent conductive layer 14 has a stepped outline rather than a flat outline when viewed from a cross section. The material of the transparent conductive layer 14 includes materials transparent to the light emitted by the active layer 13 , such as indium tin oxide (ITO) or indium zinc oxide (IZO). Since the transparent conductive layer 14 is formed on substantially the entire surface of the second semiconductor layer 12 and forms a low-resistance contact with the second semiconductor layer 12, such as an ohmic contact, current can be uniformly diffused through the transparent conductive layer 14.
through the second semiconductor layer 12 . In one embodiment, the transparent conductive layer 14 includes an outermost side, which is separated from the outer sidewall S1 of the semiconductor platform 100 t by a distance of less than 20 μm, preferably less than 10 μm, more preferably less than 5 μm.
透明導電層14的厚度可在0.1nm至100nm的範圍內。若透明導電層14的厚度小於0.1nm，則由於厚度太薄而不能有效地與第二半導體層12形成歐姆接觸。並且，若透明導電層14的厚度大於100nm，則由於厚度太厚而部分吸收活性層13所發出光線，從而導致發光元件1的亮度減少的問題。
The thickness of the transparent conductive layer 14 may range from 0.1 nm to 100 nm. If the thickness of the transparent conductive layer 14 is less than 0.1 nm, the ohmic contact with the second semiconductor layer 12 cannot be effectively formed because the thickness is too thin. Moreover, if the thickness of the transparent conductive layer 14 is greater than 100 nm, the light emitted by the active layer 13 will be partially absorbed due to the thickness being too thick, thereby causing the problem that the brightness of the light emitting element 1 is reduced.
發光元件1包含一或複數個第一接觸電極16a位於第一半導體層11上以電連接至第一半導體層11，及一或複數個第二接觸電極16b位於第二半導體層12上以電連接至第二半導體層12。一或複數個第一接觸電極16a分別位於一或複數個通孔100v內與第一半導體層11相接觸，且自發光元件1之一上視圖觀之，複數個第一接觸電極16a係彼此分離。為讓電流均勻地擴散通過第二半導體層12，第二接觸電極16b的位置係重疊於電流阻擋層15的位置，於發明之一例中，第二接觸電極16b與電流阻擋層15具有相似的形狀；於發明之另一例中，第二接觸電極16b與電流阻擋層15具有不相似的形狀。電流阻擋層15包含一面積大於第二接觸電極16b之一面積。透明導電層14包含一部分位於電流阻擋層15及第二接觸電極16b之間；以及另一部分直接接觸第二半導體層12。當電流通過第二接觸電極16b時，因電流阻擋層15位於第二接觸電極16b下方，電流無法透過電流阻擋層15自第二接觸電極直接向下傳導至第二半導體層12，所以電流會被迫流到透明導電層14後，藉由透明導電層14在水平方向上進行電流擴散，並將電流傳導至第二半導體層12。第一接觸電極16a及第二接觸電極16b具有一傾斜的側表面以降低自透明導電層14或第一半導體層11剝離的風險，並增加後續疊層的覆蓋性。於一實施例中，第一接觸電極16a之傾斜的側表面與第一半導體層11之表面之間具有一夾角介於30度及75度之間。第二接
觸電極16b之傾斜的側表面與透明導電層14之表面之間具有一夾角介於30度及75度之間。
The light emitting element 1 includes one or a plurality of first contact electrodes 16a located on the first semiconductor layer 11 to be electrically connected to the first semiconductor layer 11, and one or a plurality of second contact electrodes 16b located on the second semiconductor layer 12 to be electrically connected to to the second semiconductor layer 12. One or a plurality of first contact electrodes 16a are respectively located in one or a plurality of through holes 100v in contact with the first semiconductor layer 11, and viewed from a top view of the light emitting element 1, the plurality of first contact electrodes 16a are separated from each other . In order to allow the current to spread evenly through the second semiconductor layer 12, the position of the second contact electrode 16b overlaps the position of the current blocking layer 15. In one example of the invention, the second contact electrode 16b and the current blocking layer 15 have similar shapes ; In another example of the invention, the second contact electrode 16b and the current blocking layer 15 have dissimilar shapes. The current blocking layer 15 includes an area larger than that of the second contact electrode 16b. The transparent conductive layer 14 includes a part located between the current blocking layer 15 and the second contact electrode 16 b ; and another part directly contacting the second semiconductor layer 12 . When the current passes through the second contact electrode 16b, because the current blocking layer 15 is located below the second contact electrode 16b, the current cannot pass through the current blocking layer 15 and conduct directly downward from the second contact electrode to the second semiconductor layer 12, so the current will be blocked. After being forced into the transparent conductive layer 14 , the current is diffused in the horizontal direction through the transparent conductive layer 14 , and the current is conducted to the second semiconductor layer 12 . The first contact electrode 16a and the second contact electrode 16b have an inclined side surface to reduce the risk of delamination from the transparent conductive layer 14 or the first semiconductor layer 11 and increase the coverage of subsequent stacked layers. In one embodiment, an included angle between the inclined side surface of the first contact electrode 16 a and the surface of the first semiconductor layer 11 is between 30 degrees and 75 degrees. second pick
There is an included angle between the inclined side surface of the contact electrode 16 b and the surface of the transparent conductive layer 14 between 30 degrees and 75 degrees.
如第6圖所示，第二接觸電極16b包含一或複數個第二接觸墊161b及一或複數個第二接觸延伸部162b，自發光元件1之一上視圖觀之，第二接觸墊161b的上視形狀與阻擋墊151的形狀實質上相同或不相同，及/或第二接觸延伸部162b的上視形狀與阻擋延伸部152實質上相同或不相同。於本實施例中，第二接觸墊161b與阻擋墊151的上視形狀相同，包含圓形或橢圓形，第二接觸延伸部162b的上視形狀與阻擋延伸部152的上視形狀實質上相同，包含矩形或多邊形。於一實施例中，第二接觸墊161b的上視形狀與阻擋墊151的形狀實質上不相同，第二接觸墊161b與的上視形狀包含圓形或橢圓形，阻擋墊151的上視形狀包含矩形或多邊形。於相同方向的剖面圖中，第二接觸墊161b包含一寬度大於第二接觸延伸部162b之一寬度。於一實施例中，阻擋墊151包含一寬度大於第二接觸墊161b之一寬度。於一實施例中阻擋延伸部152包含一寬度大於第二接觸延伸部162b一寬度。於一實施例中阻擋延伸部152包含一寬度小於第二接觸延伸部162b一寬度。於一實施例中，第二接觸延伸部162b的上視形狀與阻擋延伸部152的上視形狀實質上不相同，第二接觸延伸部162b的上視形狀包含矩型或多邊型，阻擋延伸部152的上視形狀為分段式不連續點狀。
As shown in Figure 6, the second contact electrode 16b includes one or a plurality of second contact pads 161b and one or a plurality of second contact extensions 162b, viewed from a top view of the light-emitting element 1, the second contact pads 161b The top view shape of the second contact extension 162 b is substantially the same as or different from the shape of the blocking pad 151 , and/or the top view shape of the second contact extension 162 b is substantially the same as or different from the blocking extension 152 . In this embodiment, the top view shape of the second contact pad 161b is the same as that of the blocking pad 151, including circular or elliptical, and the top view shape of the second contact extension 162b is substantially the same as the top view shape of the blocking extension portion 152. , containing rectangles or polygons. In one embodiment, the top view shape of the second contact pad 161b is substantially different from the shape of the barrier pad 151, the top view shape of the second contact pad 161b and the barrier pad 161b include a circle or an ellipse, and the top view shape of the barrier pad 151 Contains rectangles or polygons. In the cross-sectional view in the same direction, the second contact pad 161b has a width greater than that of the second contact extension 162b. In one embodiment, the barrier pad 151 has a width greater than that of the second contact pad 161b. In one embodiment, the blocking extension 152 includes a width greater than that of the second contact extension 162b. In one embodiment, the blocking extension 152 includes a width smaller than that of the second contact extension 162b. In one embodiment, the top view shape of the second contact extension portion 162b is substantially different from the top view shape of the blocking extension portion 152, the top view shape of the second contact extension portion 162b includes a rectangle or a polygon, and the block extension portion The top view shape of 152 is a segmented discontinuous dot shape.
自發光元件1之一上視圖觀之，第一接觸電極16a與通孔100v具有相同的形狀，第二接觸墊161b與阻擋墊151具有相同的形狀，且第二接觸延伸部162b與阻擋延伸部152具有相同的形狀。如第1圖所示，第一接觸電極16a之一外邊緣與通孔100v之一外邊緣形成為同心圓形狀。第二接觸墊161b之一外邊緣與阻擋墊151之一外邊緣形成為同心圓形狀。於一實施例中，第一接觸電極16a可形成
為具有半徑R1的圓形形狀，且通孔100v形成為具有半徑R0的圓形形狀，其中R0大於R1。第二接觸墊161b可形成為具有半徑R2的圓形形狀，且阻擋墊151形成為具有半徑r的圓形形狀，其中r大於R2。
From a top view of the light-emitting element 1, the first contact electrode 16a has the same shape as the through hole 100v, the second contact pad 161b has the same shape as the barrier pad 151, and the second contact extension 162b has the same shape as the barrier extension. 152 has the same shape. As shown in FIG. 1, an outer edge of the first contact electrode 16a and an outer edge of the through hole 100v are formed in a concentric circle shape. An outer edge of the second contact pad 161b and an outer edge of the barrier pad 151 are formed in a concentric circle shape. In one embodiment, the first contact electrode 16a can be formed
is a circular shape with a radius R1, and the via hole 100v is formed in a circular shape with a radius R0, where R0 is larger than R1. The second contact pad 161b may be formed in a circular shape with a radius R2, and the barrier pad 151 is formed in a circular shape with a radius r, where r is greater than R2.
第一接觸電極16a及第二接觸電極16b包含金屬材料，例如鉻(Cr)、鈦(Ti)、鎢(W)、金(Au)、鋁(Al)、銦(In)、錫(Sn)、鎳(Ni)或鉑(Pt)等金屬或上述材料之合金。第一接觸電極16a及第二接觸電極16b可由單個層或是多個層所組成。例如，第一接觸電極16a或第二接觸電極16b可包括Ti/Au層、Ti/Pt/Au層、Cr/Au層、Cr/Pt/Au層、Ni/Au層、Ni/Pt/Au層或Cr/Al/Cr/Ni/Au層。
The first contact electrode 16a and the second contact electrode 16b include metal materials such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn) , nickel (Ni) or platinum (Pt) and other metals or alloys of the above materials. The first contact electrode 16a and the second contact electrode 16b can be composed of a single layer or a plurality of layers. For example, the first contact electrode 16a or the second contact electrode 16b may include Ti/Au layer, Ti/Pt/Au layer, Cr/Au layer, Cr/Pt/Au layer, Ni/Au layer, Ni/Pt/Au layer Or Cr/Al/Cr/Ni/Au layer.
第一接觸電極16a或第二接觸電極16b的厚度優選為0.5μm至2.5μm。於一實施例中，第一接觸電極16a之一上表面係低於第二半導體層12之表面12S，換言之，第一接觸電極16a之厚度係小於通孔100v之深度。於另一實施例中，第一接觸電極16a之一上表面係凸出於第二半導體層12之表面12S，換言之，第一接觸電極16a之厚度係大於通孔100v之深度。若第一接觸電極16a或第二接觸電極16b的厚度小於0.5μm，則無法有效地傳導電流。並且，若第一接觸電極16a或第二接觸電極16b的厚度大於2.5μm，則因過多的生產製造時間而導致製造上的損失。
The thickness of the first contact electrode 16 a or the second contact electrode 16 b is preferably 0.5 μm to 2.5 μm. In one embodiment, an upper surface of the first contact electrode 16 a is lower than the surface 12S of the second semiconductor layer 12 , in other words, the thickness of the first contact electrode 16 a is smaller than the depth of the through hole 100 v. In another embodiment, an upper surface of the first contact electrode 16a protrudes from the surface 12S of the second semiconductor layer 12 , in other words, the thickness of the first contact electrode 16a is greater than the depth of the through hole 100v. If the thickness of the first contact electrode 16 a or the second contact electrode 16 b is less than 0.5 μm, current cannot be efficiently conducted. Moreover, when the thickness of the 1st contact electrode 16a or the 2nd contact electrode 16b exceeds 2.5 micrometers, it will cause the loss in manufacture by excessive manufacturing time.
發光元件1包含一第一絕緣層17覆蓋於半導體平台100t、透明導電層14、第一接觸電極16a及第二接觸電極16b之上。第一絕緣層17包含一或複數個第一絕緣層第一開口171位於第一接觸電極16a上，並露出第一接觸電極16a之一表面。第一絕緣層17更包含一或複數個第一絕緣層第二開口172位於第二接觸墊161b上，並露出第二接觸墊161b之一表面，其中第二接觸延伸部162b為第一絕緣層17所覆蓋。
The light emitting device 1 includes a first insulating layer 17 covering the semiconductor platform 100t, the transparent conductive layer 14, the first contact electrode 16a and the second contact electrode 16b. The first insulating layer 17 includes one or a plurality of first openings 171 located on the first contact electrode 16a and exposing a surface of the first contact electrode 16a. The first insulating layer 17 further includes one or a plurality of first insulating layer second openings 172 located on the second contact pad 161b and exposing a surface of the second contact pad 161b, wherein the second contact extension 162b is the first insulating layer 17 covered.
第一絕緣層17係為非導電材料所形成，包含有機材料、無機材料或是介電材料。有機材料包含Su8、苯并環丁烯(BCB)、過氟環丁烷(PFCB)、環氧樹脂(Epoxy)、丙烯酸樹脂(Acrylic Resin)、環烯烴聚合物(COC)、聚甲基丙烯酸甲酯(PMMA)、聚對苯二甲酸乙二酯(PET)、聚碳酸酯(PC)、聚醚醯亞胺(Polyetherimide)或氟碳聚合物(Fluorocarbon Polymer)。無機材料包含矽膠(Silicone)或玻璃(Glass)。介電材料包含氧化鋁(Al2O3)、氮化矽(SiNx)、氧化矽(SiOx)、氧化鈦(TiOx)，或氟化鎂(MgFx)。
The first insulating layer 17 is formed of non-conductive materials, including organic materials, inorganic materials or dielectric materials. Organic materials include Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate Polyester (PMMA), Polyethylene Terephthalate (PET), Polycarbonate (PC), Polyetherimide (Polyetherimide) or Fluorocarbon Polymer (Fluorocarbon Polymer). Inorganic materials include silica gel (Silicone) or glass (Glass). The dielectric material includes aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ).
如第1圖及第5圖所示，一第一反射結構18包含一或複數個第一反射延伸部181位於第二接觸電極16b上及一第一反射環繞部182位於半導體平台100t之周圍以環繞一或複數個第一反射延伸部181，其中複數個第一反射延伸部181之位置係位於複數個第二接觸延伸部162b及/或阻擋延伸部152上，複數個第一反射延伸部181係彼此分離，且複數個第一反射延伸部181與複數個第二接觸延伸部162b及/或阻擋延伸部152具有相同或相似的形狀。一或複數個第一反射延伸部181之間包含一第一開口180以露出第二接觸墊161b之一表面。如第2圖及第3圖所示，第一反射延伸部181覆蓋第二接觸延伸部162b之一或多個表面，且第一絕緣層17介於第一反射延伸部181及第二接觸延伸部162b之間，避免第一反射延伸部181直接接觸第二接觸延伸部162b，使第一反射延伸部181與半導體平台100t電性絕緣。由於位在阻擋墊151及阻擋延伸部152下方之半導體疊層100非電流直接注入之區域，故第一反射延伸部181覆蓋阻擋墊151及/或阻擋延伸部152之一表面及/或一側壁，使此區域之側向光可以被第一反射延伸部181所反射，增加發光元件1之光摘出效率與均勻性。如第6圖所示，第一反射延伸部181包含一寬度大於第二接觸延伸部162b及/或阻擋延伸部152之一寬度。於一實施例中，第一反射延
伸部181包覆第二接觸延伸部162b之一側壁。第一反射結構18之材料包含高反射率的金屬材料，例如銀(Ag)、鋁(Al)、金(Au)、鈀(Pd)、或銠(Rh)等金屬或上述材料之合金。在此所述具有高反射率係指對於活性層13所發出光線的波長具有80%以上的反射率。
As shown in FIG. 1 and FIG. 5, a first reflective structure 18 includes one or a plurality of first reflective extensions 181 located on the second contact electrode 16b and a first reflective surrounding portion 182 located around the semiconductor platform 100t so that Surrounding one or a plurality of first reflective extensions 181, wherein the positions of the plurality of first reflective extensions 181 are located on the plurality of second contact extensions 162b and/or blocking extensions 152, and the plurality of first reflective extensions 181 They are separated from each other, and the plurality of first reflective extensions 181 have the same or similar shape as the plurality of second contact extensions 162b and/or the blocking extension 152 . A first opening 180 is included between one or a plurality of first reflective extensions 181 to expose a surface of the second contact pad 161b. As shown in FIG. 2 and FIG. 3, the first reflective extension 181 covers one or more surfaces of the second contact extension 162b, and the first insulating layer 17 is interposed between the first reflective extension 181 and the second contact extension. Between the portions 162b, the first reflective extension 181 is prevented from directly contacting the second contact extension 162b, so that the first reflective extension 181 is electrically insulated from the semiconductor platform 100t. Since the semiconductor stack 100 below the blocking pad 151 and the blocking extension 152 is not a region where current is directly injected, the first reflective extension 181 covers a surface and/or a side wall of the blocking pad 151 and/or the blocking extension 152 , so that the side light in this region can be reflected by the first reflective extension 181 , increasing the light extraction efficiency and uniformity of the light emitting element 1 . As shown in FIG. 6 , the first reflective extension 181 has a width greater than that of the second contact extension 162 b and/or the blocking extension 152 . In one embodiment, the first reflector extends
The extension portion 181 covers a sidewall of the second contact extension portion 162b. The material of the first reflective structure 18 includes metal materials with high reflectivity, such as silver (Ag), aluminum (Al), gold (Au), palladium (Pd), or rhodium (Rh), or alloys of the above materials. Herein, having a high reflectivity refers to having a reflectivity of more than 80% for the wavelength of the light emitted by the active layer 13 .
如第2圖~第5圖所示，於發明之一例中，第一反射環繞部182環繞並覆蓋半導體平台100t外圍之上表面及外側壁S1，且第一反射環繞部182與第一反射延伸部181相隔一距離，第一絕緣層17介於第一反射環繞部182及半導體平台100t之間，使第一反射環繞部182與半導體平台100t電性絕緣。如第8圖所示，於發明之一例中，發光元件1包含環繞部100e，其包含第一環繞部1001e以裸露出第一半導體層11之表面時，第一反射環繞部182覆蓋半導體平台100t之一上表面及一側壁，並藉由第一絕緣層17與第一半導體層11相隔。於一實施例中，位於半導體平台100t之上表面的第一反射環繞部182包含一第一邊，所述第一邊與半導體平台100t之側壁之間包含一距離w3小於10μm；於一實施例中，w3小於5μm；於另一實施例中，w3小於3μm。
As shown in Figures 2 to 5, in an example of the invention, the first reflective surrounding portion 182 surrounds and covers the upper surface and the outer sidewall S1 of the semiconductor platform 100t, and the first reflective surrounding portion 182 and the first reflective extension The portions 181 are separated by a distance, and the first insulating layer 17 is interposed between the first reflective surrounding portion 182 and the semiconductor platform 100t, so as to electrically insulate the first reflective surrounding portion 182 from the semiconductor platform 100t. As shown in FIG. 8, in one example of the invention, the light-emitting element 1 includes a surrounding portion 100e, which includes a first surrounding portion 1001e to expose the surface of the first semiconductor layer 11, and the first reflective surrounding portion 182 covers the semiconductor platform 100t. One upper surface and one side wall are separated from the first semiconductor layer 11 by the first insulating layer 17 . In one embodiment, the first reflective surrounding portion 182 located on the upper surface of the semiconductor platform 100t includes a first side, and the distance w3 between the first side and the sidewall of the semiconductor platform 100t is less than 10 μm; in one embodiment In one embodiment, w3 is less than 5 μm; in another embodiment, w3 is less than 3 μm.
於發明之一例中，如第8圖所示，環繞部100e包含第一環繞部1001e及第二環繞部1002e，其中第二環繞部1002e包含第一半導體層11、第二半導體層12及活性層13，第二環繞部1002e藉由第一環繞部1001e與半導體平台100t相隔一距離。第一反射環繞部182包含一第一部分覆蓋半導體平台100t之一上表面及一側壁，及第一環繞部1001e之一上表面；以及一第二部分覆蓋第二環繞部1002e之一上表面及一側壁。如第8圖所示，位於第一環繞部1001e內的第一反射環繞部182之第一部分及第二部分可彼此相連接，或是藉由第二反射結構19以相隔一距離(圖未示)。第一部分及/或第二部分可分別藉由第一絕緣層17與第一半導體層11相隔離。
In one example of the invention, as shown in FIG. 8, the surrounding portion 100e includes a first surrounding portion 1001e and a second surrounding portion 1002e, wherein the second surrounding portion 1002e includes a first semiconductor layer 11, a second semiconductor layer 12 and an active layer 13. The second surrounding portion 1002e is separated from the semiconductor platform 100t by a distance from the first surrounding portion 1001e. The first reflective surrounding portion 182 includes a first portion covering an upper surface and a side wall of the semiconductor platform 100t, and an upper surface of the first surrounding portion 1001e; and a second portion covering an upper surface of the second surrounding portion 1002e and a side wall. As shown in FIG. 8, the first portion and the second portion of the first reflective surrounding portion 182 located in the first surrounding portion 1001e can be connected to each other, or separated by a second reflective structure 19 (not shown in the figure). ). The first part and/or the second part can be separated from the first semiconductor layer 11 by the first insulating layer 17 respectively.
於一實施例中，第一反射結構18的厚度優選為100nm至1μm。若第一反射結構18的厚度小於100nm，則無法有效反射活性層13所發出的光線。並且，若第一反射結構18的厚度大於1μm，則因過多的生產製造時間而導致製造上的損失。
In one embodiment, the thickness of the first reflective structure 18 is preferably 100 nm to 1 μm. If the thickness of the first reflective structure 18 is less than 100 nm, the light emitted by the active layer 13 cannot be effectively reflected. Moreover, if the thickness of the first reflective structure 18 is greater than 1 μm, excessive manufacturing time will result in loss in manufacturing.
如第2圖、第3圖及第4圖所示，發光元件1包含一第二反射結構19覆蓋於第一絕緣層17及第一反射結構18之上。第二反射結構19包含一或複數個第二反射結構第一開口191位於第一接觸電極16a上，並露出第一接觸電極16a之表面。如第5圖所示，第二反射結構19更包含一或複數個第二反射結構第二開口192位於第二接觸墊161b上，並露出第二接觸墊161b之表面，其中第一反射結構18為第二反射結構19所完全覆蓋，藉此，第一反射結構18與半導體平台100t係電性絕緣。具體而言，第一反射結構18的第一反射延伸部181及或第一反射環繞部182被第一絕緣層17及第二反射結構19所完全包覆，避免第一反射延伸部181及第一反射環繞部182直接接觸第二接觸電極16b及第二延伸電極20b，因此第一反射結構18與半導體平台100t係電性絕緣。
As shown in FIG. 2 , FIG. 3 and FIG. 4 , the light emitting device 1 includes a second reflective structure 19 covering the first insulating layer 17 and the first reflective structure 18 . The second reflective structure 19 includes one or a plurality of second reflective structure first openings 191 located on the first contact electrode 16a and exposing the surface of the first contact electrode 16a. As shown in FIG. 5, the second reflective structure 19 further includes one or a plurality of second openings 192 located on the second contact pad 161b and exposing the surface of the second contact pad 161b, wherein the first reflective structure 18 It is completely covered by the second reflective structure 19, whereby the first reflective structure 18 is electrically insulated from the semiconductor platform 100t. Specifically, the first reflective extension portion 181 and/or the first reflective surrounding portion 182 of the first reflective structure 18 are completely covered by the first insulating layer 17 and the second reflective structure 19 to prevent the first reflective extension portion 181 and the second reflective A reflective surrounding portion 182 directly contacts the second contact electrode 16b and the second extension electrode 20b, so the first reflective structure 18 is electrically insulated from the semiconductor platform 100t.
第二反射結構第一開口191之位置對應於第一絕緣層第一開口171之位置，且彼此形成為同心圓形狀。第二反射結構第二開口192之位置對應於第一絕緣層第二開口172之位置，且彼此形成為同心圓形狀。於一實施例中，第一絕緣層第一開口171可形成為具有半徑R11的圓形形狀，且第二反射結構第一開口191形成為具有半徑R21的圓形形狀，其中R11大於R21。第一絕緣層第二開口172可形成為具有半徑R12的圓形形狀，且第二反射結構第二開口192形成為具有半徑R22的圓形形狀，其中R12大於R22。
The positions of the first openings 191 of the second reflective structure correspond to the positions of the first openings 171 of the first insulating layer, and are formed in concentric circles with each other. The positions of the second openings 192 of the second reflective structure correspond to the positions of the second openings 172 of the first insulating layer, and are formed in concentric circles with each other. In one embodiment, the first opening 171 of the first insulating layer may be formed in a circular shape with a radius R11, and the first opening 191 of the second reflective structure is formed in a circular shape with a radius R21, wherein R11 is greater than R21. The first insulating layer second opening 172 may be formed in a circular shape with a radius R12, and the second reflective structure second opening 192 is formed in a circular shape with a radius R22, wherein R12 is greater than R22.
第二反射結構19係為非導電材料所形成，包含有機材料、無機材料或介電材料。有機材料包含Su8、苯并環丁烯(BCB)、過氟環丁烷(PFCB)、環氧樹脂(Epoxy)、丙烯酸樹脂(Acrylic Resin)、環烯烴聚合物(COC)、聚甲基丙烯酸甲酯(PMMA)、聚對苯二甲酸乙二酯(PET)、聚碳酸酯(PC)、聚醚醯亞胺(Polyetherimide)或氟碳聚合物(Fluorocarbon Polymer)。無機材料包含矽膠(Silicone)或玻璃(Glass)。介電材料包含氧化鋁(Al2O3)、氮化矽(SiNx)、氧化矽(SiOx)、氧化鈦(TiOx)，或氟化鎂(MgFx)。
The second reflective structure 19 is formed of non-conductive materials, including organic materials, inorganic materials or dielectric materials. Organic materials include Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate Polyester (PMMA), Polyethylene Terephthalate (PET), Polycarbonate (PC), Polyetherimide (Polyetherimide) or Fluorocarbon Polymer (Fluorocarbon Polymer). Inorganic materials include silica gel (Silicone) or glass (Glass). The dielectric material includes aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ).
第二反射結構19可包含不同折射率的兩種以上之材料交替堆疊以形成一布拉格反射鏡(DBR)結構，選擇性地反射特定波長之光。例如，可通過層疊SiO2/TiO2或SiO2/Nb2O5等層來形成高反射率的絕緣反射層。
The second reflective structure 19 may include two or more materials with different refractive indices stacked alternately to form a Bragg reflector (DBR) structure, which selectively reflects light of a specific wavelength. For example, an insulating reflective layer with high reflectivity can be formed by laminating layers such as SiO 2 /TiO 2 or SiO 2 /Nb 2 O 5 .
當發光元件1所發射的光的波長為λ時，第二反射結構19的厚度可被設定為λ/4的整數倍。第二反射結構19的厚度在λ/4的整數倍的基礎上可具有±30%的偏差。
When the wavelength of the light emitted by the light emitting element 1 is λ, the thickness of the second reflective structure 19 can be set as an integer multiple of λ/4. The thickness of the second reflective structure 19 may have a deviation of ±30% on the basis of integer multiples of λ/4.
雖然金屬對於可見光具有良好的反射率，但是當金屬存在於電磁場之環境下，例如當外電流所注入發光元件1時，所述金屬傾向於擴散或者電子遷移。此外，這些金屬容易在潮濕的環境中氧化，隨著時間增長，反射率趨於減小，從而降低發光元件1的效率。為了避免上述問題，本發明之第一反射結構18係夾置於第一絕緣層17及包含絕緣材料之第二反射結構19之間，換言之，第一反射結構18之第一反射延伸部181及第一反射環繞部182係與半導體平台100t電絕緣。由於第二接觸墊161b係外部電流的直接注入區，因此第一反射結構18之第一反射延伸部181避免覆蓋於第二接觸墊161b之上表面，第一反射結構18第一反射延伸部181較佳位於第二接觸墊161b之側面，且第一反射延伸部181包含第一開口180以露出第二接觸墊161b之上表面。為了避免第一反射延伸部
181之金屬產生電子遷移，第二反射結構19包覆第一反射延伸部181之上表面及側表面，且第二反射結構19包含第二開口192以露出第二接觸墊161b之上表面，其中第一開口180包含一寬度大於第二開口192之寬度。
Although metal has good reflectivity for visible light, when the metal exists in the environment of electromagnetic field, for example, when the external current is injected into the light-emitting element 1 , the metal tends to diffuse or electron migrate. In addition, these metals are easily oxidized in a humid environment, and the reflectivity tends to decrease with time, thereby reducing the efficiency of the light emitting element 1 . In order to avoid the above problems, the first reflective structure 18 of the present invention is interposed between the first insulating layer 17 and the second reflective structure 19 comprising insulating material, in other words, the first reflective extension 181 and the first reflective extension 181 of the first reflective structure 18 The first reflective surround 182 is electrically insulated from the semiconductor platform 100t. Since the second contact pad 161b is a direct injection region of external current, the first reflective extension 181 of the first reflective structure 18 avoids covering the upper surface of the second contact pad 161b, and the first reflective extension 181 of the first reflective structure 18 It is preferably located on the side of the second contact pad 161b, and the first reflective extension 181 includes a first opening 180 to expose the upper surface of the second contact pad 161b. To avoid the first reflective extension
The metal of 181 produces electron migration, the second reflective structure 19 covers the upper surface and the side surface of the first reflective extension 181, and the second reflective structure 19 includes a second opening 192 to expose the upper surface of the second contact pad 161b, wherein The first opening 180 has a width greater than that of the second opening 192 .
發光元件1包含一或複數個第一延伸電極20a及一或複數個第二延伸電極20b。複數個第一延伸電極20a及複數個第二延伸電極20b係交替排列。第一延伸電極20a覆蓋於半導體平台100t及一或複數個第一接觸電極16a上，並與一或複數個第一接觸電極16a相接觸。第二延伸電極20b覆蓋於半導體平台100t及一或複數個第二接觸電極16b上，並與第二接觸墊161b相接觸，其中第二延伸電極20b不與第二接觸延伸部162b相接觸，第一絕緣層17及第二反射結構19係位於第二延伸電極20b及第二接觸延伸部162b之間。
The light emitting device 1 includes one or a plurality of first extension electrodes 20a and one or a plurality of second extension electrodes 20b. The plurality of first extension electrodes 20a and the plurality of second extension electrodes 20b are arranged alternately. The first extension electrode 20a covers the semiconductor platform 100t and one or more first contact electrodes 16a, and is in contact with one or more first contact electrodes 16a. The second extension electrode 20b covers the semiconductor platform 100t and one or a plurality of second contact electrodes 16b, and is in contact with the second contact pad 161b, wherein the second extension electrode 20b is not in contact with the second contact extension portion 162b. An insulating layer 17 and the second reflective structure 19 are located between the second extension electrode 20b and the second contact extension 162b.
第一延伸電極20a及第二延伸電極20b包含金屬材料，例如鉻(Cr)、鈦(Ti)、鎢(W)、金(Au)、鋁(Al)、銦(In)、錫(Sn)、鎳(Ni)、鉑(Pt)等金屬或上述材料之合金。第一延伸電極20a及第二延伸電極20b可由單個層或是多個層所組成。例如，第一延伸電極20a或第二延伸電極20b可包括Ti/Au層、Ti/Pt/Au層、Cr/Au層、Cr/Pt/Au層、Ni/Au層、Ni/Pt/Au層或Cr/Al/Cr/Ni/Au層。
The first extension electrode 20a and the second extension electrode 20b include metal materials such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn) , nickel (Ni), platinum (Pt) and other metals or alloys of the above materials. The first extension electrode 20a and the second extension electrode 20b can be composed of a single layer or a plurality of layers. For example, the first extension electrode 20a or the second extension electrode 20b may include Ti/Au layer, Ti/Pt/Au layer, Cr/Au layer, Cr/Pt/Au layer, Ni/Au layer, Ni/Pt/Au layer Or Cr/Al/Cr/Ni/Au layer.
於一實施例中，自發光元件1之上視圖觀之，發光元件1包含一頂針區200位於發光元件1之一幾何中心處。所述幾何中心處係指至少兩條對角線交叉且頂針區200所及之處。於一實施例中，頂針區200與第一延伸電極20a及/或第二延伸電極20b相隔一距離。於一實施例中，頂針區200可與第一延伸電極20a或第二延伸電極20b相連接。頂針區200包含與第一延伸電極20a或第二延伸電極20b相同之金屬材料或金屬疊層。
In one embodiment, viewed from the top view of the light emitting device 1 , the light emitting device 1 includes a pin region 200 located at a geometric center of the light emitting device 1 . The geometric center refers to a place where at least two diagonal lines intersect and where the thimble area 200 reaches. In one embodiment, the pin region 200 is separated from the first extension electrode 20a and/or the second extension electrode 20b by a distance. In one embodiment, the pin region 200 may be connected to the first extension electrode 20a or the second extension electrode 20b. The pin region 200 includes the same metal material or metal stack as the first extension electrode 20a or the second extension electrode 20b.
頂針區200係作為保護磊晶層之結構以避免磊晶層於後段製程，例如晶粒分離、測試晶粒、封裝，為外力所損害，例如探針、或頂針所損害。自發光元件1之上視圖觀之，頂針區200可包含與第一延伸電極20a或第二延伸電極20b不同之形狀。頂針區200之形狀包含矩形、橢圓形或是圓形。
The thimble area 200 is used as a structure to protect the epitaxial layer to prevent the epitaxial layer from being damaged by external forces, such as probes or thimbles, in subsequent processes, such as die separation, test die, and packaging. Viewed from the top view of the light emitting device 1 , the pin area 200 may have a shape different from that of the first extension electrode 20 a or the second extension electrode 20 b. The shape of the ejector pin area 200 includes rectangle, ellipse or circle.
發光元件1包含一第二絕緣層21覆蓋於半導體平台100t、第二反射結構19、第一延伸電極20a及第二延伸電極20b之上。第二絕緣層21包含一或複數個第二絕緣層第一開口211位於第一延伸電極20a上，並露出第一延伸電極20a之一表面。第二絕緣層21更包含一或複數個第二絕緣層第二開口212位於第二延伸電極20b上，並露出第二延伸電極20b之一表面。
The light emitting device 1 includes a second insulating layer 21 covering the semiconductor platform 100t, the second reflective structure 19, the first extension electrode 20a and the second extension electrode 20b. The second insulating layer 21 includes one or a plurality of second insulating layer first openings 211 located on the first extension electrode 20a and exposing a surface of the first extension electrode 20a. The second insulating layer 21 further includes one or a plurality of second openings 212 located on the second extension electrode 20b and exposing a surface of the second extension electrode 20b.
自發光元件1之一上視圖觀之，複數個第二絕緣層第一開口211皆位於發光元件1之一第一側，複數個第二絕緣層第二開口212皆位於發光元件1之一第二側，且第一側與第二側係位於發光元件1之相對側。
Viewed from a top view of the light-emitting element 1, the plurality of first openings 211 of the second insulating layer are all located on the first side of the light-emitting element 1, and the plurality of second openings 212 of the second insulating layer are all located on the first side of the light-emitting element 1. Two sides, and the first side and the second side are located on opposite sides of the light emitting element 1 .
自發光元件1之一上視圖觀之，一或複數個第二絕緣層第一開口211之形成位置係與第一接觸電極16a之形成位置相錯開，且一或複數個第二絕緣層第二開口212之形成位置係與第二接觸電極16b之形成位置相錯開。具體而言，第二絕緣層第一開口211位於兩相鄰之第一接觸電極16a之間，第二絕緣層第二開口212位於第二接觸電極16b之左右兩側或其中之一側。
Viewed from a top view of the light-emitting element 1, the formation positions of the first openings 211 of the one or plural second insulating layers are staggered from the formation positions of the first contact electrodes 16a, and the positions of the one or plural second insulating layers are second The forming position of the opening 212 is staggered from the forming position of the second contact electrode 16b. Specifically, the first opening 211 of the second insulating layer is located between two adjacent first contact electrodes 16a, and the second opening 212 of the second insulating layer is located at the left and right sides or one side of the second contact electrode 16b.
於一實施例中，自發光元件1之上視圖或側視圖觀之，第二絕緣層第一開口211包含一最大寬度大於或小於通孔100v、第一絕緣層第一開口171及第二反射結構第一開口191之其中之一的最大寬度。第二絕緣層第二開口212包含一最大寬度大於或小於第一絕緣層第二開口172及第二反射結構第二開口192之其中之一的最大寬度。
In one embodiment, viewed from the top view or side view of the light-emitting element 1, the first opening 211 of the second insulating layer includes a through hole 100v with a maximum width larger or smaller than the through hole 100v, the first opening 171 of the first insulating layer, and the second reflection The maximum width of one of the first openings 191 is structured. The second opening 212 of the second insulating layer includes a maximum width greater than or smaller than the maximum width of one of the second opening 172 of the first insulating layer and the second opening 192 of the second reflective structure.
於一實施例中，第二絕緣層第一開口211位於兩相鄰之通孔100v之間，及/或位於兩相鄰之第二接觸電極16b之間。
In one embodiment, the first opening 211 of the second insulating layer is located between two adjacent via holes 100v, and/or is located between two adjacent second contact electrodes 16b.
於一實施例中，複數個第二絕緣層第一開口211之數目與複數個第二絕緣層第二開口212之數目不同。於一實施例中，第二絕緣層第二開口212之數目多於第二絕緣層第一開口211之數目。於一實施例中，第二絕緣層第二開口212之數目少於第二絕緣層第一開口211之數目。
In one embodiment, the number of the plurality of first openings 211 of the second insulating layer is different from the number of the plurality of second openings 212 of the second insulating layer. In one embodiment, the number of the second openings 212 of the second insulating layer is greater than the number of the first openings 211 of the second insulating layer. In one embodiment, the number of the second openings 212 of the second insulating layer is less than the number of the first openings 211 of the second insulating layer.
第二絕緣層21係為非導電材料所形成，包含有機材料、無機材料或介電材料。有機材料包含Su8、苯并環丁烯(BCB)、過氟環丁烷(PFCB)、環氧樹脂(Epoxy)、丙烯酸樹脂(Acrylic Resin)、環烯烴聚合物(COC)、聚甲基丙烯酸甲酯(PMMA)、聚對苯二甲酸乙二酯(PET)、聚碳酸酯(PC)、聚醚醯亞胺(Polyetherimide)或氟碳聚合物(Fluorocarbon Polymer)。無機材料，包含矽膠(Silicone)或玻璃(Glass)。介電材料包含氧化鋁(Al2O3)、氮化矽(SiNx)、氧化矽(SiOx)、氧化鈦(TiOx)，或氟化鎂(MgFx)。
The second insulating layer 21 is formed of non-conductive materials, including organic materials, inorganic materials or dielectric materials. Organic materials include Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate Polyester (PMMA), Polyethylene Terephthalate (PET), Polycarbonate (PC), Polyetherimide (Polyetherimide) or Fluorocarbon Polymer (Fluorocarbon Polymer). Inorganic materials, including silicone or glass. The dielectric material includes aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ).
發光元件1包含一第一電極墊22a以覆蓋一或複數個第二絕緣層第一開口211，且接觸第一延伸電極20a。發光元件1包含一第二電極墊22b以覆蓋一或複數個第二絕緣層第二開口212，且接觸第二延伸電極20b。第一電極墊22a及第二電極墊22b藉由第一延伸電極20a及第二延伸電極20b分別電連接至第一接觸電極16a及第二接觸電極16b。
The light emitting device 1 includes a first electrode pad 22a covering one or a plurality of first openings 211 of the second insulating layer and contacting the first extension electrode 20a. The light emitting device 1 includes a second electrode pad 22b to cover one or a plurality of second openings 212 of the second insulating layer, and to contact the second extension electrode 20b. The first electrode pad 22a and the second electrode pad 22b are respectively electrically connected to the first contact electrode 16a and the second contact electrode 16b through the first extension electrode 20a and the second extension electrode 20b.
第一電極墊22a或第二電極墊22b之上表面可以為非平面。具體而言，第一電極墊22a或第二電極墊22b的上表面具有與第一接觸電極16a的上表面和第二接觸電極16b的上表面的表面輪廓相對應的表面輪廓。換言之，第一電極墊22a或第二電極墊22b設置在第一接觸電極16a和第二接觸電極16b上，
其中第一接觸電極16a和第二接觸電極16b具有非平坦表面輪廓，因此具有長條形、圓形或階梯形表面。如第1圖所示，第一電極墊22a或第二電極墊22b的上表面可包括至少一個凹陷部及至少一個凸出部，其分別設置於第一接觸電極16a和第二接觸電極16b所放置的區域中。因此，第一電極墊22a或第二電極墊22b的上表面可具有階梯形表面。凹陷部可形成為第1圖所示的圓形形狀，凸出部可形成為第1圖所示的長條形形狀。第一電極墊22a之凹陷部或第二電極墊22b凹陷部的外邊緣和第一接觸電極16a的邊緣可形成為同心圓形狀。
The upper surface of the first electrode pad 22a or the second electrode pad 22b may be non-planar. Specifically, the upper surface of the first electrode pad 22a or the second electrode pad 22b has a surface profile corresponding to the surface profile of the upper surface of the first contact electrode 16a and the upper surface of the second contact electrode 16b. In other words, the first electrode pad 22a or the second electrode pad 22b is disposed on the first contact electrode 16a and the second contact electrode 16b,
Wherein the first contact electrode 16a and the second contact electrode 16b have non-flat surface contours, and thus have elongated, circular or stepped surfaces. As shown in Figure 1, the upper surface of the first electrode pad 22a or the second electrode pad 22b may include at least one concave portion and at least one protruding portion, which are respectively arranged on the first contact electrode 16a and the second contact electrode 16b. placed in the area. Accordingly, the upper surface of the first electrode pad 22a or the second electrode pad 22b may have a stepped surface. The depressed portion may be formed in a circular shape as shown in FIG. 1, and the protruding portion may be formed in an elongated shape as shown in FIG. 1. The concave portion of the first electrode pad 22a or the outer edge of the concave portion of the second electrode pad 22b and the edge of the first contact electrode 16a may be formed in a concentric circle shape.
第一電極墊22a及第二電極墊22b包含金屬材料，例如鉻(Cr)、鈦(Ti)、鎢(W)、金(Au)、鋁(Al)、銦(In)、錫(Sn)、鎳(Ni)、鉑(Pt)等金屬或上述材料之合金。第一電極墊22a及第二電極墊22b可由單個層或是多個層所組成。例如，第一電極墊22a或第二電極墊22b可包括Ti/Au層、Ti/Pt/Au層、Cr/Au層、Cr/Pt/Au層、Ni/Au層、Ni/Pt/Au層或Cr/Al/Cr/Ni/Au層。第一電極墊22a及第二電極墊22b可做為外電源供電至第一半導體層11及第二半導體層12之電流路徑。
The first electrode pad 22a and the second electrode pad 22b include metal materials such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn) , nickel (Ni), platinum (Pt) and other metals or alloys of the above materials. The first electrode pad 22a and the second electrode pad 22b can be composed of a single layer or multiple layers. For example, the first electrode pad 22a or the second electrode pad 22b may include Ti/Au layer, Ti/Pt/Au layer, Cr/Au layer, Cr/Pt/Au layer, Ni/Au layer, Ni/Pt/Au layer Or Cr/Al/Cr/Ni/Au layer. The first electrode pad 22 a and the second electrode pad 22 b can be used as a current path for supplying power from an external power source to the first semiconductor layer 11 and the second semiconductor layer 12 .
於本發明之一實施例中，第一電極墊22a包含一尺寸與第二電極墊22b之一尺寸相同或不同，此尺寸可為寬度或面積。例如，第一電極墊22a或第二電極墊22b的上視面積可為第一電極墊22a及第二電極墊22b的上視面積相加所得的值的0.8倍以上且小於1倍的大小。
In an embodiment of the present invention, the first electrode pad 22a includes a dimension that is the same as or different from that of the second electrode pad 22b, and the dimension may be a width or an area. For example, the top view area of the first electrode pad 22a or the second electrode pad 22b may be 0.8 times or more and less than 1 time the value obtained by adding the top view areas of the first electrode pad 22a and the second electrode pad 22b.
第一電極墊22a或第二電極墊22b分別包含一傾斜側面，因此第一電極墊22a或第二電極墊22b的側視剖面面積可沿厚度方向發生變化。例如，第一電極墊22a或第二電極墊22b的側視剖面面積可隨著遠離半導體疊層100的上表面的方向逐漸變小。
The first electrode pad 22a or the second electrode pad 22b respectively includes an inclined side surface, so the side view cross-sectional area of the first electrode pad 22a or the second electrode pad 22b can change along the thickness direction. For example, the side view cross-sectional area of the first electrode pad 22 a or the second electrode pad 22 b may gradually become smaller in a direction away from the upper surface of the semiconductor stack 100 .
第一電極墊22a與第二電極墊22b之間包含一間隔，間隔包含一最短距離約為10μm以上，及一最長距離約為250μm以下。於上述
範圍內，藉由縮小第一電極墊22a與第二電極墊22b之間的間隔可以增大第一電極墊22a與第二電極墊22b的上視面積，從而可提高發光元件1的散熱效率，且避免第一電極墊22a與第二電極墊22b之間的短路。
There is a space between the first electrode pad 22a and the second electrode pad 22b, and the space includes a shortest distance of about 10 μm or more and a longest distance of about 250 μm or less. in the above
Within the range, by reducing the distance between the first electrode pad 22a and the second electrode pad 22b, the top view area of the first electrode pad 22a and the second electrode pad 22b can be increased, thereby improving the heat dissipation efficiency of the light emitting element 1, And avoid short circuit between the first electrode pad 22a and the second electrode pad 22b.
第一電極墊22a與第二電極墊22b包含一厚度介於1~100μm之間，較佳為1.5~6μm之間。
The first electrode pad 22a and the second electrode pad 22b include a thickness between 1-100 μm, preferably between 1.5-6 μm.
於本發明之一實施例中，第一延伸電極20a包含一第一接觸部分201a位於第一電極墊22a下方及一第一延伸部分202a位於第二電極墊22b下方，其中第一接觸部分201a包含一寬度大於第一延伸部分202a之一寬度。第二延伸電極20b包含一第二接觸部分201b位於第二電極墊22b下方及一第二延伸部分202b位於第一電極墊22a下方，其中第二接觸部分201b包含一寬度大於第二延伸部分202b之一寬度。
In one embodiment of the present invention, the first extended electrode 20a includes a first contact portion 201a located below the first electrode pad 22a and a first extended portion 202a located below the second electrode pad 22b, wherein the first contact portion 201a includes A width is greater than a width of the first extension portion 202a. The second extended electrode 20b includes a second contact portion 201b located below the second electrode pad 22b and a second extended portion 202b located below the first electrode pad 22a, wherein the second contact portion 201b includes a width larger than the second extended portion 202b a width.
於本發明之一實施例中，第一接觸電極16a包含一寬度至少8μm以上，較佳為15μm以上，更佳為20μm以上。第一延伸電極20a之第一接觸部分201a包含一寬度至少15μm以上，較佳為20μm以上，更佳為25μm以上。第一延伸電極20a之第一延伸部分202a包含一寬度至少1μm以上，較佳為2μm以上，更佳為4μm以上。
In an embodiment of the present invention, the first contact electrode 16 a has a width of at least 8 μm, preferably 15 μm, more preferably 20 μm. The first contact portion 201a of the first extension electrode 20a includes a width of at least 15 μm, preferably 20 μm, more preferably 25 μm. The first extension portion 202a of the first extension electrode 20a includes a width of at least 1 μm, preferably 2 μm, more preferably 4 μm.
於本發明之一實施例中，第二接觸電極16b包含一寬度至少1μm以上，較佳為2μm以上，更佳為4μm以上。第二延伸電極20b之第二接觸部分201b包含一寬度至少15μm以上，較佳為20μm以上，更佳為25μm以上。第二延伸電極20b之第二延伸部分202b包含一寬度至少1μm以上，較佳為2μm以上，更佳為4μm以上。
In an embodiment of the present invention, the second contact electrode 16b includes a width of at least 1 μm, preferably 2 μm, more preferably 4 μm. The second contact portion 201b of the second extension electrode 20b includes a width of at least 15 μm, preferably 20 μm, more preferably 25 μm. The second extension portion 202b of the second extension electrode 20b includes a width of at least 1 μm, preferably 2 μm, more preferably 4 μm.
第9圖係為依本發明一實施例之發光裝置2之示意圖。將前述實施例中的發光元件1以倒裝晶片之形式安裝於封裝基板51之第一墊片511、第二墊片512上。第一墊片511、第二墊片512之間藉由一包含絕緣材料之絕緣部53做電性絕緣。倒裝晶片安裝係將與電極墊形成面相對之成長基板側向上設為主要的光取出面。為了增加發光裝置2之光取出效率，可於發光元件1之周圍設置一反射結構54。
FIG. 9 is a schematic diagram of a light emitting device 2 according to an embodiment of the present invention. The light-emitting element 1 in the foregoing embodiments is mounted on the first pad 511 and the second pad 512 of the packaging substrate 51 in the form of a flip chip. The first spacer 511 and the second spacer 512 are electrically insulated by an insulating portion 53 including insulating material. In flip-chip mounting, the side of the growth substrate opposite to the surface where the electrode pads are formed is set upward as the main light extraction surface. In order to increase the light extraction efficiency of the light emitting device 2 , a reflective structure 54 can be provided around the light emitting element 1 .
第10圖係為依本發明一實施例之發光裝置3之示意圖。發光裝置3為一球泡燈包括一燈罩602、一反射鏡604、一發光模組610、一燈座612、一散熱片614、一連接部616以及一電連接元件618。發光模組610包含一承載部606，以及複數個發光單元608位於承載部606上，其中複數個發光單元608可為前述實施例中的發光元件1或發光裝置2。
Fig. 10 is a schematic diagram of a light emitting device 3 according to an embodiment of the present invention. The light emitting device 3 is a bulb lamp including a lampshade 602 , a reflector 604 , a light emitting module 610 , a lamp holder 612 , a heat sink 614 , a connection portion 616 and an electrical connection element 618 . The light emitting module 610 includes a carrying portion 606, and a plurality of light emitting units 608 are located on the carrying portion 606, wherein the plurality of light emitting units 608 can be the light emitting elements 1 or the light emitting devices 2 in the foregoing embodiments.
本發明所列舉之各實施例僅用以說明本發明，並非用以限制本發明之範圍。任何人對本發明所作之任何顯而易知之修飾或變更皆不脫離本發明之精神與範圍。
The various embodiments listed in the present invention are only used to illustrate the present invention, and are not intended to limit the scope of the present invention. Any obvious modifications or changes made by anyone to the present invention will not depart from the spirit and scope of the present invention.
