TWI789293B - Light-emitting device - Google Patents

Light-emitting device Download PDF

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TWI789293B
TWI789293B TW111115629A TW111115629A TWI789293B TW I789293 B TWI789293 B TW I789293B TW 111115629 A TW111115629 A TW 111115629A TW 111115629 A TW111115629 A TW 111115629A TW I789293 B TWI789293 B TW I789293B
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light
semiconductor layer
electrode pad
contact electrode
layer
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TW202232784A (en
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蔣宗勳
邱柏順
紀喨勝
趙欣
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晶元光電股份有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46Reflective coating, e.g. dielectric Bragg reflector

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Abstract

A light-emitting device includes a substrate including a sidewall; a light-emitting stack formed on the substrate, including a first semiconductor layer, an active layer and a second semiconductor layer; a semiconductor structure formed on the substrate, being separated from the light-emitting stack by the first semiconductor layer and surrounding the light-emitting stack; and a distributed bragg reflector covering the light-emitting stack and the semiconductor structure, wherein the semiconductor structure includes a side surface directly connected to the sidewall of the substrate, and a top surface directly connected to the side surface of the semiconductor structure, the top surface includes a top surface of the second semiconductor layer, the distributed bragg reflector comprises a first side surface directly connected to the side surface of the semiconductor structure and a second side surface separated from the side surface of the semiconductor structure by a distance to expose the top surface of the semiconductor structure.

Description

發光元件Light emitting element

本發明係關於一種發光元件,且特別係關於一種發光元件,其包含一發光疊層,一半導體結構環繞發光疊層及一反射結構位於發光疊層及半導體結構上。The present invention relates to a light-emitting element, and in particular to a light-emitting element, which includes a light-emitting stack, a semiconductor structure surrounding the light-emitting stack, and a reflective structure located on the light-emitting stack and the semiconductor structure.

發光二極體(Light-Emitting Diode, LED)為固態半導體發光元件,其優點為功耗低,產生的熱能低,工作壽命長,防震,體積小,反應速度快和具有良好的光電特性,例如穩定的發光波長。因此發光二極體被廣泛應用於家用電器,設備指示燈,及光電產品等。Light-Emitting Diode (Light-Emitting Diode, LED) is a solid-state semiconductor light-emitting element, which has the advantages of low power consumption, low heat generation, long working life, shockproof, small size, fast response and good photoelectric properties, such as Stable emission wavelength. Therefore, light-emitting diodes are widely used in household appliances, equipment indicator lights, and optoelectronic products.

一發光元件包含一基板包含一側壁;一發光疊層包含複數個外側壁位於基板上,發光疊層包含一第一半導體層、一活性層及一第二半導體層;一半導體結構位於基板上,藉由第一半導體層與發光疊層相隔一距離並環繞發光疊層之複數個外側壁;以及一布拉格反射鏡覆蓋發光疊層及半導體結構,其中,半導體結構包含一側表面與基板之側壁直接相接,以及一上表面與半導體結構之側表面直接相接,上表面包含第二半導體層之一表面,布拉格反射鏡包含一第一側面與半導體結構之側表面直接相連及一第二側面與半導體結構之側表面相隔一距離以露出半導體結構之上表面。A light emitting element includes a substrate including a side wall; a light emitting stack includes a plurality of outer side walls on the substrate, a light emitting stack includes a first semiconductor layer, an active layer and a second semiconductor layer; a semiconductor structure is located on the substrate, The first semiconductor layer is separated from the light-emitting stack by a distance and surrounds a plurality of outer walls of the light-emitting stack; and a Bragg reflector covers the light-emitting stack and the semiconductor structure, wherein the semiconductor structure includes one side surface directly connected to the side wall of the substrate connected, and an upper surface directly connected to the side surface of the semiconductor structure, the upper surface includes a surface of the second semiconductor layer, the Bragg reflector includes a first side directly connected to the side surface of the semiconductor structure and a second side connected to the side surface of the semiconductor structure. The side surfaces of the semiconductor structure are separated by a distance to expose the upper surface of the semiconductor structure.

一發光元件包含一基板包含一側壁;一發光疊層包含複數個外側壁位於基板上,發光疊層包含一第一半導體層、一活性層及一第二半導體層;一半導體結構位於基板上,藉由第一半導體層與發光疊層相隔一距離並環繞發光疊層之複數個外側壁;一第一溝槽位於基板上,露出第一半導體層,且位於發光疊層及半導體結構之間,藉由第一溝槽露出的第一半導體層將半導體結構與發光疊層分相隔一距離,並且半導體結構係環繞發光疊層;一第二溝槽位於第一半導體層上,藉由半導體結構與第一溝槽相隔一距離並環繞半導體結構之複數個側面;以及一布拉格反射鏡覆蓋發光疊層及半導體結構,其中,半導體結構包含一側表面與基板之側壁相隔一距離,以及一與半導體結構之側表面直接相接之上表面,上表面包含第二半導體層之一表面,布拉格反射鏡包含一第一側面與半導體結構之側表面直接連接或相隔一距離。A light emitting element includes a substrate including a side wall; a light emitting stack includes a plurality of outer side walls on the substrate, a light emitting stack includes a first semiconductor layer, an active layer and a second semiconductor layer; a semiconductor structure is located on the substrate, The first semiconductor layer is separated from the light-emitting stack by a distance and surrounds a plurality of outer sidewalls of the light-emitting stack; a first groove is located on the substrate, exposing the first semiconductor layer, and is located between the light-emitting stack and the semiconductor structure, The first semiconductor layer exposed by the first groove separates the semiconductor structure and the light-emitting stack at a distance, and the semiconductor structure surrounds the light-emitting stack; a second groove is located on the first semiconductor layer, and the semiconductor structure and the light-emitting stack are separated by a distance. The first trench is separated by a distance and surrounds a plurality of sides of the semiconductor structure; and a Bragg reflector covers the light-emitting stack and the semiconductor structure, wherein the semiconductor structure includes a side surface separated by a distance from the side wall of the substrate, and a semiconductor structure. The side surface of the Bragg mirror directly connects with the upper surface, and the upper surface includes a surface of the second semiconductor layer. The Bragg reflector includes a first side that is directly connected with the side surface of the semiconductor structure or separated by a distance.

為了使本發明之敘述更加詳盡與完備,請參照下列實施例之描述並配合相關圖示。惟,以下所示之實施例係用於例示本發明之發光元件,並非將本發明限定於以下之實施例。又,本說明書記載於實施例中的構成零件之尺寸、材質、形狀、相對配置等在沒有限定之記載下,本發明之範圍並非限定於此,而僅是單純之說明而已。且各圖示所示構件之大小或位置關係等,會由於為了明確說明有加以誇大之情形。更且,於以下之描述中,為了適切省略詳細說明,對於同一或同性質之構件用同一名稱、符號顯示。In order to make the description of the present invention more detailed and complete, please refer to the description of the following embodiments together with the relevant figures. However, the examples shown below are for illustrating the light-emitting device of the present invention, and the present invention is not limited to the following examples. In addition, the dimensions, materials, shapes, relative arrangements, etc. of the components described in the embodiments in this specification are not limited, and the scope of the present invention is not limited thereto, but is merely illustrative. In addition, the size and positional relationship of components shown in the drawings may be exaggerated for clarity. In addition, in the following description, in order to omit detailed description appropriately, the same name and symbol are used for the same or similar member.

第1圖係本發明一實施例中所揭示之一發光元件1的上視圖。第2圖係第1圖之左下部分放大圖。第3圖係第2圖的掃描電子顯微鏡(SEM)立體圖。第4圖係沿著第1圖之切線A-A’的剖面圖。第5圖係沿著第1圖之切線B-B’的剖面圖。實施例中所揭露之發光元件1係為一覆晶結構之發光二極體。FIG. 1 is a top view of a light emitting element 1 disclosed in an embodiment of the present invention. Figure 2 is an enlarged view of the lower left part of Figure 1. Fig. 3 is a scanning electron microscope (SEM) perspective view of Fig. 2 . Figure 4 is a sectional view along the tangent line A-A' of Figure 1. Fig. 5 is a sectional view along the tangent line B-B' of Fig. 1. The light emitting element 1 disclosed in the embodiment is a light emitting diode with flip chip structure.

如第1圖之上視圖及第4圖之剖面圖所示,發光元件1包含一基板10包含一側壁10s;一發光疊層11包含複數個外側壁S1位於基板10上,發光疊層11包含一第一半導體層111,一第二半導體層112,及一活性層113位於第一半導體層111及第二半導體層112之間;一半導體結構12位於基板10上,藉由第一半導體層111與發光疊層11相隔一距離,並環繞發光疊層11之複數個外側壁S1;以及一布拉格反射鏡20覆蓋發光疊層11及半導體結構12,其中,半導體結構12包含一側表面12s與基板10之側壁10s直接相接,一與側表面12s相對之內側表面12ns,以及一與側表面12s及內側表面12ns直接連接的上表面12t,布拉格反射鏡20包含一第一側面201s與半導體結構12之側表面12s直接連接,及一第二側面202s與半導體結構12之側表面12s相隔一距離以露出半導體結構之上表面12t。As shown in the top view of FIG. 1 and the cross-sectional view of FIG. 4, the light-emitting element 1 includes a substrate 10 including sidewalls 10s; a light-emitting stack 11 includes a plurality of outer sidewalls S1 on the substrate 10, and the light-emitting stack 11 includes A first semiconductor layer 111, a second semiconductor layer 112, and an active layer 113 are located between the first semiconductor layer 111 and the second semiconductor layer 112; a semiconductor structure 12 is located on the substrate 10, by the first semiconductor layer 111 There is a distance from the light-emitting stack 11 and surrounds a plurality of outer sidewalls S1 of the light-emitting stack 11; and a Bragg reflector 20 covers the light-emitting stack 11 and the semiconductor structure 12, wherein the semiconductor structure 12 includes a side surface 12s and a substrate The side wall 10s of 10 is directly connected, an inner surface 12ns opposite to the side surface 12s, and an upper surface 12t directly connected to the side surface 12s and the inner surface 12ns, and the Bragg reflector 20 includes a first side surface 201s and a semiconductor structure 12 The side surface 12s of the semiconductor structure 12 is directly connected, and a second side surface 202s is separated from the side surface 12s of the semiconductor structure 12 by a distance to expose the upper surface 12t of the semiconductor structure.

如第1圖之上視圖所示,發光元件1可以具有矩形或正方形的外形,並如第4圖~第5圖之側視圖所示,發光元件1之基板10包含複數個側壁10s位於發光元件1之一周圍以構成矩形或正方形的外形。由上視圖觀之,發光元件1的尺寸例如可以是300μmÍ1000μm的矩形形狀或700μmÍ700μm的正方形形狀,但不特別限定於此。As shown in the top view of FIG. 1, the light-emitting element 1 may have a rectangular or square shape, and as shown in the side views of FIGS. 1 to form a rectangular or square shape. Viewed from the top view, the size of the light emitting element 1 may be, for example, a rectangular shape of 300 μm to 1000 μm or a square shape of 700 μm to 700 μm, but it is not particularly limited thereto.

基板10可以為一成長基板,包括用以磊晶成長磷化鋁鎵銦(AlGaInP)之砷化鎵(GaAs)晶圓,或用以成長氮化銦鎵(InGaN)之藍寶石(Al 2O 3)晶圓、氮化鎵(GaN)晶圓或碳化矽(SiC)晶圓。 The substrate 10 may be a growth substrate, including gallium arsenide (GaAs) wafers for epitaxial growth of aluminum gallium indium phosphide (AlGaInP), or sapphire (Al 2 O 3 ) wafer, gallium nitride (GaN) wafer or silicon carbide (SiC) wafer.

於本發明之一實施例中,藉由有機金屬化學氣相沉積法(MOCVD)、分子束磊晶(MBE)、氫化物氣相沉積法(HVPE)、物理氣相沉積法(PVD)或離子電鍍方法以於基板10上形成具有光電特性之發光疊層11,其中物理氣象沉積法包含濺鍍 (Sputtering)或蒸鍍(Evoaporation)法。In one embodiment of the present invention, by metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD) or ion The electroplating method is used to form a light-emitting stack 11 with optoelectronic properties on the substrate 10, wherein the physical vapor deposition method includes sputtering or evaporation (Evoaporation) method.

如第4圖~第5圖所示,發光疊層11包含第一半導體層111,第二半導體層112,以及活性層113位於第一半導體層111及第二半導體層112之間。藉由改變發光疊層11中一層或多層的物理及化學組成以調整發光元件1發出光線的波長。發光疊層11之材料包含Ⅲ-Ⅴ族半導體材料,例如Al xIn yGa (1-x-y)N或Al xIn yGa (1-x-y)P,其中0≦x,y≦1;(x+y)≦1。當發光疊層11之材料為AlInGaP系列材料時,可發出波長介於610 nm及650 nm之間的紅光。當發光疊層11之材料為AlInGaP系列或InGaN系列材料時,可發出波長介於500 nm及570 nm之間的綠光。當發光疊層11之材料為InGaN系列材料時,可發出波長介於400 nm及490 nm之間的藍光。當發光疊層11之材料為AlGaN系列或AlInGaN系列材料時,可發出波長介於400 nm及250 nm之間的紫外光。 As shown in FIGS. 4-5 , the light emitting stack 11 includes a first semiconductor layer 111 , a second semiconductor layer 112 , and an active layer 113 located between the first semiconductor layer 111 and the second semiconductor layer 112 . By changing the physical and chemical composition of one or more layers in the light-emitting stack 11, the wavelength of the light emitted by the light-emitting element 1 can be adjusted. The material of the light emitting stack 11 includes III-V group semiconductor materials, such as Al x In y Ga (1-xy) N or Al x In y Ga (1-xy) P, where 0≦x, y≦1; (x +y)≦1. When the material of the light emitting stack 11 is AlInGaP series material, it can emit red light with a wavelength between 610 nm and 650 nm. When the material of the light-emitting stack 11 is AlInGaP series or InGaN series materials, it can emit green light with a wavelength between 500 nm and 570 nm. When the material of the light emitting stack 11 is an InGaN series material, it can emit blue light with a wavelength between 400 nm and 490 nm. When the material of the light-emitting stack 11 is AlGaN series or AlInGaN series materials, it can emit ultraviolet light with a wavelength between 400 nm and 250 nm.

第一半導體層111和第二半導體層112可為包覆層(cladding layer),兩者具有不同的導電型態、電性、極性,或依摻雜的元素以提供電子或電洞,例如第一半導體層111為n型電性的半導體,第二半導體層112為p型電性的半導體。活性層113形成在第一半導體層111和第二半導體層112之間,電子與電洞於一電流驅動下在活性層113複合,將電能轉換成光能,以發出一光線。活性層113可為單異質結構(single heterostructure, SH),雙異質結構(double heterostructure, DH),雙側雙異質結構(double-side double heterostructure, DDH),或是多層量子井結構(multi-quantum well, MQW)。活性層113之材料可為中性、p型或n型電性的半導體。第一半導體層111、第二半導體層112、或活性層113可為單層或包含多個子層的結構。The first semiconductor layer 111 and the second semiconductor layer 112 can be a cladding layer (cladding layer), both of which have different conductivity types, electric properties, polarities, or provide electrons or holes according to doped elements, such as the first The first semiconductor layer 111 is an n-type semiconductor, and the second semiconductor layer 112 is a p-type semiconductor. The active layer 113 is formed between the first semiconductor layer 111 and the second semiconductor layer 112 . Electrons and holes are driven by a current to recombine in the active layer 113 to convert electrical energy into light energy to emit a light. The active layer 113 can be single heterostructure (single heterostructure, SH), double heterostructure (double heterostructure, DH), double-side double heterostructure (double-side double heterostructure, DDH), or multi-layer quantum well structure (multi-quantum well, MQW). The material of the active layer 113 can be neutral, p-type or n-type semiconductor. The first semiconductor layer 111 , the second semiconductor layer 112 , or the active layer 113 may be a single layer or a structure including multiple sublayers.

發光疊層11包含一上表面及一下表面,活性層113包含一第一上表面及一第二下表面,其中發光疊層11之上表面和活性層113之第一上表面之間包含一第一距離,發光疊層11之下表面和活性層113之第二下表面之間包含一第二距離,且第二距離大於第一距離。The light-emitting stack 11 includes an upper surface and a lower surface, and the active layer 113 includes a first upper surface and a second lower surface, wherein a first upper surface of the light-emitting stack 11 and the first upper surface of the active layer 113 include a A distance includes a second distance between the lower surface of the light emitting stack 11 and the second lower surface of the active layer 113 , and the second distance is greater than the first distance.

於本發明之一實施例中,發光疊層11還可包含一緩衝層(圖未示)位於第一半導體層111和基板10之間,用以釋放基板10和發光疊層11之間因材料晶格不匹配而產生的應力,以減少差排及晶格缺陷,進而提升磊晶品質。緩衝層可為一單層或包含多個子層的結構。於一實施例中,可選用PVD氮化鋁(AlN)做為緩衝層,形成於發光疊層11及基板10之間,用以改善發光疊層11的磊晶品質。在一實施例中,用以形成PVD氮化鋁(AlN)的靶材係由氮化鋁所組成。在另一實施例中,係使用由鋁組成的靶材,於氮源的環境下與鋁靶材反應性地形成氮化鋁。In one embodiment of the present invention, the light emitting stack 11 may further include a buffer layer (not shown) located between the first semiconductor layer 111 and the substrate 10 to release the material between the substrate 10 and the light emitting stack 11 The stress generated by lattice mismatch can reduce misalignment and lattice defects, thereby improving epitaxy quality. The buffer layer can be a single layer or a structure comprising multiple sublayers. In one embodiment, PVD aluminum nitride (AlN) may be used as a buffer layer formed between the light emitting stack 11 and the substrate 10 to improve the epitaxial quality of the light emitting stack 11 . In one embodiment, a target for forming PVD aluminum nitride (AlN) is composed of aluminum nitride. In another embodiment, a target composed of aluminum is used to form aluminum nitride reactively with the aluminum target in the presence of a nitrogen source.

如第1圖之上視圖所示,發光元件1包含半導體結構12位於發光元件1之一周圍以環繞發光疊層11之複數個外側壁S1。如第4圖~第5圖之剖面圖所示,半導體結構12位於基板10上,且半導體結構12藉由第一溝槽110以與發光疊層11相隔離。第一溝槽110包含一最小寬度D介於1 μm~30 μm之間,較佳介於2 μm~14 μm之間,更佳介於5 μm~10 μm之間。第一溝槽110係藉由移除部分的第二半導體層112及活性層113而形成,且第一溝槽110露出部分第一半導體層111之表面111t。第一溝槽110的上視形狀包含矩形環狀、多邊形環狀、圓形環狀、橢圓形環狀或不規則環狀,其中矩形或多邊形之各角落可以圓弧化。As shown in the top view of FIG. 1 , the light-emitting element 1 includes a plurality of outer sidewalls S1 of the light-emitting stack 11 surrounded by a semiconductor structure 12 located on one periphery of the light-emitting element 1 . As shown in the cross-sectional views of FIGS. 4 to 5 , the semiconductor structure 12 is located on the substrate 10 , and the semiconductor structure 12 is isolated from the light emitting stack 11 by the first trench 110 . The first trench 110 includes a minimum width D between 1 μm˜30 μm, preferably between 2 μm˜14 μm, more preferably between 5 μm˜10 μm. The first trench 110 is formed by removing part of the second semiconductor layer 112 and the active layer 113 , and the first trench 110 exposes part of the surface 111t of the first semiconductor layer 111 . The top view shape of the first trench 110 includes a rectangular ring, a polygonal ring, a circular ring, an elliptical ring or an irregular ring, wherein each corner of the rectangle or polygon can be rounded.

於發明之一實施例中,半導體結構12包含與發光疊層11相同的結構。例如,半導體結構12包含第一半導體層111、第二半導體層112及活性層113。半導體結構12的上表面12t包含第二半導體層112之一表面。In one embodiment of the invention, the semiconductor structure 12 includes the same structure as the light emitting stack 11 . For example, the semiconductor structure 12 includes a first semiconductor layer 111 , a second semiconductor layer 112 and an active layer 113 . The upper surface 12t of the semiconductor structure 12 includes a surface of the second semiconductor layer 112 .

發光元件1包含一或複數個凹槽120為第二半導體層112及/或活性層113所環繞。一或複數個凹槽120係藉由移除部份的第二半導體層112及活性層113,以露出第一半導體層111之表面111t。一或複數個凹槽120位於發光疊層11中,且各為第二半導體層112及活性層113所環繞。一或複數個凹槽120的上視形狀各包含圓形、橢圓形、矩形、多邊形、或是任意形狀。複數個凹槽120可包含相同或不相同的上視形狀。複數個凹槽120可排列成複數列,任相鄰兩列或每相鄰兩列上的凹槽120可彼此對齊或是錯開。複數個凹槽120的數目並不特別限定。如第1圖之上視圖所示,複數個凹槽120可以按照固定間隔呈固定圖案的方式配置,使電流可沿水平方向均勻地分散。The light emitting device 1 includes one or more grooves 120 surrounded by the second semiconductor layer 112 and/or the active layer 113 . One or more grooves 120 are made by removing part of the second semiconductor layer 112 and the active layer 113 to expose the surface 111t of the first semiconductor layer 111 . One or a plurality of grooves 120 are located in the light emitting stack 11 and each is surrounded by the second semiconductor layer 112 and the active layer 113 . The top-view shapes of one or more grooves 120 each include circle, ellipse, rectangle, polygon, or any shape. The plurality of grooves 120 may have the same or different top-view shapes. The plurality of grooves 120 can be arranged in a plurality of rows, and the grooves 120 on any two adjacent rows or every two adjacent rows can be aligned with each other or staggered. The number of the plurality of grooves 120 is not particularly limited. As shown in the top view of FIG. 1 , the plurality of grooves 120 can be arranged in a fixed pattern at fixed intervals, so that the current can be uniformly distributed along the horizontal direction.

發光疊層11包含複數個外側壁S1及複數個內側壁S2,其中外側壁S1及內側壁S2分別包含第半導體層111、第二半導體層112及活性層113之一側壁。外側壁S1之一端與第二半導體層12之一表面112t相連接,外側壁S1之另一端與第一半導體層111之一表面111t相連接。內側壁S2之一端與第二半導體層112之表面112t相連接,內側壁S2之另一端與第一半導體層11之表面111t相連接。複數個內側壁S2構成凹槽120之一周圍。複數個外側壁S1構成發光疊層11之一周圍。如第4圖及第5圖所示,外側壁S1與第一半導體層111的表面111t之間具有一第一角度,內側壁S2與第一半導體層111的表面111t之間具有一第二角度,其中第一角度與第二角度之間的角度差異小於20度,較佳小於14度,更佳小於10度。於一實施例中,第一角度包含鈍角、銳角或直角,第二角度包含鈍角、銳角或直角。The light emitting stack 11 includes a plurality of outer sidewalls S1 and a plurality of inner sidewalls S2 , wherein the outer sidewalls S1 and inner sidewalls S2 respectively include sidewalls of the first semiconductor layer 111 , the second semiconductor layer 112 and the active layer 113 . One end of the outer sidewall S1 is connected to a surface 112t of the second semiconductor layer 12 , and the other end of the outer sidewall S1 is connected to a surface 111t of the first semiconductor layer 111 . One end of the inner sidewall S2 is connected to the surface 112t of the second semiconductor layer 112 , and the other end of the inner sidewall S2 is connected to the surface 111t of the first semiconductor layer 11 . A plurality of inner sidewalls S2 form around one of the grooves 120 . A plurality of outer sidewalls S1 constitute a periphery of one of the light emitting stacks 11 . As shown in FIG. 4 and FIG. 5, there is a first angle between the outer sidewall S1 and the surface 111t of the first semiconductor layer 111, and there is a second angle between the inner sidewall S2 and the surface 111t of the first semiconductor layer 111. , wherein the angle difference between the first angle and the second angle is less than 20 degrees, preferably less than 14 degrees, more preferably less than 10 degrees. In one embodiment, the first angle includes an obtuse angle, an acute angle or a right angle, and the second angle includes an obtuse angle, an acute angle or a right angle.

發光元件1包含一或複數個電流阻擋層14位於第二半導體層112上。電流阻擋層14係為非導電材料所形成,包含氧化鋁(Al 2O 3)、氮化矽(SiN x)、氧化矽(SiO x)、氧化鈦(TiO x),或氟化鎂(MgF x)。電流阻擋層14可以包括分布式布拉格反射器(DBR),其中分布式布拉格反射器具有不同折射率的絕缘材料彼此堆叠。電流阻擋層14對於活性層113所發出的光線具有80%以上的透光率或80%以上的光反射率。如第4圖及第5圖所示,電流阻擋層14具有一傾斜的側表面以降低自第二半導體層112剝離的風險,並增加後續疊層的覆蓋性。 The light emitting device 1 includes one or more current blocking layers 14 located on the second semiconductor layer 112 . The current blocking layer 14 is formed of non-conductive materials, including aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ). The current blocking layer 14 may include a distributed Bragg reflector (DBR) in which insulating materials having different refractive indices are stacked on each other. The current blocking layer 14 has a light transmittance of more than 80% or a light reflectance of more than 80% for the light emitted by the active layer 113 . As shown in FIG. 4 and FIG. 5 , the current blocking layer 14 has an inclined side surface to reduce the risk of delamination from the second semiconductor layer 112 and increase the coverage of subsequent stacked layers.

發光元件1包含一透明導電層16位於第二半導體層112及電流阻擋層14上,且透明導電層16覆蓋電流阻擋層14之一側壁。覆蓋於電流阻擋層14之上的透明導電層16的表面輪廓對應於電流阻擋層14之輪廓。透明導電層16自剖面觀之呈階梯狀輪廓,而不是平坦的輪廓。透明導電層16之材料包含對於活性層113所發出的光線為透明的材料,例如,氧化銦錫(ITO)或氧化銦鋅(IZO)。由於透明導電層16形成於第二半導體層112之大致整個面,並與第二半導體層112形成低電阻接觸,例如歐姆接觸,因此電流可以藉由透明導電層16以均勻地擴散通過第二半導體層112。於一實施例中,透明導電層16包含一最外側,其與發光疊層11之外側壁S1或內側壁S2相隔一距離小於20 μm,較佳小於10 μm,更佳小於5 μm。The light emitting device 1 includes a transparent conductive layer 16 located on the second semiconductor layer 112 and the current blocking layer 14 , and the transparent conductive layer 16 covers a sidewall of the current blocking layer 14 . The surface profile of the transparent conductive layer 16 covering the current blocking layer 14 corresponds to the profile of the current blocking layer 14 . The transparent conductive layer 16 has a stepped outline rather than a flat outline when viewed from a cross section. The material of the transparent conductive layer 16 includes a material transparent to the light emitted by the active layer 113 , such as indium tin oxide (ITO) or indium zinc oxide (IZO). Since the transparent conductive layer 16 is formed on substantially the entire surface of the second semiconductor layer 112 and forms a low-resistance contact with the second semiconductor layer 112, such as an ohmic contact, current can be uniformly diffused through the second semiconductor layer 16 through the transparent conductive layer 112. Layer 112. In one embodiment, the transparent conductive layer 16 includes an outermost side, which is separated from the outer sidewall S1 or the inner sidewall S2 of the light emitting stack 11 by a distance of less than 20 μm, preferably less than 10 μm, more preferably less than 5 μm.

透明導電層16的厚度可在0.1 nm至100 nm的範圍內。若透明導電層16的厚度小於0.1 nm,則由於厚度太薄而不能有效地與第二半導體層112形成歐姆接觸。並且,若透明導電層16的厚度大於100 nm,則由於厚度太厚而部分吸收活性層113所發出光線,從而導致發光元件1的亮度減少的問題。The thickness of the transparent conductive layer 16 may range from 0.1 nm to 100 nm. If the thickness of the transparent conductive layer 16 is less than 0.1 nm, the ohmic contact with the second semiconductor layer 112 cannot be effectively formed because the thickness is too thin. Moreover, if the thickness of the transparent conductive layer 16 is greater than 100 nm, the light emitted by the active layer 113 will be partially absorbed due to the thickness being too thick, thereby causing the problem that the brightness of the light emitting element 1 is reduced.

發光元件1包含一或複數個第一接觸電極18位於第一半導體層111上以電連接至第一半導體層111,及一或複數個第二接觸電極19位於第二半導體層112上以電連接至第二半導體層112。如第1圖所示,自發光元件1之一上視圖觀之,第一接觸電極18包含一第一接觸電極墊18a及/或一第一接觸電極延伸部18b。於本實施例中,第一接觸電極墊18a的上視形狀包含圓形或橢圓形,第一接觸電極延伸部18b的上視形狀包含條型、矩形或多邊形。第一接觸電極墊18a及第一接觸電極延伸部18b包含相同的疊層結構與厚度。The light emitting element 1 includes one or a plurality of first contact electrodes 18 located on the first semiconductor layer 111 to be electrically connected to the first semiconductor layer 111, and one or a plurality of second contact electrodes 19 located on the second semiconductor layer 112 to be electrically connected to the second semiconductor layer 112. As shown in FIG. 1 , viewed from a top view of the light emitting device 1 , the first contact electrode 18 includes a first contact electrode pad 18 a and/or a first contact electrode extension 18 b. In this embodiment, the top view shape of the first contact electrode pad 18a includes circle or ellipse, and the top view shape of the first contact electrode extension portion 18b includes strip shape, rectangle shape or polygon shape. The first contact electrode pad 18 a and the first contact electrode extension 18 b include the same stacked structure and thickness.

如第1圖所示,自發光元件1之一上視圖觀之,第二接觸電極19包含一第二接觸電極墊19a及/或一第二接觸電極延伸部19b。於本實施例中,第二接觸電極墊19a的上視形狀包含圓形或橢圓形,第二接觸電極延伸部19b 19b的上視的上視形狀包含條型、矩形或多邊形。第二接觸電極墊19a及第二接觸電極延伸部19b包含相同的疊層結構與厚度。As shown in FIG. 1 , viewed from a top view of the light emitting element 1 , the second contact electrode 19 includes a second contact electrode pad 19 a and/or a second contact electrode extension 19 b. In this embodiment, the top view shape of the second contact electrode pad 19a includes circle or ellipse, and the top view shape of the second contact electrode extensions 19b 19b includes strip shape, rectangle shape or polygon shape. The second contact electrode pad 19 a and the second contact electrode extension 19 b include the same stacked structure and thickness.

如第1圖所示,自發光元件1之一上視圖觀之,一或複數個第一接觸電極18分別位於一或複數個凹槽120內與第一半導體層111相接觸。複數個第一接觸電極18係彼此分離,且第一接觸電極18與凹槽120具有相同的形狀。為讓電流均勻地擴散通過第二半導體層112,第二接觸電極19的位置係重疊於電流阻擋層14的位置。於發明之一實施例中,第二接觸電極19位於電流阻擋層14及透明導電層16之上,且與透明導電層16接觸。於發明之一實施例中,透明導電層16具有一開口(圖未示)對應於第二接觸電極墊19a,且第二接觸電極墊19a藉由此開口與電流阻擋層14及第二半導體層112接觸。於發明之一實施例中,第二接觸電極19與電流阻擋層14具有相似的形狀;於發明之另一實施例中,第二接觸電極19與電流阻擋層14具有不相似的形狀。於發明之一實施例中,如第1圖所示,自發光元件1之一上視觀之,電流阻擋層14包含一面積大於第二接觸電極19之一面積。於另一實施例中,第二接觸電極墊19a與其下方對應的電流阻擋層14具有不相似的形狀,例如第二接觸電極墊19a為圓形,其下方的電流阻擋層14為矩形。於另一實施例中,第二接觸電極墊19a與其下方對應的電流阻擋層14具有相似的形狀,例如第二接觸電極墊19a及其下方的電流阻擋層14為圓形,但是第二接觸電極墊19a的圓心與其下方的電流阻擋層14的圓心互不重疊。或是,第二接觸電極墊19a為圓形,其下方的電流阻擋層14為矩形,第二接觸電極墊19a周圍與其下方的電流阻擋層14周圍之間的距離為非等距。於另一實施例中,位於第二接觸電極墊19a下方的電流阻擋層14包含複數個彼此分離的電流阻擋區域,且透明導電層16於第二接觸電極墊19a下方的位置有一開口,使得部分第二接觸電極墊19a藉由開口及彼此分離的電流阻擋區域之間的間隙直接接觸第二半導體層112;當然於一實施例中,透明導電層16於第二接觸電極墊19a下方的位置可以不具有開口,第二接觸電極墊19a直接接觸透明導電層16。As shown in FIG. 1 , viewed from a top view of the light-emitting element 1 , one or a plurality of first contact electrodes 18 are respectively located in one or a plurality of grooves 120 and are in contact with the first semiconductor layer 111 . The plurality of first contact electrodes 18 are separated from each other, and the first contact electrodes 18 and the groove 120 have the same shape. In order to allow the current to diffuse uniformly through the second semiconductor layer 112 , the position of the second contact electrode 19 is overlapped with the position of the current blocking layer 14 . In an embodiment of the invention, the second contact electrode 19 is located on the current blocking layer 14 and the transparent conductive layer 16 and is in contact with the transparent conductive layer 16 . In one embodiment of the invention, the transparent conductive layer 16 has an opening (not shown) corresponding to the second contact electrode pad 19a, and the second contact electrode pad 19a communicates with the current blocking layer 14 and the second semiconductor layer through the opening. 112 contacts. In one embodiment of the invention, the second contact electrode 19 and the current blocking layer 14 have similar shapes; in another embodiment of the invention, the second contact electrode 19 and the current blocking layer 14 have dissimilar shapes. In one embodiment of the invention, as shown in FIG. 1 , viewed from the top of one of the light emitting elements 1 , the current blocking layer 14 has an area larger than that of the second contact electrode 19 . In another embodiment, the second contact electrode pad 19a and the corresponding current blocking layer 14 below have dissimilar shapes, for example, the second contact electrode pad 19a is circular, and the current blocking layer 14 below it is rectangular. In another embodiment, the second contact electrode pad 19a and the corresponding current blocking layer 14 below it have a similar shape, for example, the second contact electrode pad 19a and the current blocking layer 14 below it are circular, but the second contact electrode pad 19a The center of the circle of the pad 19a and the center of the circle of the current blocking layer 14 below it do not overlap each other. Alternatively, the second contact electrode pad 19a is circular, the current blocking layer 14 below it is rectangular, and the distance between the second contact electrode pad 19a and the current blocking layer 14 below is not equidistant. In another embodiment, the current blocking layer 14 located below the second contact electrode pad 19a includes a plurality of current blocking regions separated from each other, and the transparent conductive layer 16 has an opening at the position below the second contact electrode pad 19a, so that part The second contact electrode pad 19a directly contacts the second semiconductor layer 112 through the opening and the gap between the separated current blocking regions; of course, in one embodiment, the position of the transparent conductive layer 16 below the second contact electrode pad 19a can be Having no opening, the second contact electrode pad 19 a directly contacts the transparent conductive layer 16 .

於發明之另一實施例中,如第1圖所示,發光元件1包含一或複數個第一電流阻擋層13位於第一半導體層111及第一接觸電極18之間。複數個第一電流阻擋層13以一距離彼此相隔離,其中上述距離可為一固定值。較靠近於第一接觸電極墊18a之兩相鄰的複數個第一電流阻擋層13之間的距離較遠離於第一接觸電極墊18a之兩相鄰的複數個第一電流阻擋層13之間的距離長或短。複數個第一電流阻擋層13的數目可隨著第一接觸電極18的長度增長而增加。當第一電流阻擋層13係為非導電材料所形成,包含氧化鋁(Al 2O 3)、氮化矽(SiN x)、氧化矽(SiO x)、氧化鈦(TiO x),或氟化鎂(MgF x)。第一電流阻擋層13可以包括分布式布拉格反射器(DBR),其中分布式布拉格反射器具有不同折射率的絕缘材料彼此堆叠。第一電流阻擋層13對於活性層113所發出的光線具有80%以上的透光率或80%以上的光反射率。第一電流阻擋層13具有一傾斜的側表面以降低自第一半導體層111剝離的風險,並增加後續疊層的覆蓋性。於發明之一實施例中,複數個第一電流阻擋層13之寬度大於第一接觸電極18之寬度。於發明之一實施例中,位於第一接觸電極墊18a下方的第一電流阻擋層13之面積大於或小於第一接觸電極墊18a的面積。於發明之一實施例中,第一接觸電極18與於第一半導體層111之間沒有第一電流阻擋層13。於發明之一實施例中,第一接觸電極18與第一半導體層111或第一電流阻擋層13之間可包含一透明導電層(圖未示)。 In another embodiment of the invention, as shown in FIG. 1 , the light emitting device 1 includes one or more first current blocking layers 13 located between the first semiconductor layer 111 and the first contact electrode 18 . The plurality of first current blocking layers 13 are separated from each other by a distance, wherein the distance can be a fixed value. The distance between the two adjacent plural first current blocking layers 13 closer to the first contact electrode pad 18a is farther away from the distance between the two adjacent plural first current blocking layers 13 of the first contact electrode pad 18a long or short distance. The number of the plurality of first current blocking layers 13 may increase as the length of the first contact electrode 18 increases. When the first current blocking layer 13 is formed of a non-conductive material, including aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or fluoride Magnesium ( MgFx ). The first current blocking layer 13 may include a distributed Bragg reflector (DBR) in which insulating materials having different refractive indices are stacked on each other. The first current blocking layer 13 has a light transmittance of more than 80% or a light reflectance of more than 80% for the light emitted by the active layer 113 . The first current blocking layer 13 has an inclined side surface to reduce the risk of delamination from the first semiconductor layer 111 and increase the coverage of subsequent stacked layers. In one embodiment of the invention, the width of the plurality of first current blocking layers 13 is greater than the width of the first contact electrode 18 . In one embodiment of the invention, the area of the first current blocking layer 13 located under the first contact electrode pad 18a is larger or smaller than the area of the first contact electrode pad 18a. In one embodiment of the invention, there is no first current blocking layer 13 between the first contact electrode 18 and the first semiconductor layer 111 . In an embodiment of the invention, a transparent conductive layer (not shown) may be included between the first contact electrode 18 and the first semiconductor layer 111 or the first current blocking layer 13 .

如第4圖及第5圖所示,透明導電層16包含一部分位於電流阻擋層14及第二接觸電極19之間;以及另一部分直接接觸第二半導體層12。當電流通過第二接觸電極19時,因電流阻擋層14位於第二接觸電極19下方,電流無法透過電流阻擋層14,自第二接觸電極直接向下傳導至第二半導體層12,所以電流會被迫流到透明導電層16後,藉由透明導電層16在水平方向上進行電流擴散,並將電流傳導至第二半導體層112。As shown in FIG. 4 and FIG. 5 , the transparent conductive layer 16 includes a part located between the current blocking layer 14 and the second contact electrode 19 ; and another part directly contacting the second semiconductor layer 12 . When the current passes through the second contact electrode 19, because the current blocking layer 14 is located below the second contact electrode 19, the current cannot pass through the current blocking layer 14, and is directly conducted downward from the second contact electrode to the second semiconductor layer 12, so the current will After being forced to flow to the transparent conductive layer 16 , the current spreads in the horizontal direction through the transparent conductive layer 16 and conducts the current to the second semiconductor layer 112 .

第一接觸電極18及第二接觸電極19分別具有一傾斜的側表面以降低自透明導電層16或第一半導體層111剝離的風險,並增加後續疊層的覆蓋性。於一實施例中,第一接觸電極18之傾斜的側表面與第一半導體層111之表面之間具有一內夾角介於30度及75度之間。第二接觸電極19之傾斜的側表面與透明導電層16之表面之間具有一內夾角介於30度及75度之間。The first contact electrode 18 and the second contact electrode 19 respectively have an inclined side surface to reduce the risk of delamination from the transparent conductive layer 16 or the first semiconductor layer 111 and increase the coverage of subsequent stacked layers. In one embodiment, the inclined side surface of the first contact electrode 18 and the surface of the first semiconductor layer 111 have an inner angle between 30 degrees and 75 degrees. There is an inner angle between the inclined side surface of the second contact electrode 19 and the surface of the transparent conductive layer 16 between 30 degrees and 75 degrees.

如第1圖所示,自發光元件1之一上視圖觀之,第二接觸電極19位於第一接觸電極18之左右兩側。As shown in FIG. 1 , viewed from a top view of the light emitting element 1 , the second contact electrodes 19 are located on the left and right sides of the first contact electrodes 18 .

如第1圖所示,於一實施例中,自發光元件1之一上視圖觀之,第一接觸電極墊18a及第二接觸電極墊19a包含不相同的直徑以做為不同電性的鑑別。As shown in FIG. 1, in one embodiment, viewed from a top view of the light-emitting element 1, the first contact electrode pad 18a and the second contact electrode pad 19a include different diameters for identification of different electrical properties .

第一接觸電極18及第二接觸電極19包含金屬材料,例如鉻(Cr)、鈦(Ti)、鎢(W)、金(Au)、鋁(Al)、銦(In)、錫(Sn)、鎳(Ni) 或鉑(Pt)等金屬或上述材料之合金。第一接觸電極18及第二接觸電極19可由單個層或是多個層所組成。例如,第一接觸電極18或第二接觸電極19可包括Ti/Au層、Ti/Pt/Au層、Cr/Au層、Cr/Pt/Au層、Ni/Au層、Ni/Pt/Au層或Cr/Al/Cr/Ni/Au層。The first contact electrode 18 and the second contact electrode 19 include metal materials such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn) , nickel (Ni) or platinum (Pt) and other metals or alloys of the above materials. The first contact electrode 18 and the second contact electrode 19 can be composed of a single layer or multiple layers. For example, the first contact electrode 18 or the second contact electrode 19 may include Ti/Au layer, Ti/Pt/Au layer, Cr/Au layer, Cr/Pt/Au layer, Ni/Au layer, Ni/Pt/Au layer Or Cr/Al/Cr/Ni/Au layer.

第一接觸電極18或第二接觸電極19的厚度優選為0.5 μm至2.5 μm。於一實施例中,第一接觸電極18之一上表面係低於第二半導體層112之表面112t,換言之,第一接觸電極18之厚度係小於凹槽120之深度。於另一實施例中,第一接觸電極18之一上表面係凸出於第二半導體層112之表面112t,換言之,第一接觸電極18之厚度係大於凹槽120之深度。若第一接觸電極18或第二接觸電極19的厚度小於0.5 μm,則無法有效地傳導電流。並且,若第一接觸電極18或第二接觸電極19的厚度大於2.5 μm,則因過多的生產製造時間而導致製造上的損失。The thickness of the first contact electrode 18 or the second contact electrode 19 is preferably 0.5 μm to 2.5 μm. In one embodiment, an upper surface of the first contact electrode 18 is lower than the surface 112t of the second semiconductor layer 112 , in other words, the thickness of the first contact electrode 18 is smaller than the depth of the groove 120 . In another embodiment, an upper surface of the first contact electrode 18 protrudes from the surface 112t of the second semiconductor layer 112 , in other words, the thickness of the first contact electrode 18 is greater than the depth of the groove 120 . If the thickness of the first contact electrode 18 or the second contact electrode 19 is less than 0.5 μm, current cannot be efficiently conducted. In addition, if the thickness of the first contact electrode 18 or the second contact electrode 19 is greater than 2.5 μm, excessive production time will result in loss in production.

發光元件1包含一布拉格反射鏡(DBR)20覆蓋於發光疊層11、透明導電層16、第一接觸電極18及第二接觸電極19之上。布拉格反射鏡(DBR)20包含一或複數個第一開口201位於第一接觸電極墊18a上,並露出第一接觸電極墊18a之一表面,其中第一接觸電極延伸部18b為布拉格反射鏡(DBR)20完全覆蓋。布拉格反射鏡(DBR)20更包含一或複數個第二開口202位於第二接觸電極19之第二接觸電極墊19a上,並露出第二接觸電極墊19a之一表面,其中第二接觸電極延伸部19b為布拉格反射鏡(DBR)20完全覆蓋。The light emitting device 1 includes a Bragg reflector (DBR) 20 covering the light emitting stack 11 , the transparent conductive layer 16 , the first contact electrode 18 and the second contact electrode 19 . The Bragg reflector (DBR) 20 includes one or a plurality of first openings 201 located on the first contact electrode pad 18a, and exposes a surface of the first contact electrode pad 18a, wherein the first contact electrode extension 18b is a Bragg reflector ( DBR) 20 full coverage. The Bragg reflector (DBR) 20 further includes one or a plurality of second openings 202 located on the second contact electrode pad 19a of the second contact electrode 19, and exposing a surface of the second contact electrode pad 19a, wherein the second contact electrode extends Portion 19b is completely covered by Bragg reflector (DBR) 20 .

於發明之一實施例中,如第1圖之上視圖所示,布拉格反射鏡(DBR)20之第一開口201包含一第一開口直徑小於第一接觸電極墊18a之一直徑。布拉格反射鏡(DBR)20之第二開口202包含一第二開口直徑小於第二接觸電極墊19a之一直徑。In one embodiment of the invention, as shown in the top view of FIG. 1 , the first opening 201 of the Bragg reflector (DBR) 20 includes a first opening diameter smaller than that of the first contact electrode pad 18a. The second opening 202 of the Bragg reflector (DBR) 20 includes a second opening diameter smaller than that of the second contact electrode pad 19a.

於發明之一實施例中,如第1圖之上視圖所示,布拉格反射鏡(DBR)20之複數個第一開口201之一數目小於布拉格反射鏡(DBR)20之複數個第二開口202之一數目。In one embodiment of the invention, as shown in the top view of FIG. 1 , one of the plurality of first openings 201 of the Bragg reflector (DBR) 20 is smaller than the plurality of second openings 202 of the Bragg reflector (DBR) 20 one number.

如第4圖~第5圖之側視圖所示,布拉格反射鏡(DBR)20覆蓋發光疊層11及半導體結構12,將來自發光疊層11之活性層113的光反射到基板10之一方向上。布拉格反射鏡20包含不同折射率的兩種以上之介電材料交替堆疊。介電材料包含氧化鋁(Al 2O 3)、氮化矽(SiN x)、氧化矽(SiO x)、氧化鈦(TiO x),或氟化鎂(MgF x)。例如,可通過層疊SiO 2/TiO 2或SiO 2/Nb 2O 5等層來形成高反射率的絕緣反射層。當發光元件1所發射的光的波長為λ時,布拉格反射鏡20的光學厚度可被設定為λ/4的整數倍。布拉格反射鏡20的光學厚度在λ/4的整數倍的基礎上可具有±30%的偏差。於一實施例中,布拉格反射鏡20包含一或複數個模堆,每一模堆中包含複數介電層對,每一介電層對中,包含第一介電層和第二介電層。其中,第一介電層的第一光學厚度及第二介電層的第二光學厚度相對於可見光波段(400nm ~ 700nm)之中心波長λ ,例如550nm,的比值可大於1/4、小於1/4或一層大於1/4,另一層小於1/4。 As shown in the side views of FIGS. 4 to 5, a Bragg reflector (DBR) 20 covers the light-emitting stack 11 and the semiconductor structure 12, and reflects light from the active layer 113 of the light-emitting stack 11 to one direction of the substrate 10. . The Bragg reflector 20 includes two or more dielectric materials with different refractive indices stacked alternately. The dielectric material includes aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ). For example, an insulating reflective layer with high reflectivity can be formed by laminating layers such as SiO 2 /TiO 2 or SiO 2 /Nb 2 O 5 . When the wavelength of light emitted by the light emitting element 1 is λ, the optical thickness of the Bragg reflector 20 can be set to be an integer multiple of λ/4. The optical thickness of the Bragg mirror 20 may have a deviation of ±30% on the basis of integer multiples of λ/4. In one embodiment, the Bragg reflector 20 includes one or more die stacks, each die stack includes a plurality of dielectric layer pairs, and each dielectric layer pair includes a first dielectric layer and a second dielectric layer . Wherein, the ratio of the first optical thickness of the first dielectric layer and the second optical thickness of the second dielectric layer to the central wavelength λ ' of the visible light band (400nm ~ 700nm), such as 550nm, can be greater than 1/4, less than 1/4 or one layer is larger than 1/4 and the other layer is smaller than 1/4.

布拉格反射鏡20包含非導電材料,可藉由物理蒸鍍法(PVD;Physical Vapor Deposition)、電子束蒸鍍法(E-Beam Evaporation)、濺射法(Sputtering)或熱蒸鍍法(Thermal Evaporation)而形成。在形成布拉格反射鏡20之前,優選地形成具備一定的厚度的介質層(圖未示),從而能夠穩定地形成布拉格反射鏡20,也有利於光的反射。介質層(圖未示)的材質優選為SiO 2,關於其厚度,例如可以是0.2μm〜l μm。布拉格反射鏡20的整體厚度可以是1〜8μm。於發明之一實施例中,在形成布拉格反射鏡20之後,可形成具備一定的厚度的另一介質層(圖未示),有利於光的摘出。 The Bragg reflector 20 includes a non-conductive material, which can be deposited by physical evaporation (PVD; Physical Vapor Deposition), electron beam evaporation (E-Beam Evaporation), sputtering (Sputtering) or thermal evaporation (Thermal Evaporation) ) to form. Before forming the Bragg reflector 20 , it is preferable to form a dielectric layer (not shown) with a certain thickness, so that the Bragg reflector 20 can be stably formed, and it is also beneficial to light reflection. The material of the dielectric layer (not shown in the figure) is preferably SiO 2 , and its thickness may be, for example, 0.2 μm˜1 μm. The overall thickness of the Bragg mirror 20 may be 1˜8 μm. In an embodiment of the invention, after forming the Bragg reflector 20, another dielectric layer (not shown) with a certain thickness can be formed to facilitate light extraction.

於發明之一實施例中,如第3圖之掃描電子顯微鏡(SEM)圖及第5圖之剖面圖所示,布拉格反射鏡20包含一第一厚度T1位於第二半導體層12之表面112t之上及一第二厚度T2位於第二半導體層12之表面112t之下,其中第一厚度T1大於第二厚度T2。例如,第一厚度T1大於2μm,較佳大於3μm,更佳大於4μm,且第二厚度T2小於2μm。In one embodiment of the invention, as shown in the scanning electron microscope (SEM) figure of FIG. 3 and the cross-sectional view of FIG. and a second thickness T2 located below the surface 112t of the second semiconductor layer 12, wherein the first thickness T1 is greater than the second thickness T2. For example, the first thickness T1 is greater than 2 μm, preferably greater than 3 μm, more preferably greater than 4 μm, and the second thickness T2 is less than 2 μm.

如第1圖之上視圖、第4圖及第5圖之剖面圖所示,因為布拉格反射鏡(DBR)20下方為疊層結構,例如,發光疊層11、電流阻擋層14、透明導電層16、第一接觸電極18或第二接觸電極19等結構,因此當發光元件1經過切割、劈裂製程時,布拉格反射鏡(DBR)20容易因這些具有高度差的結構,而在發光元件1的周圍形成破裂面S。當破裂面S延伸至發光疊層11,露出發光疊層11,布拉格反射鏡(DBR)20即喪失保護發光元件1的效果,水氣容易藉由破裂面S進入至發光疊層11的內部。於本發明之一實施例中,為了避免破裂面S延伸至發光疊層11,發光元件1包含半導體結構12位於基板10上,且半導體結構12與發光疊層11之間具有第一半導體層111,藉由第一半導體層111將半導體結構12與發光疊層11分隔一距離,並且半導體結構12環繞發光疊層11。如第5圖所示,因為布拉格反射鏡(DBR)20的成膜特性,即使發光元件1的周圍有破裂面S,破裂面S會如布拉格反射鏡(DBR)20的第二側面202s所示,停止於半導體結構12或第一溝槽110的轉角處。As shown in the top view of FIG. 1, the cross-sectional views of FIG. 4 and FIG. 5, because the bottom of the Bragg reflector (DBR) 20 is a stacked structure, for example, a light emitting stack 11, a current blocking layer 14, a transparent conductive layer 16. The structure of the first contact electrode 18 or the second contact electrode 19. Therefore, when the light-emitting element 1 undergoes cutting and splitting processes, the Bragg reflector (DBR) 20 is likely to be in the light-emitting element 1 due to these structures with height differences. A fracture surface S is formed around the . When the rupture surface S extends to the light-emitting stack 11 to expose the light-emitting stack 11 , the Bragg reflector (DBR) 20 loses the effect of protecting the light-emitting element 1 , and water vapor easily enters the interior of the light-emitting stack 11 through the rupture surface S. In one embodiment of the present invention, in order to prevent the fracture surface S from extending to the light-emitting stack 11, the light-emitting element 1 includes a semiconductor structure 12 located on the substrate 10, and a first semiconductor layer 111 is provided between the semiconductor structure 12 and the light-emitting stack 11 , the semiconductor structure 12 and the light emitting stack 11 are separated by a distance by the first semiconductor layer 111 , and the semiconductor structure 12 surrounds the light emitting stack 11 . As shown in FIG. 5, due to the film-forming properties of the Bragg reflector (DBR) 20, even if there is a cracked surface S around the light-emitting element 1, the cracked surface S will be as shown on the second side 202s of the Bragg reflector (DBR) 20. , stop at the corner of the semiconductor structure 12 or the first trench 110 .

於發明之一實施例中,如第3圖之掃描電子顯微鏡(SEM)圖及第5圖之剖面圖所示,布拉格反射鏡(DBR)20的第二側面202s與半導體結構12的內側表面12ns之間包含一鈍角介於95度~140度之間,較佳介於100度~130度之間,更佳介於100度~120度之間。In one embodiment of the invention, as shown in the scanning electron microscope (SEM) figure of FIG. 3 and the cross-sectional view of FIG. There is an obtuse angle between 95 degrees and 140 degrees, preferably between 100 degrees and 130 degrees, more preferably between 100 degrees and 120 degrees.

於發明之一實施例中,如第3圖之掃描電子顯微鏡(SEM)圖、第4圖及第5圖之剖面圖所示,發光疊層11的外側壁S1與第一半導體層111的表面111t之間具有第一角度,半導體結構12的內側表面12ns與第一半導體層111的表面111t之間具有一第三角度,且第一角度大於第三角度以避免布拉格反射鏡(DBR)20膜層的破裂,其中第一角度與第三角度之間的角度差異小於30度,較佳小於20度,更佳小於10度。In one embodiment of the invention, as shown in the scanning electron microscope (SEM) diagram of FIG. 3 and the cross-sectional diagrams of FIG. 4 and FIG. There is a first angle between 111t, there is a third angle between the inner surface 12ns of the semiconductor structure 12 and the surface 111t of the first semiconductor layer 111, and the first angle is greater than the third angle to avoid the Bragg reflector (DBR) 20 film Breakage of the layer, wherein the angle difference between the first angle and the third angle is less than 30 degrees, preferably less than 20 degrees, more preferably less than 10 degrees.

發光元件1包含一第一電極墊21以覆蓋布拉格反射鏡(DBR)20之一或複數個第一開口201,並藉由一或複數個第一開口201以接觸第一接觸電極墊18a。發光元件1包含一第二電極墊22以覆蓋一或複數個布拉格反射鏡(DBR)20之一或複數個第二開口202,並藉由一或複數個第二開口202以接觸第二接觸電極墊19a。第一接觸電極墊18a及第二接觸電極墊19a分別藉由第一接觸電極延伸部18b及第二接觸電極延伸部19b分別電連接至第一半導體層111及第二半導體層112。The light emitting device 1 includes a first electrode pad 21 covering one or a plurality of first openings 201 of a Bragg reflector (DBR) 20 , and contacts the first contact electrode pad 18a through the one or a plurality of first openings 201 . The light-emitting element 1 includes a second electrode pad 22 to cover one or a plurality of second openings 202 of one or a plurality of Bragg reflectors (DBR) 20, and to contact a second contact electrode through one or a plurality of second openings 202 Pad 19a. The first contact electrode pad 18 a and the second contact electrode pad 19 a are respectively electrically connected to the first semiconductor layer 111 and the second semiconductor layer 112 through the first contact electrode extension 18 b and the second contact electrode extension 19 b .

第一電極墊21或第二電極墊22之上表面可以為非平面。具體而言,第一電極墊21或第二電極墊22的上表面具有與第一接觸電極18的上表面和第二接觸電極19的上表面的表面輪廓相對應的表面輪廓。換言之,第一電極墊21或第二電極墊22設置在第一接觸電極18和第二接觸電極19上,其中第一接觸電極18和第二接觸電極19具有非平坦表面輪廓,因此具有長條形、圓形或階梯形表面。如第4圖及第5圖所示,第一電極墊21或第二電極墊22的上表面可包括至少一個凹陷部及至少一個凸出部,其分別設置於第一接觸電極18和第二接觸電極19所放置的區域中。因此,第一電極墊21或第二電極墊22的上表面可具有階梯形表面。The upper surface of the first electrode pad 21 or the second electrode pad 22 may be non-planar. Specifically, the upper surface of the first electrode pad 21 or the second electrode pad 22 has a surface profile corresponding to the surface profile of the upper surface of the first contact electrode 18 and the upper surface of the second contact electrode 19 . In other words, the first electrode pad 21 or the second electrode pad 22 is disposed on the first contact electrode 18 and the second contact electrode 19, wherein the first contact electrode 18 and the second contact electrode 19 have a non-flat surface profile and thus have a long strip Shaped, rounded or stepped surfaces. As shown in Figures 4 and 5, the upper surface of the first electrode pad 21 or the second electrode pad 22 may include at least one concave portion and at least one protruding portion, which are respectively arranged on the first contact electrode 18 and the second contact electrode 18. In the area where the contact electrode 19 is placed. Accordingly, the upper surface of the first electrode pad 21 or the second electrode pad 22 may have a stepped surface.

自發光元件1之一上視圖觀之,如第1圖所示,一或複數個第一接觸電極墊18a僅為第一電極墊21所覆蓋,且一或複數個第二接觸電極墊19a僅為第二電極墊22所覆蓋。一或複數個第一接觸電極延伸部18b為第二電極墊22所覆蓋,且一或複數個第二接觸電極延伸部19b為第一電極墊21及/或第二電極墊22所覆蓋。於一實施例中,一或複數個第一接觸電極延伸部18b為第一電極墊21及第二電極墊22所覆蓋。於一實施例中,一或複數個第一接觸電極墊18a不被第一電極墊21所覆蓋,亦即第一電極墊21避開第一接觸電極墊18a設置。於一實施例中,一或複數個第一接觸電極延伸部18b不被第一電極墊21及/或第二電極墊22所覆蓋,亦即第一電極墊21及/或第二電極墊22避開第一接觸電極延伸部18b設置。於一實施例中,一或複數個第二接觸電極墊19a不被第二電極墊22所覆蓋,亦即第二電極墊22避開第二接觸電極墊19a設置。於一實施例中,一或複數個第二接觸電極延伸部19b不被第一電極墊21及/或第二電極墊22所覆蓋,亦即第一電極墊21及/或第二電極墊22避開第二接觸電極延伸部19b設置。From a top view of the light-emitting element 1, as shown in FIG. 1, one or a plurality of first contact electrode pads 18a are only covered by the first electrode pad 21, and one or a plurality of second contact electrode pads 19a are only covered by the first electrode pad 21. Covered by the second electrode pad 22 . One or more first contact electrode extensions 18b are covered by the second electrode pads 22 , and one or more second contact electrode extensions 19b are covered by the first electrode pads 21 and/or the second electrode pads 22 . In one embodiment, one or more first contact electrode extensions 18 b are covered by the first electrode pad 21 and the second electrode pad 22 . In one embodiment, one or more first contact electrode pads 18 a are not covered by the first electrode pads 21 , that is, the first electrode pads 21 are disposed away from the first contact electrode pads 18 a. In one embodiment, one or a plurality of first contact electrode extensions 18b are not covered by the first electrode pad 21 and/or the second electrode pad 22, that is, the first electrode pad 21 and/or the second electrode pad 22 It is provided avoiding the first contact electrode extension 18b. In one embodiment, one or more second contact electrode pads 19 a are not covered by the second electrode pads 22 , that is, the second electrode pads 22 are arranged to avoid the second contact electrode pads 19 a. In one embodiment, one or a plurality of second contact electrode extensions 19b are not covered by the first electrode pad 21 and/or the second electrode pad 22, that is, the first electrode pad 21 and/or the second electrode pad 22 The second contact electrode extension 19b is avoided.

第一電極墊21及第二電極墊22包含金屬材料,例如鉻(Cr)、鈦(Ti)、鎢(W)、金(Au)、鋁(Al)、銦(In)、錫(Sn)、鎳(Ni)、鉑(Pt)等金屬或上述材料之合金。第一電極墊21及第二電極墊22可由單個層或是多個層所組成。例如,第一電極墊21或第二電極墊22可包括Ti/Au層、Ti/Pt/Au層、Cr/Au層、Cr/Pt/Au層、Ni/Au層、Ni/Pt/Au層或Cr/Al/Cr/Ni/Au層。第一電極墊21及第二電極墊22可做為外電源供電至第一半導體層111及第二半導體層112之電流路徑。The first electrode pad 21 and the second electrode pad 22 include metal materials such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn) , nickel (Ni), platinum (Pt) and other metals or alloys of the above materials. The first electrode pad 21 and the second electrode pad 22 can be composed of a single layer or multiple layers. For example, the first electrode pad 21 or the second electrode pad 22 may include Ti/Au layer, Ti/Pt/Au layer, Cr/Au layer, Cr/Pt/Au layer, Ni/Au layer, Ni/Pt/Au layer Or Cr/Al/Cr/Ni/Au layer. The first electrode pad 21 and the second electrode pad 22 can be used as a current path for supplying power from an external power source to the first semiconductor layer 111 and the second semiconductor layer 112 .

於本發明之一實施例中,第一電極墊21包含一尺寸與第二電極墊22之一尺寸相同或不同,此尺寸可為寬度或面積。例如,第一電極墊21或第二電極墊22的上視面積可為第一電極墊21及第二電極墊22的上視面積相加所得的值的0.8倍以上且小於1倍的大小。In an embodiment of the present invention, the first electrode pad 21 includes a dimension that is the same as or different from that of the second electrode pad 22 , and the dimension may be a width or an area. For example, the top view area of the first electrode pad 21 or the second electrode pad 22 may be 0.8 times or more and less than 1 time the value obtained by adding the top view areas of the first electrode pad 21 and the second electrode pad 22 .

第一電極墊21或第二電極墊22分別包含一傾斜側面,因此第一電極墊21或第二電極墊22的側視剖面面積可沿厚度方向發生變化。例如,第一電極墊21或第二電極墊22的側視剖面面積可隨著遠離發光疊層11的上表面的方向逐漸變小。The first electrode pad 21 or the second electrode pad 22 respectively includes an inclined side surface, so the cross-sectional area of the first electrode pad 21 or the second electrode pad 22 can change along the thickness direction. For example, the side view cross-sectional area of the first electrode pad 21 or the second electrode pad 22 may gradually become smaller along the direction away from the upper surface of the light emitting stack 11 .

第一電極墊21與第二電極墊22之間包含一間隔,間隔包含一最短距離約為10 μm以上,及一最長距離約為250 μm以下。於上述範圍內,藉由縮小第一電極墊21與第二電極墊22之間的間隔可以增大第一電極墊21與第二電極墊22的上視面積,從而可提高發光元件l的散熱效率,且避免第一電極墊21與第二電極墊22之間的短路。There is a gap between the first electrode pad 21 and the second electrode pad 22, and the gap includes a shortest distance of about 10 μm or more and a longest distance of about 250 μm or less. Within the above range, by reducing the distance between the first electrode pad 21 and the second electrode pad 22, the top view area of the first electrode pad 21 and the second electrode pad 22 can be increased, thereby improving the heat dissipation of the light emitting element 1. efficiency and avoid short circuit between the first electrode pad 21 and the second electrode pad 22 .

第一電極墊21與第二電極墊22包含一厚度介於1~100μm之間,較佳為1.5~6μm之間。The first electrode pad 21 and the second electrode pad 22 have a thickness between 1-100 μm, preferably between 1.5-6 μm.

第6圖係本發明另一實施例所揭示之一發光元件2的上視圖。第7圖係沿著第6圖之切線C-C’的剖面圖。實施例中所揭露之發光元件2係為一覆晶結構之發光二極體。發光元件2與發光元件1包含相同或相似的部件,其中相同或相似的部件將在第6圖~第7圖中以相同的標號於下描述。FIG. 6 is a top view of a light emitting element 2 disclosed in another embodiment of the present invention. Fig. 7 is a sectional view along the tangent line C-C' of Fig. 6. The light emitting element 2 disclosed in the embodiment is a light emitting diode with flip chip structure. The light-emitting element 2 and the light-emitting element 1 include the same or similar components, wherein the same or similar components will be described below with the same reference numerals in FIGS. 6-7 .

如第6圖之上視圖及第7圖之剖面圖所示,發光元件2包含一基板10包含一側壁10s;一發光疊層11包含複數個外側壁S1位於基板10上,發光疊層11包含一第一半導體層111,一第二半導體層112,及一活性層113位於第一半導體層111及第二半導體層112之間;一半導體結構12位於基板10上,藉由第一半導體層111與發光疊層11相隔一距離並環繞發光疊層11之複數個側面;一第一溝槽110位於基板10上,露出第一半導體層111,且位於發光疊層11及半導體結構12之間;一第二溝槽1101位於基板10上,露出第一半導體層111,藉由半導體結構12與第一溝槽110相隔一距離並環繞半導體結構12之複數個側面;以及一布拉格反射鏡20覆蓋發光疊層11及半導體結構12,其中,半導體結構12包含一側表面12s與基板10之側壁10s相隔一距離,一與側表面12s相對之內側表面12ns,以及一與側表面12s及內側表面12ns直接相接之上表面12t,布拉格反射鏡20包含一第一側面201s與第一半導體層111之側面111s及一第二側面202s與半導體結構12之側表面12s直接連接。As shown in the top view of FIG. 6 and the cross-sectional view of FIG. 7, the light-emitting element 2 includes a substrate 10 including sidewalls 10s; a light-emitting stack 11 includes a plurality of outer sidewalls S1 on the substrate 10, and the light-emitting stack 11 includes A first semiconductor layer 111, a second semiconductor layer 112, and an active layer 113 are located between the first semiconductor layer 111 and the second semiconductor layer 112; a semiconductor structure 12 is located on the substrate 10, by the first semiconductor layer 111 A distance from the light-emitting stack 11 and surrounding multiple sides of the light-emitting stack 11; a first groove 110 is located on the substrate 10, exposing the first semiconductor layer 111, and is located between the light-emitting stack 11 and the semiconductor structure 12; A second trench 1101 is located on the substrate 10, exposing the first semiconductor layer 111, separated by a distance from the first trench 110 by the semiconductor structure 12 and surrounding a plurality of sides of the semiconductor structure 12; and a Bragg reflector 20 covering the light emitting A stack 11 and a semiconductor structure 12, wherein the semiconductor structure 12 includes a distance between one side surface 12s and the side wall 10s of the substrate 10, an inner side surface 12ns opposite to the side surface 12s, and a side surface 12s and the inner side surface 12ns directly Contacting the upper surface 12t, the Bragg reflector 20 includes a first side 201s directly connected to the side 111s of the first semiconductor layer 111 and a second side 202s directly connected to the side surface 12s of the semiconductor structure 12 .

於發明之一實施例中,布拉格反射鏡20之第二側面202s係與半導體結構12之內側表面12ns直接連接。In one embodiment of the invention, the second side 202s of the Bragg mirror 20 is directly connected to the inner surface 12ns of the semiconductor structure 12 .

如第6圖之上視圖所示,發光元件2包含第一溝槽110及第二溝槽1101位於第一半導體層111上,並環繞發光疊層11之複數個側面,其中半導體結構12位於第一溝槽110及第二溝槽1101之間,並環繞發光疊層11之複數個側面。如第7圖之剖面圖所示,半導體結構12位於基板上,且半導體結構12藉由第一溝槽110以與發光疊層11相隔離。第一溝槽110包含一最小寬度D介於1 μm~30 μm之間,較佳介於2 μm~14 μm之間,更佳介於5 μm~10 μm之間。第一溝槽110係藉由移除部分的第二半導體層112及活性層113而形成,且第一溝槽110露出部分第一半導體層111。第一溝槽110的上視形狀包含矩形環狀或多邊形環狀、圓形環狀、橢圓形環狀或不規則環狀,其中矩形或多邊形之各角落可以圓弧化。As shown in the top view of FIG. 6, the light-emitting element 2 includes a first trench 110 and a second trench 1101 on the first semiconductor layer 111, and surrounds a plurality of sides of the light-emitting stack 11, wherein the semiconductor structure 12 is located on the first semiconductor layer 111. Between the first groove 110 and the second groove 1101 , and surround multiple sides of the light emitting stack 11 . As shown in the cross-sectional view of FIG. 7 , the semiconductor structure 12 is located on the substrate, and the semiconductor structure 12 is isolated from the light emitting stack 11 by the first trench 110 . The first trench 110 includes a minimum width D between 1 μm˜30 μm, preferably between 2 μm˜14 μm, more preferably between 5 μm˜10 μm. The first trench 110 is formed by removing part of the second semiconductor layer 112 and the active layer 113 , and the first trench 110 exposes part of the first semiconductor layer 111 . The top view shape of the first trench 110 includes a rectangular ring, a polygonal ring, a circular ring, an elliptical ring or an irregular ring, wherein each corner of the rectangle or polygon can be rounded.

如第7圖之剖面圖所示,第二溝槽1101包含一最小寬度D1介於1 μm~80 μm之間,較佳介於2 μm~50 μm之間,更佳介於5 μm~20 μm之間。第二溝槽1101係藉由移除部分的第二半導體層112及活性層113而形成,且第二溝槽1101露出部分第一半導體層111。第二溝槽1101的上視形狀包含矩形或多邊形環狀,其中矩形或多邊形之各角落可以圓弧化。As shown in the cross-sectional view of FIG. 7, the second trench 1101 includes a minimum width D1 between 1 μm~80 μm, preferably between 2 μm~50 μm, more preferably between 5 μm~20 μm between. The second trench 1101 is formed by removing part of the second semiconductor layer 112 and the active layer 113 , and the second trench 1101 exposes part of the first semiconductor layer 111 . The top-view shape of the second groove 1101 includes a rectangle or a polygon ring, wherein each corner of the rectangle or polygon can be rounded.

於發明之一實施例中,半導體結構12包含與發光疊層11相同的結構。例如,半導體結構12包含第一半導體層111、第二半導體層112及活性層113。半導體結構12的上表面12t包含第二半導體層112之一表面。In one embodiment of the invention, the semiconductor structure 12 includes the same structure as the light emitting stack 11 . For example, the semiconductor structure 12 includes a first semiconductor layer 111 , a second semiconductor layer 112 and an active layer 113 . The upper surface 12t of the semiconductor structure 12 includes a surface of the second semiconductor layer 112 .

如第6圖之上視圖及第7圖之剖面圖所示,因為布拉格反射鏡(DBR)20為疊層結構,例如,發光疊層11、電流阻擋層14、透明導電層16、第一接觸電極18或第二接觸電極19等結構,因此當發光元件2經過切割、劈裂製程時,布拉格反射鏡(DBR)20容易因這些具有高度差的結構而在發光元件2的周圍形成破裂面S。當破裂面S延伸至發光疊層11,露出發光疊層11,布拉格反射鏡(DBR)20即喪失保護發光元件2的效果,水氣容易藉由破裂面S進入至發光疊層11的內部。於本發明之一實施例中,為了避免破裂面S延伸至發光疊層11,發光元件2包含半導體結構12位於基板10上,且半導體結構12與發光疊層11之間具有第一溝槽110暴露出的第一半導體層111,藉由第一溝槽110暴露出的第一半導體層111將半導體結構12與發光疊層11分相隔一距離,並且半導體結構12環繞發光疊層11。如第6圖所示,因為布拉格反射鏡(DBR)20的成膜特性,即使發光元件2的周圍有破裂面S,破裂面S會如布拉格反射鏡(DBR)20的第二側面202s所示,停止於半導體結構12、第一溝槽110或第二溝槽1101的轉角處。As shown in the top view of FIG. 6 and the cross-sectional view of FIG. 7, because the Bragg reflector (DBR) 20 is a stacked structure, for example, a light emitting stack 11, a current blocking layer 14, a transparent conductive layer 16, a first contact Electrode 18 or second contact electrode 19 and other structures, so when the light emitting element 2 undergoes cutting and splitting processes, the Bragg reflector (DBR) 20 is likely to form a fracture surface S around the light emitting element 2 due to these structures with height differences . When the rupture surface S extends to the light-emitting stack 11 to expose the light-emitting stack 11 , the Bragg reflector (DBR) 20 loses the effect of protecting the light-emitting element 2 , and water vapor easily enters the interior of the light-emitting stack 11 through the rupture surface S. In one embodiment of the present invention, in order to prevent the rupture surface S from extending to the light emitting stack 11, the light emitting element 2 includes a semiconductor structure 12 located on the substrate 10, and a first trench 110 is provided between the semiconductor structure 12 and the light emitting stack 11 The exposed first semiconductor layer 111 , the first semiconductor layer 111 exposed by the first trench 110 separates the semiconductor structure 12 from the light emitting stack 11 by a distance, and the semiconductor structure 12 surrounds the light emitting stack 11 . As shown in FIG. 6, because of the film-forming properties of the Bragg reflector (DBR) 20, even if there is a cracked surface S around the light-emitting element 2, the cracked surface S will be as shown on the second side 202s of the Bragg reflector (DBR) 20. , stop at the corner of the semiconductor structure 12 , the first trench 110 or the second trench 1101 .

於發明之一實施例中,如第7圖之剖面圖所示,布拉格反射鏡(DBR)20的第二側面202s係與半導體結構12的側表面12s直接連接。換言之,第二側面202s與半導體結構12之上表面12t之間包含一第一銳角,側表面12s與半導體結構12之上表面12t之間包含一第一鈍角,其中第一銳角與第一鈍角為互補。例如,第一銳角介於20度~85度之間,第一鈍角介於95度~160度之間。In one embodiment of the invention, the second side 202s of the Bragg reflector (DBR) 20 is directly connected to the side surface 12s of the semiconductor structure 12 as shown in the cross-sectional view of FIG. In other words, a first acute angle is included between the second side surface 202s and the upper surface 12t of the semiconductor structure 12, and a first obtuse angle is included between the side surface 12s and the upper surface 12t of the semiconductor structure 12, wherein the first acute angle and the first obtuse angle are complementary. For example, the first acute angle is between 20 degrees and 85 degrees, and the first obtuse angle is between 95 degrees and 160 degrees.

於發明之一實施例中,當布拉格反射鏡20之第二側面202s係與半導體結構12之內側表面12ns直接連接時,布拉格反射鏡(DBR)20的第二側面202s與半導體結構12的內側表面12ns之間包含一鈍角介於95度~140度之間,較佳介於100度~130度之間,更佳介於100度~120度之間。In one embodiment of the invention, when the second side 202s of the Bragg reflector 20 is directly connected with the inner surface 12ns of the semiconductor structure 12, the second side 202s of the Bragg reflector (DBR) 20 and the inner surface of the semiconductor structure 12 The interval between 12 ns includes an obtuse angle between 95 degrees to 140 degrees, preferably between 100 degrees to 130 degrees, more preferably between 100 degrees to 120 degrees.

於本發明之一實施例中,發光元件2包含複數個半導體結構12位於發光元件1之一周圍以環繞發光疊層11(圖未示)。複數個半導體結構12藉由第一溝槽110以與發光疊層11相隔離,且兩相鄰之複數個半導體結構12藉由第三溝槽(圖未示)以彼此間隔。複數個半導體結構12與複數個第三溝槽(圖未示)彼此交替排列以增加布拉格反射鏡(DBR)20與發光疊層11及/或半導體結構12之間的附著力,避免布拉格反射鏡(DBR)20自發光疊層11及/或半導體結構12的表面剝離。In one embodiment of the present invention, the light emitting device 2 includes a plurality of semiconductor structures 12 located around one of the light emitting device 1 to surround the light emitting stack 11 (not shown). The plurality of semiconductor structures 12 are separated from the light emitting stack 11 by the first trench 110 , and two adjacent semiconductor structures 12 are separated from each other by the third trench (not shown). A plurality of semiconductor structures 12 and a plurality of third grooves (not shown) are alternately arranged to increase the adhesion between the Bragg reflector (DBR) 20 and the light-emitting stack 11 and/or the semiconductor structure 12, avoiding the Bragg reflector The (DBR) 20 is peeled off from the surface of the light emitting stack 11 and/or the semiconductor structure 12 .

第一溝槽110及第三溝槽各包含最小寬度D介於1 μm~30 μm之間,較佳介於2 μm~14 μm之間,更佳介於5 μm~10 μm之間。第一溝槽110及第三溝槽係藉由移除部分的第二半導體層112及活性層113而形成,且第一溝槽110及第三溝槽露出部分第一半導體層111。第一溝槽110及第三溝槽的上視形狀包含矩形或多邊形環狀,其中矩形或多邊形之各角落可以圓弧化。Each of the first groove 110 and the third groove includes a minimum width D between 1 μm˜30 μm, preferably between 2 μm˜14 μm, more preferably between 5 μm˜10 μm. The first trench 110 and the third trench are formed by removing part of the second semiconductor layer 112 and the active layer 113 , and the first trench 110 and the third trench expose part of the first semiconductor layer 111 . The top view shapes of the first trench 110 and the third trench include a rectangle or a polygon ring, wherein each corner of the rectangle or polygon can be rounded.

於本發明之一實施例中,發光元件2更包含第二溝槽1101位於發光元件2之一最外圍以環繞發光疊層11、複數個半導體結構12及位於複數個半導體結構12之間的第三溝槽(圖未示)。In one embodiment of the present invention, the light-emitting element 2 further includes a second trench 1101 located at the outermost edge of the light-emitting element 2 to surround the light-emitting stack 11, the plurality of semiconductor structures 12, and the first trench 1101 between the plurality of semiconductor structures 12. Three grooves (not shown).

用以分隔複數個半導體結構12之複數個第三溝槽(圖未示)包含相同或不同的最小寬度D。於發明之一實施例中,第三溝槽的最小寬度D係自發光疊層11往半導體結構12之方向上逐漸變大。於發明之另一實施例中,第三溝槽的最小寬度D係自發光疊層11往半導體結構12之方向上逐漸變小。The plurality of third trenches (not shown) for separating the plurality of semiconductor structures 12 include the same or different minimum width D. As shown in FIG. In an embodiment of the invention, the minimum width D of the third trench gradually increases from the light emitting stack 11 to the semiconductor structure 12 . In another embodiment of the invention, the minimum width D of the third trench gradually decreases from the light emitting stack 11 to the semiconductor structure 12 .

於發明之一實施例中,發光元件1或發光元件2更包含一切割道 (圖未示)位於發光元件1或發光元件2之最外側。自發光元件1或發光元件2之一上視觀之,切割道圍繞發光疊層11、半導體結構12及第一溝槽110。切割道係藉由移除第一半導體層11、第二半導體層12及活性層13,以露出基板10之一上表面。切割道的上視形狀包含矩形或多邊形環狀。於一實施例中,所述切割道露出基板10之上表面係為一粗糙面。粗糙面可以為具有不規則形態的表面或具有規則形態的表面,例如具有多個半球形狀的面,具有多個圓錐形狀的面,或者具有多個多邊錐形狀的面。In one embodiment of the invention, the light-emitting element 1 or the light-emitting element 2 further includes a cutting line (not shown) located on the outermost side of the light-emitting element 1 or the light-emitting element 2 . Viewed from one of the light emitting element 1 or the light emitting element 2 , the dicing line surrounds the light emitting stack 11 , the semiconductor structure 12 and the first trench 110 . The dicing line is to expose an upper surface of the substrate 10 by removing the first semiconductor layer 11 , the second semiconductor layer 12 and the active layer 13 . The top-view shape of the cutting line includes a rectangle or a polygon ring. In one embodiment, the top surface of the substrate 10 exposed by the cutting line is a rough surface. The rough surface may be a surface with an irregular shape or a surface with a regular shape, such as a surface with multiple hemispherical shapes, a surface with multiple conical shapes, or a surface with multiple polygonal cone shapes.

第8圖係為依本發明一實施例之發光裝置3之示意圖。將前述實施例中的發光元件1或發光元件2以倒裝晶片之形式安裝於封裝基板51 之第一墊片511、第二墊片512上。第一墊片511、第二墊片512之間藉由一包含絕緣材料之絕緣部53做電性絕緣。倒裝晶片安裝係將與電極墊形成面相對之成長基板側向上設為主要的光取出面。為了增加發光裝置3之光取出效率,可於發光元件1或發光元件2之周圍設置一反射結構54。Fig. 8 is a schematic diagram of a light emitting device 3 according to an embodiment of the present invention. The light-emitting element 1 or light-emitting element 2 in the foregoing embodiments is mounted on the first pad 511 and the second pad 512 of the package substrate 51 in the form of flip chip. The first spacer 511 and the second spacer 512 are electrically insulated by an insulating portion 53 including insulating material. In flip-chip mounting, the side of the growth substrate opposite to the surface where the electrode pads are formed is set upward as the main light extraction surface. In order to increase the light extraction efficiency of the light emitting device 3 , a reflective structure 54 can be provided around the light emitting element 1 or the light emitting element 2 .

第9圖係為依本發明一實施例之發光裝置4之示意圖。發光裝置4為一球泡燈包括一燈罩602、一反射鏡604、一發光模組610、一燈座612、一散熱片614、一連接部616以及一電連接元件618。發光模組610包含一承載部606,以及複數個發光單元608位於承載部606上,其中複數個發光單元608可為前述實施例中的發光元件1、發光元件2或發光裝置3。FIG. 9 is a schematic diagram of a light emitting device 4 according to an embodiment of the present invention. The light emitting device 4 is a bulb lamp including a lampshade 602 , a reflector 604 , a light emitting module 610 , a lamp holder 612 , a heat sink 614 , a connecting portion 616 and an electrical connecting element 618 . The light emitting module 610 includes a carrying portion 606 and a plurality of light emitting units 608 located on the carrying portion 606 , wherein the plurality of light emitting units 608 can be the light emitting element 1 , the light emitting element 2 or the light emitting device 3 in the foregoing embodiments.

本發明所列舉之各實施例僅用以說明本發明,並非用以限制本發明之範圍。任何人對本發明所作之任何顯而易知之修飾或變更皆不脫離本發明之精神與範圍。The various embodiments listed in the present invention are only used to illustrate the present invention, and are not intended to limit the scope of the present invention. Any obvious modifications or changes made by anyone to the present invention will not depart from the spirit and scope of the present invention.

1,2:發光元件 3,4:發光裝置 10:基板 10s:側壁 11:發光疊層 110:第一溝槽 1101:第二溝槽 111:第一半導體層 111s:第一半導體層之側面 111t:第一半導體層之表面 112:第二半導體層 112t:第二半導體層之表面 113:活性層 12:半導體結構 12t:上表面 12s:側表面 12ns:內側表面 120:凹槽 13:第一電流阻擋層 14:電流阻擋層 16:透明導電層 18:第一接觸電極 18a:第一接觸電極墊 18b:第一接觸電極延伸部 19:第二接觸電極 19a:第二接觸電極墊 19b:第二接觸電極延伸部 20:布拉格反射鏡(DBR) 201:第一開口 201s:第一側面 202:第二開口 202s:第二側面 21:第一電極墊 22:第二電極墊 D:最小寬度 D1:最小寬度 S:破裂面 S1:外側壁 S2:內側壁 T1:第一厚度 T2:第二厚度 51:封裝基板 511:第一墊片 512:第二墊片 53:絕緣部 54:反射結構 602:燈罩 604:反射鏡 606:承載部 608:發光單元 610:發光模組 612:燈座 614:散熱片 616:連接部 618:電連接元件 1, 2: Light emitting element 3, 4: Lighting device 10: Substrate 10s: side wall 11: Luminous Lamination 110: the first groove 1101: the second groove 111: the first semiconductor layer 111s: the side of the first semiconductor layer 111t: the surface of the first semiconductor layer 112: the second semiconductor layer 112t: the surface of the second semiconductor layer 113: active layer 12:Semiconductor structure 12t: upper surface 12s: side surface 12ns: inner surface 120: Groove 13: The first current blocking layer 14: Current blocking layer 16: Transparent conductive layer 18: First contact electrode 18a: first contact electrode pad 18b: first contact electrode extension 19: The second contact electrode 19a: Second contact electrode pad 19b: second contact electrode extension 20: Bragg reflector (DBR) 201: first opening 201s: First Side 202: second opening 202s: second side 21: The first electrode pad 22: Second electrode pad D: minimum width D1: minimum width S: rupture surface S1: Outer wall S2: Medial wall T1: first thickness T2: second thickness 51: Package substrate 511: The first gasket 512: second gasket 53: Insulation part 54: Reflection structure 602: lampshade 604: Mirror 606: bearing part 608: Lighting unit 610: Lighting module 612: lamp holder 614: heat sink 616: connection part 618: Electrical connection components

第1圖係本發明一實施例中所揭示之一發光元件1的上視圖。FIG. 1 is a top view of a light emitting element 1 disclosed in an embodiment of the present invention.

第2圖係第1圖之左下部分放大圖。Figure 2 is an enlarged view of the lower left part of Figure 1.

第3圖係第2圖的掃描電子顯微鏡(SEM)立體圖。Fig. 3 is a scanning electron microscope (SEM) perspective view of Fig. 2 .

第4圖係沿著第1圖之切線A-A’的剖面圖。Figure 4 is a sectional view along the tangent line A-A' of Figure 1.

第5圖係沿著第1圖之切線B-B’的剖面圖。Fig. 5 is a sectional view along the tangent line B-B' of Fig. 1.

第6圖係本發明一實施例中所揭示之一發光元件2的上視圖。FIG. 6 is a top view of a light emitting element 2 disclosed in an embodiment of the present invention.

第7圖係沿著第6圖之切線C-C’的剖面圖。Fig. 7 is a sectional view along the tangent line C-C' of Fig. 6.

第8圖係為依本發明一實施例之發光裝置3之示意圖。Fig. 8 is a schematic diagram of a light emitting device 3 according to an embodiment of the present invention.

第9圖係為依本發明一實施例之發光裝置4之示意圖。。FIG. 9 is a schematic diagram of a light emitting device 4 according to an embodiment of the present invention. .

none

1:發光元件 1: Light emitting element

10:基板 10: Substrate

10s:側壁 10s: side wall

11:發光疊層 11: Luminous Lamination

110:第一溝槽 110: the first groove

111:第一半導體層 111: the first semiconductor layer

111t:第一半導體層之表面 111t: the surface of the first semiconductor layer

112:第二半導體層 112: the second semiconductor layer

112t:第二半導體層之表面 112t: the surface of the second semiconductor layer

113:活性層 113: active layer

12:半導體結構 12:Semiconductor structure

12t:上表面 12t: upper surface

12s:側表面 12s: side surface

12ns:內側表面 12ns: inner surface

120:凹槽 120: Groove

13:第一電流阻擋層 13: The first current blocking layer

14:電流阻擋層 14: Current blocking layer

16:透明導電層 16: Transparent conductive layer

18:第一接觸電極 18: First contact electrode

19:第二接觸電極 19: The second contact electrode

20:布拉格反射鏡(DBR) 20: Bragg reflector (DBR)

201:第一開口 201: first opening

201s:第一側面 201s: First Side

202:第二開口 202: second opening

202s:第二側面 202s: second side

21:第一電極墊 21: The first electrode pad

22:第二電極墊 22: Second electrode pad

S1:外側壁 S1: Outer wall

S2:內側壁 S2: Medial wall

Claims (10)

一發光元件,包含:一基板;一發光疊層位於該基板上,該發光疊層包含一第一半導體層,一第二半導體層,及一活性層位於該第一半導體層及該第二半導體層之間,且該第二半導體層包含一上表面;一第一溝槽環繞該發光疊層並露出該第一半導體層之一表面,其中,該第一溝槽的上視形狀包含矩形環狀、多邊形環狀、圓形環狀、橢圓形環狀或不規則環狀,且該第一溝槽包含一最小寬度D介於1μm~5μm之間;以及一布拉格反射鏡覆蓋該發光疊層及該第一溝槽,其中,該布拉格反射鏡包含一厚度位於該發光疊層上,位於該第一溝槽上之該布拉格反射鏡包含一第一厚度位於該第二半導體層之該上表面之上及一第二厚度位於該第二半導體層之該上表面之下,其中該厚度大於該第一厚度,該厚度大於該第二厚度,且該第二厚度小於2μm。 A light-emitting element, comprising: a substrate; a light-emitting stacked layer located on the substrate, the light-emitting stacked layer comprising a first semiconductor layer, a second semiconductor layer, and an active layer located on the first semiconductor layer and the second semiconductor layer between the layers, and the second semiconductor layer includes an upper surface; a first trench surrounds the light emitting stack and exposes a surface of the first semiconductor layer, wherein the top view shape of the first trench includes a rectangular ring shape, polygonal ring, circular ring, elliptical ring or irregular ring, and the first groove includes a minimum width D between 1 μ m ~ 5 μ m; and a Bragg mirror covering The light-emitting stack and the first trench, wherein the Bragg reflector includes a thickness on the light-emitting stack, and the Bragg reflector on the first trench includes a first thickness on the second semiconductor layer. above the upper surface and under the upper surface of the second semiconductor layer, wherein the thickness is greater than the first thickness, the thickness is greater than the second thickness, and the second thickness is less than 2 μm. 如申請專利範圍第1項所述的發光元件,其中該第一厚度大於2μm。 The light-emitting element described in claim 1, wherein the first thickness is greater than 2 μm. 如申請專利範圍第1項所述的發光元件,包含一第一接觸電極墊接觸該第一半導體層並電連接至該第一半導體層;以及一第二接觸電極墊位於該第二半導體層上以電連接至該第二半導體層,其中該第一接觸電極墊之一上表面係低於該第二半導體層之該上表面。 The light-emitting element as described in item 1 of the patent scope of the application, comprising a first contact electrode pad contacting the first semiconductor layer and electrically connected to the first semiconductor layer; and a second contact electrode pad located on the second semiconductor layer To be electrically connected to the second semiconductor layer, wherein an upper surface of the first contact electrode pad is lower than the upper surface of the second semiconductor layer. 如申請專利範圍第1項所述的發光元件,包含一第一接觸電極墊接觸該第一半導體層並電連接至該第一半導體層;以及一第二接觸電極墊位於 該第二半導體層上以電連接至該第二半導體層,其中該第一接觸電極墊之一上表面係凸出於該第二半導體層之該上表面。 The light-emitting element as described in item 1 of the patent scope of the application, comprising a first contact electrode pad contacting the first semiconductor layer and electrically connected to the first semiconductor layer; and a second contact electrode pad located at The second semiconductor layer is electrically connected to the second semiconductor layer, wherein an upper surface of the first contact electrode pad protrudes from the upper surface of the second semiconductor layer. 如申請專利範圍第3項或第4項所述的發光元件,其中該布拉格反射鏡包含一第一開口露出該第一接觸電極墊以及一第二開口露出該第二接觸電極墊,該第一開口包含一第一開口直徑小於該第一接觸電極墊之一直徑,且該第二開口包含一第二開口直徑小於該第二接觸電極墊之一直徑。 The light-emitting element as described in item 3 or item 4 of the scope of the patent application, wherein the Bragg reflector includes a first opening exposing the first contact electrode pad and a second opening exposing the second contact electrode pad, the first The opening includes a first opening diameter smaller than a diameter of the first contact electrode pad, and the second opening includes a second opening diameter smaller than a diameter of the second contact electrode pad. 如申請專利範圍第1項所述的發光元件,其中該布拉格反射鏡的整體厚度可以是1~8μm。 The light-emitting element as described in item 1 of the scope of the patent application, wherein the overall thickness of the Bragg reflector can be 1-8 μm. 如申請專利範圍第1項所述的發光元件,包含一包含SiO2之介質層位於該布拉格反射鏡之下,且具有一厚度位於0.2μm~1μm之間。 The light-emitting element described in item 1 of the scope of the patent application includes a dielectric layer comprising SiO 2 located under the Bragg reflector, and has a thickness between 0.2 μm and 1 μm. 如申請專利範圍第3項或第4項所述的發光元件,包含一電流阻擋層位於該第二接觸電極墊之下,其中該電流阻擋層包含一圓心與該第二接觸電極墊之一圓心互不重疊。 The light-emitting element as described in item 3 or item 4 of the scope of the patent application, comprising a current blocking layer located under the second contact electrode pad, wherein the current blocking layer includes a circle center and a circle center of the second contact electrode pad do not overlap each other. 如申請專利範圍第5項所述的發光元件,包含一第一電極墊以及一第二電極墊分別覆蓋該第一開口及該第二開口,其中該第一電極墊以及該第二電極墊各包括一凹陷部及一凸出部。 The light-emitting element as described in item 5 of the scope of the patent application includes a first electrode pad and a second electrode pad covering the first opening and the second opening respectively, wherein the first electrode pad and the second electrode pad are respectively It includes a concave part and a protruding part. 如申請專利範圍第9項所述的發光元件,其中該第一電極墊與該第二電極墊之間包含一間隔為10μm以上。 The light-emitting device as described in claim 9 of the patent claims, wherein there is an interval between the first electrode pad and the second electrode pad that is more than 10 μm.
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