TWI828116B - Semiconductor device - Google Patents

Abstract

A semiconductor device is provided, including: a first-type semiconductor structure, an active structure, a second-type semiconductor structure, an insulating structure, a recess and a metal structure. The first-type semiconductor structure has a first area, a second area and a side wall. The active structure is disposed on the first-type semiconductor structure. The second-type semiconductor structure is disposed on the active layer. The insulating structure covers the first area of the first-type semiconductor structure and has a first opening. The recess is formed in the first-type semiconductor structure at a position corresponding to the first opening. The metal structure includes a first metal filling in the recess.

Description

Semiconductor components

The present disclosure relates to a semiconductor device, and in particular to a semiconductor device having good ohmic contact.

Semiconductor components are used in a wide range of applications, and research and development on related materials continues. For example, III-V semiconductor materials containing III and V elements can be used in various semiconductor devices such as light-emitting wafers (such as light-emitting diodes or laser diodes), light-absorbing wafers (photodetectors or Solar cells) or non-luminous wafers (such as power components of switches or rectifiers), can be used in lighting, medical, display, communications, sensing, power systems and other fields. With the development of science and technology, there are still many technical research and development needs for semiconductor components. Although existing semiconductor devices have generally met general requirements, they are not satisfactory in all aspects and further improvements are still needed.

Embodiments of the present disclosure provide a semiconductor device. The semiconductor element includes a first-type semiconductor structure, an active structure, a second-type semiconductor structure, an insulation structure, a groove and a metal structure. The first type semiconductor layer includes a first region, a second region and a first sidewall. The active structure is located on the second region of the first-type semiconductor structure. The second type semiconductor structure is located on the active structure. The insulation structure covers the first region of the first-type semiconductor structure and has a first opening. The groove is located in the first type semiconductor structure and corresponds to the first opening. The metal structure includes a first metal layer, and the first metal layer fills the groove.

The following disclosure provides numerous embodiments, or examples, for implementing different elements of the provided subject matter. Specific examples of each component and its configuration are described below to simplify the description of the embodiments of the present disclosure. Of course, these are only examples and are not intended to limit the embodiments of the present disclosure. For example, if the description mentions that a first element is formed on a second element, it may include an embodiment in which the first and second elements are in direct contact, or may include an additional element formed between the first and second elements. , so that they are not in direct contact. In addition, embodiments of the present disclosure may repeat reference numbers and/or letters in various examples. Such repetition is for the sake of simplicity and clarity and is not intended to represent the relationship between the various embodiments and/or configurations discussed.

Furthermore, words relative to space may be used, such as "under", "below", "lower", "above", "higher" and other similar words, for the convenience of description. The relationship between one component(s) or feature(s) and another(s) component(s) or feature(s) in the diagram. Spatially relative terms are used to encompass different orientations of equipment in use or operation and the orientation depicted in the drawings. When the device is turned at a different orientation (rotated 90 degrees or at any other orientation), the spatially relative adjectives used therein will also be interpreted in accordance with the rotated orientation.

FIGS. 1 to 5 are schematic cross-sectional views of the manufacturing process of the semiconductor device 10 according to an embodiment of the present disclosure. In the various schematic diagrams and illustrative embodiments described below, similar reference numbers are used to represent similar elements. The semiconductor device 10 of the present disclosure may include a light-emitting chip (such as a light-emitting diode or a laser diode), a light-absorbing chip (such as a photodetector or a solar cell), or a non-light-emitting chip (such as a switch or rectifier). power components). In the embodiment of the present disclosure, the length of the semiconductor element 10 is no more than 150 microns, preferably in the range of 10 microns to 150 microns, or 10 microns to 60 microns, or 60 microns to 150 microns, and the width is no more than 100 microns, preferably The preferred range is 5 microns to 100 microns, or 5 microns to 30 microns, or 30 microns to 75 microns.

Referring to Figure 1, a substrate 100 is provided, and a first-type semiconductor structure 102, an active structure 104, and a second-type semiconductor structure 106 are sequentially formed on the substrate 100, and can be performed by, for example, a dry etching process, a wet etching process, Or a combination of the above is used to etch part of the first-type semiconductor structure 102, the active structure 104, and the second-type semiconductor structure 106 to expose a part of the first-type semiconductor structure 102. As shown in FIG. 1 , the first type semiconductor structure 102 includes a first region and a second region. In this embodiment, in a cross-sectional view, the first type semiconductor structure 102 includes three first regions 110a1, 110a2, 110a3 and two second regions 110b1, 110b2. The first area 110a1 is surrounded by the second areas 110b1 and 110b2, and the first area 110a1 is located between the other two first areas 110a2 and 110a3. The active structure 104 and the second-type semiconductor structure 106 are located in the second regions 110b1 and 110b2 and are not located in the first regions 110a1, 110a2 and 110a3.

In some embodiments, substrate 100 may include insulating materials, semiconductor materials, or both. The insulating material may include, for example, the following materials: sapphire, diamond, glass, quartz, or AlN. Semiconductor materials may include, for example, the following materials: gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium phosphide (GaP), gallium arsenic phosphide (GaAsP), zinc oxide (ZnO), selenium Zinc (ZnSe), gallium nitride (GaN), aluminum nitride (AlN), lithium gallate (LiGaO ₂ ), lithium aluminate (LiAlO ₂ ), germanium (Ge) or silicon (Si). In some embodiments, substrate 100 is a gallium arsenide substrate. In some embodiments, the thickness of the substrate 100 may range from 50 μm to 1300 μm.

In the embodiment of the present disclosure, the first type semiconductor structure 102, the second type semiconductor structure 106, and the active structure 104 include a single layer or multiple layers. The first type semiconductor structure 102, the second type semiconductor structure 106, and the active structure 104 may respectively include III-V semiconductor materials, such as aluminum (Al), gallium (Ga), arsenic (As), phosphorus (P), indium ( In), or nitrogen (N). Specifically, in the embodiment of the present disclosure, the above-mentioned III-V semiconductor material may be a binary compound semiconductor (such as GaAs, GaP, or GaN), a ternary compound semiconductor (such as InGaAs, AlGaAs, InGaP, AlInP, InGaN, or AlGaN), or quaternary compound semiconductors (such as AlGaInAs, AlGaInP, AlInGaN, InGaAsP, InGaAsN, or AlGaAsP). In some embodiments, the thickness of the first-type semiconductor structure 102 may be between 1.5 μm and 4 μm. In some embodiments, the thickness of the second-type semiconductor structure 106 may be between 0.1 μm and 2 μm. In some embodiments, the thickness of active structure 104 may be between 0.01 μm and 1.0 μm. The first type semiconductor structure 102 or the second type semiconductor structure 106 may include a distributed bragg reflector structure (DBR), which is formed by alternately stacking two or more semiconductor materials with different refractive indexes.

In some embodiments, the first type semiconductor structure 102, the second type semiconductor structure 106 and the active structure 104 can be formed by the following epitaxial growth process, such as metal-organic chemical vapor deposition, MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE) or liquid-phase epitaxy (LPE), vapor phase epitaxy ( vapor phase epitaxy (VPE), or a combination of the above.

In some embodiments, the first type semiconductor structure 102 may be formed by in-situ doping during epitaxial growth and/or by implanting with dopants after epitaxial growth. Doping of the second type semiconductor structure 106 . The first type semiconductor structure 102 may include a first dopant to have a first conductivity type, and the second type semiconductor structure 106 may include a second dopant to have a second conductivity type. The first type semiconductor structure 102 and the second type semiconductor structure 106 have different conductivity types, that is, the first conductivity type and the second conductivity type are different. The first conductivity type is, for example, p-type and the second conductivity type is, for example, n-type. The first conductivity type, for example, is n-type and the second conductivity type is, for example, p-type. When the semiconductor device 10 is a light-emitting device, the first-type semiconductor structure 102 and the second-type semiconductor structure 106 respectively provide holes and electrons or holes, and the electrons or holes are combined in the active structure 104 to emit light. The first dopant or the second dopant may include silicon, tellurium, carbon, beryllium, magnesium).

In some embodiments, the semiconductor device 10 may include a multiple quantum well (MQW), a single-quantum well (SQW), a homojunction, or a heterojunction.

When the semiconductor device 10 is a light-emitting device and operates on the semiconductor device 10 , the active structure 104 can emit light. The light emitted by the active structure 104 includes visible light or invisible light. The wavelength of the light emitted by the semiconductor element 10 depends on the material composition of the active structure 104 . For example, when the material of the active structure 104 includes the InGaN series, it can emit blue light or deep blue light with a peak wavelength of 400 nanometers to 490 nanometers, or a peak wavelength of 490 nanometers to 550 nanometers. Green light; when the material of the active structure 104 includes the AlGaN series, it can emit ultraviolet light with a peak wavelength of 250 nanometers to 400 nanometers; when the material of the active structure 104 includes the InGaAs series, InGaAsP series, AlGaAs series, or AlGaInAs series , can emit infrared light with a peak wavelength of 700 nanometers to 1700 nanometers; when the material of the active structure 104 includes InGaP series or AlGaInP series, can emit red light with a peak wavelength of 610 nanometers to 700 nanometers, or peak wavelength Yellow light with a wavelength of 530 nanometers to 600 nanometers.

Referring to FIG. 2 , the insulating structure 108 compliantly covers the upper surface of the structure shown in FIG. 1 . In other words, the insulating structure 108 compliantly covers the first-type semiconductor structure 102 , the active structure 104 and the second-type semiconductor structure 106 . Although the insulating structure 108 is only shown as one layer in the figure, the insulating structure 108 may be more than one film layer. In some embodiments, the insulating structure 108 may be formed of non-conductive materials, including organic materials, such as benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), and acrylic resin (Acrylic resin). Resin), cyclic olefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide), fluorine Carbon polymer (Fluorocarbon Polymer), or inorganic materials, such as silicone, glass, or dielectric materials, such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ). In an embodiment of the present disclosure, the insulating structure 108 is an insulating reflective structure, allowing the semiconductor element 10 to emit light toward the substrate 100 to reduce light loss on the electrode side, thereby increasing the light output of the semiconductor element 10 . In one embodiment, the insulating structure 108 may include a distributed bragg reflector structure (DBR), which is formed by alternately stacking two or more insulating materials with different refractive indexes, for example, by stacking SiO ₂ /TiO ₂ , SiO ₂ /Nb ₂ O ₅ and other layers to form an insulating reflective layer with high reflectivity.

In some embodiments, a deposition process may be used to form the insulating structure 108 . The above-mentioned deposition processes include physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), and atomic layer deposition. deposition, ALD) or a combination thereof.

Referring to FIG. 3, the insulating structure 108 located in the first region 110a1 and the second region 110b1 can be etched through an etching process to form the first opening 112 and the second opening 114, exposing the first type semiconductor structure 102 and the second type semiconductor structure 102. Semiconductor structure 106. The process used to etch the insulating structure 108 may include a dry etching process, a wet etching process, or a combination thereof. For example, the wet etching process may use an acidic solution or an alkaline solution. The acidic solution may include a solution containing hydrofluoric acid, phosphoric acid, nitric acid, acetic acid or a combination thereof; the alkaline solution may include a solution containing potassium hydroxide, ammonia, hydrogen peroxide or a combination thereof. For example, the dry etching process may include plasma etching (PE), reactive ion etching (RIE), and inductively coupled plasma reactive ion etching (ICP-RIE). The gas for the etching reaction may include oxygen-containing gas, fluorine-containing gas, chlorine-containing gas, boron-containing gas, argon-containing gas, and/or a combination of the above.

Next, referring to FIG. 4 , the first type semiconductor structure 102 in the first region 110 a 1 is further etched through the first opening 112 to form a groove 116 , which corresponds to the position of the first opening and overlaps the first opening. . The first type semiconductor structure 102 has a first top surface 121 and a second top surface 122 . The first top surface 121 is the bottom of the groove and the second top surface 122 is covered by the insulating structure 108 . The first top surface 121 is closer to the substrate 100 than the second top surface 122 . In one embodiment, the groove 116 has a depth D greater than 0.001 μm or between 0.001 μm and 0.1 μm.

In some embodiments, as shown in Figures 3 and 4, a two-stage dry etching method can be used. The first opening 112 and the second opening 114 are formed in the first stage of the etching process, and then the second stage of etching is used. The process forms grooves 116 . Specifically, the first stage of the etching process may be dry etching to etch part of the insulating structure 108 to form the first opening 112 and the second opening 114 . The second stage of the etching process is also dry etching, and a portion of the first-type semiconductor structure 102 and the by-products produced in the first stage of the etching process are etched to form the groove 116 . The reactive gas in the first stage of the etching process is different from the reactive gas in the second stage of the etching process. In other embodiments, the dry etching method may include one or more stages of process, for example, three or more stages of etching process.

In one embodiment, a contact layer (not shown) may be formed on the second type semiconductor structure 106, and then, as shown in FIG. 2, an insulating structure 108 covers the contact layer. The contact layer may be transparent and include metal oxide (eg, ITO) or semiconductor material (eg, GaAs or InGaAs). As shown in FIG. 3 , during the step of performing an etching process to etch the insulating structure 108 located in the first region 110a1 and the second region 110b1 to form the first opening 112 and the second opening 114 , part of the contact layer will be etched.

Referring to FIG. 5 , the first metal structure 118 is filled in the groove 116 and the first opening 112 , and the second metal structure 119 is filled in the second opening 114 . FIG. 6 is a schematic top view of the semiconductor device 10 , and FIG. 5 is a schematic cross-sectional view along line I-I in FIG. 6 .

As shown in FIG. 5 , the first metal structure 118 and the second metal structure 119 cover part of the top surface of the insulation structure 108 . In one embodiment, each of the first metal structure 118 and the second metal structure 119 may include a metal material, such as germanium (Ge), beryllium (Be), zinc (Zn), chromium (Cr), tungsten (W), gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), indium (In), tin (Sn), nickel (Ni), copper (Cu) and other metals or alloys of the above materials; first metal The structure 118 and the second metal structure 119 may be composed of multiple layers, for example, may include a Cr/Au layer, a Cr/Cu layer, a Ni/Au layer, a Ti/Au layer, a Ti/Cu layer, and a Cr/Pt/Au layer. , Ni/Pt/Au layer, Ti/Pt/Au layer, Cr/Ti/Pt/Au layer, Au/Be layer, Cr/Ti/Pt/Ni/Au/Sn layer, Cr/Ti/Pt/Ni/ Au/In layer, Au/GeAu/Au layer or Cr/Al/Ti/Ni/Au layer.

As shown in FIG. 5 , the insulation structure 108 has a side wall 1081 and a side wall 1082 , and the side wall 1081 is closer to the groove 116 than the side wall 1082 . The first type semiconductor structure 102 has a sidewall 120 defining the groove 116 and a sidewall 1081 defining the first opening 112 . The sidewall 120 of the first type semiconductor structure 102 and the sidewall 1081 of the insulating structure 108 have a first tilt angle θ1 and a second tilt angle θ2 respectively. In some embodiments, the first tilt angle θ1 is different from the second tilt angle θ2 , that is, the first slope of the side wall 120 is different from the second slope of the side wall 1081 . In some embodiments, the first tilt angle θ1 is greater than the second tilt angle θ2 (the first slope is greater than the second slope), which can help the first metal structure 118 to connect with the first-type semiconductor structure 102 when filling the groove 116 . Adhesion and coverage. In an embodiment, the first tilt angle θ1 may range from 20 to 80 degrees. If the first tilt angle θ1 is greater than 80 degrees, the coverage of the first metal structure 118 in the groove 116 may be poor, which may cause the semiconductor device 10 to fail to conduct smoothly or cause reliability problems during operation; if If the first tilt angle θ1 is less than 20 degrees, the process yield may be poor. On the contrary, for the second tilt angle θ2 (second slope), a smaller second tilt angle θ2 (ie, a smaller second slope) can make the first metal structure 118 have a smaller shape in the first opening 112 . Excellent adhesion and coverage. In an embodiment, the second tilt angle θ2 may range from 10 to 70 degrees. If the second tilt angle θ2 is less than 10 degrees, the process yield may be poor; if the second tilt angle θ2 is greater than 70 degrees, the first metal structure 118 has poor coverage with the insulating structure 108 in the first opening 112 , and As a result, the semiconductor device 10 may not conduct smoothly or the device reliability may fail during operation.

In this embodiment, the first metal structure 118 includes a first metal layer 118a, a second metal layer 118b, and a third metal layer 118c in sequence, and their respective average widths are Wa<Wb<Wc. The first metal layer 118a fills the groove 116, is formed on the first-type semiconductor structure 102, and directly contacts the bottom and sidewalls of the groove 116 (ie, directly contacts the sidewalls 120 and the first top surface 121 of the first-type semiconductor structure 102). . The second metal layer 118b is formed on the first metal layer 118a and fills the first opening 112 and is in direct contact with the sidewall 1081 of the insulation structure 108 . The third metal layer 118c is formed on the second metal layer 118b and is in direct contact with the sidewall 1082 of the insulating structure 108. The arrangement of the groove 116 can increase the contact area between the first metal layer 118a and the first-type semiconductor structure 102, thereby reducing the forward voltage (Vf) and improving device performance. Similarly, the second metal structure 119 may include a first metal layer 119a, a second metal layer 119b, and a third metal layer 119c in sequence, as shown in FIG. 5 .

In some embodiments, the first metal layer 118a/119a, the second metal layer 118b/119b and the third metal layer 118c/119c each include different metal materials. The first metal layer 118a/119a may be made of materials suitable for forming ohmic contact with the semiconductor, such as Cr, Ti, Ni, BeAu, and GeAu. The second metal layer 118b/119b can be made of metal material and has a reflective function, such as Pt, Al, Ti, Ni, TiW, and Au. The third metal layer 118c/119c may be made of conductive materials suitable for external connections, such as Au, AuSn, Sn, Sn alloy, In, Cu, and Ni. In one embodiment, each of the first metal structure 118 and the second metal structure 119 may be a three-layer structure composed of Cr/Pt/Au layers. However, it should be understood that in other embodiments, the first metal structure 118 and the second metal structure 119 can each be a single-layer structure, a double-layer structure, or a multi-layer structure of three or more layers, and the materials of each film layer can be selected. Materials used in the above-mentioned first metal layer, second metal layer and third metal layer or combinations thereof.

In one embodiment, the second metal structure 119 and the first metal structure 118 can be filled in the first opening 112 and the second opening 114 respectively in the same or different deposition processes. In some embodiments, the thickness T of the first metal layer 118a may range from 50Å to 500Å. The thickness of the second metal layer 118b may range from 50Å to 1000Å. The thickness of the third metal layer 118c may be between 0.1 μm and 3 μm. In some embodiments, the thickness of the first metal layer 119a may be between 50Å and 500Å. The thickness of the second metal layer 119b may range from 50Å to 1000Å. The thickness of the third metal layer 119c may be between 0.1 μm and 3 μm. In one embodiment, the thickness T of the first metal layer 118a is smaller than that of the second metal layer 118b, and the thickness T of the second metal layer 118b is smaller than that of the third metal layer 118c. In detail, the first metal layers 118a and 119a have a thin thickness, which can increase the light transmittance of the first metal layers 118a and 119a, and the light emitted by the active structure 104 can pass through the first metal layers 118a and 119a and be The second metal layers 118b, 119b are reflective. Since the second metal layers 118b and 119b serve as reflective layers, they need to have a certain thickness that is greater than the thickness of the first metal layers 118a and 119a. The third metal layers 118c and 119c are used to connect to external circuits. A thicker thickness can increase the bonding yield of the semiconductor element 10 and the external circuit, thereby improving the optoelectronic characteristics of the semiconductor element 10.

In some embodiments, the ratio of the thickness T of the first metal layer 118a to the depth D of the groove 116 is between 0.5-2. In one embodiment, as shown in FIG. 5 , the thickness T of the first metal layer 118 a is greater than the depth D of the groove 116 . In one embodiment, the ratio of the thickness T of the first metal layer 118 a to the depth D of the groove 116 is greater than 1.0 and less than or equal to 2.0. In this embodiment, the first metal layer 118a fills the groove 116, is in direct contact with the sidewall 120 of the first-type semiconductor structure 102, and covers a portion of the sidewall 1081 of the insulating structure 108, but does not cover the sidewall 1082.

Figure 7 is a schematic cross-sectional view of a semiconductor device 10' according to another embodiment of the present disclosure. The main difference from Figure 5 is that the thickness T of the first metal layer 118a is equal to the depth D of the groove 116, and the first metal layer 118a only fills the groove 116, that is, the ratio of the thickness T of the first metal layer 118a to the depth D of the groove 116 is equal to 1.0.

Figure 8 is a schematic cross-sectional view of a semiconductor device 10'' according to another embodiment of the present disclosure. The main difference from Figure 5 is that the thickness T of the first metal layer 118a is less than the depth D of the groove 116, and the second metal layer Layer 118b fills recess 116 and is in direct contact with sidewall 120. That is, the ratio of the thickness T of the first metal layer 118 a to the depth D of the groove 116 is greater than or equal to 0.5 and less than 1.0.

FIG. 9 is a schematic top view of a semiconductor device 20 according to another embodiment of the present disclosure. Semiconductor element 20 has a similar structure to semiconductor element 10 . In this embodiment, the shape of the semiconductor device 20 may be a square or a rectangle and includes two short sides S1 and S2 and two long sides L1 and L2. A short side center line SC passes through the center of the two short sides S1 and S2 to divide the semiconductor element 20 into an upper half and a lower half; a long side center line LC passes through the center of the two long sides L1 and L2 to divide the semiconductor element 20 into an upper half and a lower half. 20 is divided into left and right halves. A left long side line LL is located between the long side center line LC and the short side S1, and divides the left half into two equal parts; a right long side line LR is located between the long side center line LC and the short side S2, and divides the right half Part into two equal parts. The first opening 112 , the groove 116 and the first metal structure 118 are disposed on the left half of the semiconductor device 20 , and the second opening 114 and the second metal structure 119 are disposed on the right half of the semiconductor device 20 . When the first opening 112, the groove 116 or the first metal structure 118 is circular or square in top view, its center or center is set at the short side center line SC or/and the left long side line LL. In other words, the first opening 112. The center or center of the groove 116 or the first metal structure 118 overlaps with the short side center line SC or/and the left long side line LL. When the shape of the second opening 114 or the second metal structure 119 is circular or square, its center or center is set on the short side center line SC or/and the right long side line LR. In other words, the second opening 114 or the second The center or center of the metal structure 119 overlaps with the short side center line SC or/and the right long side line LR. The center of the circle or the center of the first opening 112 or the first metal structure 118 is symmetrical or mirrored with the center of the circle or the center of the second opening 114 or the second metal structure 119 respectively relative to the long side centerline LC. In one embodiment, the left long side line LL, the long side center line LC and the right long side line LR divide the long side into equal quarters.

In summary, the embodiments of the present disclosure can improve the contact between the metal and the semiconductor by further etching part of the semiconductor layer to form a groove, so that the metal structure is directly in contact with the sidewalls of the semiconductor layer exposed in the groove. Electrical contact to improve component voltage abnormalities to maintain product performance. It should be understood that not all advantages have necessarily been discussed here, not all embodiments are required to possess specific advantages, and other embodiments may provide different advantages.

The components of several embodiments are summarized above so that those with ordinary skill in the technical field to which the present invention belongs can more easily understand the concepts of the disclosed embodiments. Those with ordinary skill in the technical field of the present invention should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and/or advantages as the embodiments introduced here. Those with ordinary skill in the technical field to which the present invention belongs should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present invention, and they can be used without departing from the spirit and scope of the present invention. Make all kinds of changes, substitutions and substitutions.

10, 10’, 10”: semiconductor components

100:Base

102: Type 1 semiconductor structure

104:Active structure

106: Type 2 semiconductor structure

108:Insulation structure

112:First opening

114:Second opening

116: Groove

118:First metal structure

119: Second metal structure

118a, 119a: first metal layer

118b, 119b: second metal layer

118c, 119c: third metal layer

120:Side wall

121: First top surface

122: Second top surface

1081-1082: Side wall

110a1, 110a2, 110a3: first area

110b1, 110b2: Second area

20:Semiconductor components

θ1-θ2: tilt angle

Wa-Wc: Width

D: Depth

T:Thickness

S1, S2: short side

L1, L2: Long side

SC: short side center line

LC: long side center line

LL: left long side line

LR: right long border

Embodiments of the present disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are for illustration only. In fact, the dimensions of various elements may be arbitrarily enlarged or reduced to clearly illustrate the features of the embodiments of the present disclosure. FIGS. 1 to 5 are schematic cross-sectional views of a semiconductor device manufacturing process according to an embodiment of the present disclosure. FIG. 6 is a schematic top view of a semiconductor device according to an embodiment of the present disclosure. FIG. 7 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. FIG. 8 is a schematic cross-sectional view of a semiconductor device according to yet another embodiment of the present disclosure. FIG. 9 is a schematic top view of a semiconductor device according to another embodiment of the present disclosure.

104: Active structure 106: Type 2 Semiconductor Structure 110a1, 110a2, 110a3: First area 110b1, 110b2: Second area 112: First opening 116: Groove 118: First Metal Structure 119: Second metal structure 118a, 119a: first metal layer 118b, 119b: Second metal layer 118c, 119c: third metal layer 120: side wall 121: First top surface 122: Second top surface 1081, 1082: Side wall θ1-θ2: tilt angle Wa-Wc: Width D: Depth T: Thickness

Claims (10)

A semiconductor element includes: a first-type semiconductor structure including a first region, a second region and a first sidewall; an active structure located on the second region of the first-type semiconductor structure; a second A type semiconductor structure is located on the active structure; an insulating structure covers the first region of the first type semiconductor structure and has a first opening; a groove is located in the first type semiconductor structure and corresponds to the first opening. an opening; and a metal structure including a first metal layer, the first metal layer filling the groove; wherein the first type semiconductor structure has a first sidewall defining the groove, the first metal layer filling the groove The groove is in direct contact with the first side wall. The semiconductor device of claim 1, wherein the metal structure further includes a second metal layer, the second metal layer is formed on the first metal layer and has an average width greater than the first metal layer. The semiconductor device of claim 2, wherein the metal structure further includes a third metal layer formed on the second metal layer and having a width greater than the second metal layer. The semiconductor device of claim 3, wherein the first metal layer, the second metal layer and the third metal layer each include different metal materials. The semiconductor device of claim 1, wherein the metal structure further includes A second metal layer fills the groove and is in direct contact with the first side wall. The semiconductor device of claim 1, wherein the metal structure further includes a second metal layer, and the thickness of the first metal layer is smaller than the thickness of the second metal layer. The semiconductor device of claim 1, wherein the groove has a depth, the first metal layer has a thickness, and a ratio of the thickness to the depth is between 0.5-2. The semiconductor device of claim 1, wherein the insulating structure has a second sidewall and a third sidewall, the second sidewall is closer to the groove than the third sidewall, and the first metal layer covers the second sidewall. The semiconductor device of claim 1, wherein the insulating structure has a second sidewall, the first sidewall has a first slope, the second sidewall has a second slope, and the first slope is different from the second slope. The semiconductor device of claim 9, wherein the first slope is greater than the second slope.

Images