TWI807850B - Light-emitting device - Google Patents

Abstract

A light-emitting device includes a substrate including a surface; a first light-emitting unit and a second light-emitting unit formed on the substrate, the irst light-emitting unit and the second light-emitting unit respectively includes a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor laeyr and the second semiconductor layer; a trench formed between the first light-emitting unit and the second light-emitting unit, exposing the surface of the substrate; a first surrounding part formed on the first light-emitting unit, surrounding the first light-emitting unit and exposing the first semiconductor layer of the first light-emitting unit; a second surrounding part formed on the second light-emitting unit, surrounding the second light-emitting unit and exposing the first semiconductor layer of the second light-emitting unit; a first insulating layer including a first opening on the first surrounding part and a second opening on the second semiconductor layer of the second light-emitting unit; and one or a plurality of connecting electrodes respectively includes a first connecting end on the first light-emitting unit and connected to the first semiconductor layer formed in the first opening, a second connecting end on the second light-emitting unit and connected to the second semiconductor layer of the second light-emitting unit, and a third connecting end formed in the trench to connect the first connecting end and the second connecting end.

Description

Light emitting element

The present invention relates to a light-emitting element, and in particular to a light-emitting element, which includes a plurality of light-emitting units and one or a plurality of connecting electrodes located between the plurality of light-emitting units.

Light-emitting diode (Light-Emitting Diode, LED) is a solid-state semiconductor light-emitting element, which has the advantages of low power consumption, low heat generation, long working life, shockproof, small size, fast response and good optoelectronic characteristics, such as stable light-emitting wavelength. Therefore, light-emitting diodes are widely used in household appliances, equipment indicator lights, and optoelectronic products.

A light-emitting element, comprising a base plate with a surface; a first light-emitting unit and a second light-emitting unit located on the base plate, the first light-emitting unit and the second light-emitting unit each comprising a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; a trench located between the first light-emitting unit and the second light-emitting unit, exposing the surface of the substrate; a first surrounding portion located on the first light-emitting unit, surrounding the first light-emitting unit and exposing the first semiconductor layer located on the first light-emitting unit; a second surrounding portion located on the second light-emitting unit, surrounding the second light-emitting unit and exposing the first semiconductor layer located on the second light-emitting unit a first insulating layer includes a first opening located on the first surrounding portion of the first light emitting unit and a second opening located on the second semiconductor layer of the second light emitting unit; and one or a plurality of connection electrodes each include a first connection terminal located on the first light emitting unit and connected to the first semiconductor layer located in the first opening, a second connection terminal located on the second light emitting unit and connected to the second semiconductor layer located in the second light emitting unit, and a third connection terminal located in the trench to connect the first connection terminal and the second connection terminal.

A light-emitting element, comprising a base plate with a surface; a first light-emitting unit and a second light-emitting unit located on the base plate, the first light-emitting unit and the second light-emitting unit each comprising a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; a trench located between the first light-emitting unit and the second light-emitting unit, exposing the surface of the substrate; a first surrounding portion located on the first light-emitting unit, surrounding the first light-emitting unit and exposing the first semiconductor layer located on the first light-emitting unit; a second surrounding portion located on the second light-emitting unit, surrounding the second light-emitting unit and exposing the first semiconductor layer located on the second light-emitting unit The first semiconductor layer on the top; one or more connection electrodes each include a first connection end on the first light emitting unit and connected to the first semiconductor layer of the first light emitting unit, a second connection end on the second light emitting unit and connected to the second semiconductor layer of the second light emitting unit, and a third connection end in the trench to connect the first connection end and the second connection end;

A light-emitting element, comprising a substrate with a surface; a first light-emitting unit and a second light-emitting unit located on the substrate, the first light-emitting unit and the second light-emitting unit each comprising a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; a trench located between the first light-emitting unit and the second light-emitting unit, exposing the surface of the substrate; a first concave portion located on the first light-emitting unit and exposing the first semiconductor layer located on the first light-emitting unit; a second concave portion located on the second light-emitting unit and exposing the first semiconductor layer located on the second light-emitting unit, wherein the first The inner concave portion and the second inner concave portion are located on two opposite sides of the ditch; one or a plurality of connection electrodes each include a first connection terminal located on the first inner concave portion and contacting the first semiconductor layer of the first light-emitting unit, a second connection terminal covering the second inner concave portion and electrically connected to the second semiconductor layer of the second light-emitting unit, and a third connection terminal located in the trench to connect the first connection terminal and the second connection terminal; and an insulating layer covering the first semiconductor layer of the second inner concave portion and located below the second connection terminal.

A light-emitting element, comprising a substrate with a surface; a first light-emitting unit and a second light-emitting unit located on the substrate, the first light-emitting unit and the second light-emitting unit each comprising a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; a trench located between the first light-emitting unit and the second light-emitting unit, exposing the surface of the substrate; a first surrounding portion located on the first light-emitting unit and exposing the first semiconductor layer located on the first light-emitting unit; a second surrounding portion located on the second light-emitting unit and exposing the first semiconductor layer located on the second light-emitting unit; a plurality of connections The electrodes are located between the first light-emitting unit and the second light-emitting unit, and each includes a first connection end located on the first surrounding portion and contacting the first semiconductor layer of the first light-emitting unit, a second connection end covering the second surrounding portion and forming an electrical connection with the second semiconductor layer of the second light-emitting unit, and a third connection end located in the trench to connect the first connection end and the second connection end; a first lower electrode is located on the first surrounding portion and contacts the first semiconductor layer on the first light-emitting unit; From the view, the plurality of connection electrodes and the plurality of protrusions of the second lower electrodes are arranged alternately.

In order to make the description of the present invention more detailed and complete, please refer to the description of the following embodiments together with the relevant figures. However, the examples shown below are for illustrating the light-emitting device of the present invention, and the present invention is not limited to the following examples. In addition, the dimensions, materials, shapes, relative arrangements, etc. of the constituent parts described in the embodiments in this specification are not limited, and the scope of the present invention is not limited thereto, but is merely illustrative. In addition, the size and positional relationship of components shown in the drawings may be exaggerated for clarity. In addition, in the following description, in order to omit detailed description appropriately, the same name and symbol are used for the same or similar member.

FIG. 1 is a top view of a trench and a hole formed in a semiconductor stack according to an embodiment of the present invention. Fig. 2 is a sectional view along the tangent line A-A' of Fig. 1. The semiconductor stack includes a first semiconductor layer 201 , an active layer 202 , and a second semiconductor layer 203 sequentially formed on a surface of a substrate 10 . One or more trenches 21 pass through the second semiconductor layer 203, the active layer 202 and the first semiconductor layer 201 to expose one or more surfaces 21s of the substrate 10, and separate the semiconductor stack into a plurality of light-emitting units 20, wherein the plurality of light-emitting units 20 are separated from each other by the trench 21.

In this embodiment, as shown in FIG. 1 and FIG. 2, the light-emitting element 1 includes a first light-emitting unit 20a and a second light-emitting unit 20b, wherein the first light-emitting unit 20a and the second light-emitting unit 20b are separated by a trench 21 and expose the surface 21s of the substrate 10.

In another embodiment (not shown in the figure), the light-emitting element 1 includes a plurality of light-emitting units 20 arranged to form a rectangular array. The plurality of light-emitting units 20 are separated from each other by a plurality of trenches 21. The plurality of light-emitting units 20 may include the same area and/or shape, or different areas and/or shapes. The plurality of trenches 21 are connected to each other to continuously expose the surface 21s of the substrate 10.

In one embodiment, the light emitting element 1 may have a polygonal shape, such as a triangular, hexagonal, rectangular or square shape. The light-emitting device 1 includes a substrate 10 with a plurality of outer sidewalls S located around one of the light-emitting device 1 to form a polygonal, such as triangular, hexagonal, rectangular or square shape. Viewed from the top view, the size of the light emitting element 1 may be, for example, a square shape of 1000 μm to 1000 μm or 700 μm to 700 μm or a rectangular shape of similar size, but is not particularly limited thereto.

The substrate 10 may be a growth substrate, including a gallium arsenide (GaAs) wafer for epitaxial growth of aluminum gallium indium phosphide (AlGaInP), or a sapphire (Al ₂ O ₃ ) wafer, gallium nitride (GaN) wafer or silicon carbide (SiC) wafer for growth of indium gallium nitride (InGaN). In another embodiment, the substrate 10 can be a supporting substrate, and the semiconductor stacks originally grown on the growth substrate can be transferred to the above-mentioned supporting substrate, and the growth substrate originally used for epitaxy growth can be selectively removed according to the needs of the application.

The support substrate includes conductive materials such as silicon (Si), aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), silicon carbide (SiC) or alloys of the above materials, or thermal conductive materials such as diamond, graphite, or aluminum nitride. Moreover, although not shown in the figure, the side of the substrate 10 that is in contact with the semiconductor stack may have a roughened surface, and the roughened surface may be a surface with an irregular shape or a surface with a regular shape, such as a surface with multiple hemispherical shapes, a surface with multiple conical shapes, or a surface with multiple polygonal cone shapes.

In one embodiment of the present invention, a semiconductor laminate with optoelectronic properties, such as a light-emitting laminate, is formed on the substrate 10 by metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD) or ion plating, wherein the physical vapor deposition method includes sputtering or evaporation.

In one embodiment of the present invention, the semiconductor stack may further include a buffer layer (not shown) located between the first semiconductor layer 201 and the substrate 10 to release the stress between the substrate 10 and the first semiconductor layer 201 due to material lattice mismatch, so as to reduce misalignment and lattice defects, thereby improving epitaxy quality. The buffer layer can be a single layer or a structure comprising multiple layers. In one embodiment, PVD aluminum nitride (AlN) may be used as a buffer layer formed between the first semiconductor layer 201 and the substrate 10 to improve the epitaxial quality of the semiconductor stack. In one embodiment, a target for forming PVD aluminum nitride (AlN) is composed of aluminum nitride. In another embodiment, a target composed of aluminum is used to form aluminum nitride reactively with the aluminum target in the presence of a nitrogen source.

The wavelength of light emitted by the light-emitting element 1 is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack. The material of the semiconductor stack includes Group III-V semiconductor materials, such as Al _x In _y Ga _(1-xy) N or Al _x In _y Ga _(1-xy) P, where 0≦x, y≦1; (x+y)≦1. When the material of the semiconductor stack is AlInGaP series material, it can emit red light with a wavelength between 610 nm and 650 nm, or green light with a wavelength between 530 nm and 570 nm. When the material of the semiconductor stack is an InGaN series material, it can emit blue light with a wavelength between 400 nm and 490 nm. When the material of the semiconductor stack is AlGaN series or AlInGaN series materials, it can emit ultraviolet light with a wavelength between 400 nm and 250 nm.

The first semiconductor layer 201 and the second semiconductor layer 203 can be cladding layers (cladding layer), both have different conductivity types, electrical properties, polarities, or provide electrons or holes according to doped elements, for example, the first semiconductor layer 201 is an n-type electrical semiconductor, and the second semiconductor layer 203 is a p-type electrical semiconductor. The active layer 202 is formed between the first semiconductor layer 201 and the second semiconductor layer 203 . Electrons and holes are driven by a current to recombine in the active layer 202 to convert electrical energy into light energy to emit a light. The active layer 202 can be a single heterostructure (SH), double heterostructure (DH), double-side double heterostructure (DDH), or a multi-quantum well structure (MQW). The material of the active layer 202 can be neutral, p-type or n-type semiconductor. The first semiconductor layer 201, the active layer 202, or the second semiconductor layer 203 can be a single layer or a structure including multiple layers.

As shown in FIG. 2 , then, selective etching is performed on each light emitting unit 20 to form one or a plurality of hole portions 200 , one or a plurality of surrounding portions 204 and one or a plurality of semiconductor platforms 205 on each light emitting unit 20 . The semiconductor platform 205 on each light emitting unit 20 is surrounded by one or a plurality of surrounding parts 204 . For example, the photoresist pattern of the hole portion 200 , the surrounding portion 204 and the semiconductor platform 205 is formed by coating a photoresist and then removing part of the photoresist through a conventional patterning process. Then, an etching process is performed by using the photoresist pattern as an etching mask to form the hole portion 200 , the surrounding portion 204 and the semiconductor platform 205 . Specifically, each semiconductor platform 205 is formed by removing part of the second semiconductor layer 203 and the active layer 202 to form a structure including the first semiconductor layer 201 , the active layer 202 and the second semiconductor layer 203 . Each of the hole portion 200 and the surrounding portion 204 exposes the first semiconductor layer 201 by removing part of the second semiconductor layer 203 and the active layer 202 . The remaining photoresist pattern is removed after the etching process. In other words, the semiconductor platform 205 includes the first semiconductor layer 201 , the active layer 202 and the second semiconductor layer 203 . The hole portion 200 and the surrounding portion 204 include the first semiconductor layer 201 , but do not include the second semiconductor layer 203 and the active layer 202 .

As shown in FIG. 2, each semiconductor platform 205 includes an upper surface t1 and a lower surface b1, the active layer 202 includes a first upper surface and a second lower surface, wherein the first upper surface of the active layer 202 is closer to the upper surface t1 of the semiconductor platform than the second lower surface, a first distance is included between the upper surface t1 of the semiconductor platform 205 and the first upper surface of the active layer 202, and a second distance is included between the lower surface b1 of the semiconductor platform 205 and the second lower surface of the active layer 202, and the second distance is greater than the first distance.

In one embodiment, when the semiconductor stack is transferred from the growth substrate to the support substrate, each semiconductor platform 205 includes an upper surface t1 and a lower surface b1, and the active layer 202 includes a first upper surface and a second lower surface, wherein the upper surface t1 of the semiconductor platform 205 and the first upper surface of the active layer 202 are farther away from the supporting substrate than the lower surface b1 of the semiconductor platform and the second lower surface of the active layer 202 respectively. The first distance includes a second distance between the lower surface b1 of the semiconductor platform 205 and the second lower surface of the active layer 20 , and the first distance is greater than the second distance.

Viewed from a top view of the light emitting device 1 , as shown in FIG. 1 , the shape of one or more holes 200 includes ellipse, circle, rectangle or other arbitrary shapes. .

In one embodiment, as shown in FIG. 1 , each light emitting unit 20 includes only one surrounding portion 204 . In one embodiment, the surrounding portion 204 is located on the outermost side of each light emitting unit 20 and continuously surrounds the light emitting unit 20 . The outermost side of the light-emitting unit 20 includes a surrounding portion 204 that continuously surrounds. Viewed from a top view of the light-emitting element 1 , the shape of the surrounding portion 204 includes polygons, such as triangles, hexagons, rectangles or other arbitrary shapes. In other words, the shape of the surrounding portion 204 corresponds to the shape of each light emitting unit 20 . The shape of each surrounding portion 204 is similar to the shape of each light emitting unit 20 respectively. In one embodiment, the shape of the surrounding portion 204 includes a rectangle, and the shape of each light emitting unit 20 includes a rectangle. The surrounding portion 204 is located on the outermost side of each light emitting unit 20 , wherein the corners of the rectangle of the light emitting unit 20 can be rounded to prevent current from locally concentrating on the corners of each light emitting unit 20 . The surrounding portion 204 continuously surrounds the second semiconductor layer 203 and the active layer 202 of each light emitting unit 20 by exposing the surface of the outermost first semiconductor layer 201 of each light emitting unit 20 .

In another embodiment (not shown), each light emitting unit 20 includes a plurality of surrounding portions 204 respectively. The shapes of the plurality of surrounding portions 204 respectively include rectangle, ellipse or circle, and the plurality of surrounding portions 204 are located on the outermost side of each light emitting unit 20 to continuously surround the second semiconductor layer 203 and the active layer 202 of each light emitting unit 20 . In order to avoid local concentration of current at the corners of each light emitting unit 20 , the semiconductor stack located on the corner of each light emitting unit 20 , that is, the second semiconductor layer 203 and the active layer 202 at the corners may remain without being removed. By removing the second semiconductor layer 203 and the active layer 202 located on the multiple sides of each light emitting unit 20 , a plurality of surrounding portions 204 are formed on the multiple sides of each light emitting unit 20 . One or more surrounding portions 204 are located on one of the multiple sides of each light emitting unit 20 . The number of surrounding portions 204 included in one of the plurality of sides of each light emitting unit 20 may be the same as or different from the number of surrounding portions 204 included in the other side of the plurality of sides. Taking one of the light-emitting units 20 as an example, one side of the light-emitting unit 20 includes one or more surrounding portions 204, and the other side of the light-emitting unit 20, such as its adjacent or opposite side, may include one or more surrounding portions 204, and the number of surrounding portions 204 on both sides may be the same or different.

As shown in FIG. 1 , one or a plurality of hole portions 200 are located inside each light emitting unit 20 and surrounded by one or a plurality of surrounding portions 204 . In other words, one or a plurality of holes 200 are respectively surrounded by the second semiconductor layer 203 and the active layer 202 of each light emitting unit 20 .

The number and arrangement positions of the plurality of holes 200 are not limited, and they can be regularly arranged at certain intervals, so that the current can be uniformly dispersed in the horizontal direction. The plurality of hole portions 200 can be arranged in a plurality of rows, and the hole portions 200 in any two adjacent rows or every two adjacent rows can be aligned with each other or staggered. The positions of the subsequent contact layer and the electrode layer can be determined according to the arrangement positions of the plurality of hole portions 200 .

In one embodiment of the present invention (not shown in the figure), the holes 200 on two adjacent rows are staggered from each other, and the distance between the holes 200 on two adjacent rows is the same as the distance between the holes 200 on the same row, so that the plurality of holes 200 form the closest packing and evenly disperse the current.

In one embodiment of the present invention (not shown in the figure), considering the positions of subsequent contact layers and electrode layers, the holes 200 in two adjacent columns are staggered from each other, and the spacing between the holes 200 in two adjacent columns is smaller than the spacing between the holes 200 in the same column.

In one embodiment of the present invention (not shown in the figure), considering the positions of subsequent contact layers and electrode layers, the holes 200 on two adjacent columns are staggered from each other, and the spacing between the holes 200 on two adjacent columns is greater than the spacing between the holes 200 on the same column.

As shown in FIG. 1 and FIG. 2, the first light emitting unit 20a includes a first semiconductor platform 205a. The first light-emitting unit 20a includes one or a plurality of first holes 200a to expose the inner surface 200as of the first semiconductor layer 201, wherein, viewed from a top view of the light-emitting element, the plurality of first holes 200a are not connected to each other. The first light emitting unit 20a includes a first surrounding portion 204a formed on multiple sides of the first light emitting unit 20a to continuously expose the outer surface 204as of the first semiconductor layer 201, wherein the first surrounding portion 204a includes a first inner concave portion 2041a and a plurality of first outer concave portions 2042a. The first hole portion 200a is formed in the first semiconductor platform 205a, and the first surrounding portion 204a surrounds the first semiconductor platform 205a.

As shown in FIG. 1 and FIG. 2, the second light emitting unit 20b includes a second semiconductor platform 205b. The second light emitting unit 20b includes one or a plurality of second holes 200b to expose the inner surface 200bs of the first semiconductor layer 201, wherein, viewed from a top view of the light emitting element, the plurality of second holes 200b are not connected to each other. The second light emitting unit 20b includes a second surrounding portion 204b formed on multiple sides of the second light emitting unit 20b to continuously expose the outer surface 204bs of the first semiconductor layer 201, wherein the second surrounding portion 204b includes a second inner concave portion 2041b and a plurality of second outer concave portions 2042b. The second hole portion 200b is formed in the second semiconductor platform 205b, and the second surrounding portion 204b surrounds the second semiconductor platform 205b.

As shown in FIG. 1 and FIG. 2, the trench 21 between the first light emitting unit 20a and the second light emitting unit 20b is located between the first concave portion 2041a of the first light emitting unit 20a and the second concave portion 2041b of the second light emitting unit 20b.

As shown in FIG. 2, the first hole portion 200a is located in the first semiconductor platform 205a, and the first inner concave portion 2041a and the first outer concave portion 2042a are respectively located on two sides of the first semiconductor platform 205a. The second hole portion 200b is located in the second semiconductor platform 205b, and the second inner concave portion 2041b and the second outer concave portion 2042b are respectively located on two sides of the second semiconductor platform 205b.

Each of the first hole portion 200a and the second hole portion 200b includes a first slope S1, which has a first slope angle within a range relative to the horizontal extension planes of the inner surface 200as and the inner surface 200bs of the first semiconductor layer 201, for example, the inner angle is between 10° and 80°. Each of the first surrounding portion 204a and the second surrounding portion 204b includes a second slope S2, which has a second slope angle within a range relative to the horizontal extension planes of the outer surface 204as and the outer surface 204bs of the first semiconductor layer 201, for example, the inner angle is between 10° and 80°. If the angle is less than 10 degrees, the too low slope will reduce the area of the active layer 202, and the reduction of the area of the active layer 202 will reduce the brightness of the light emitting element. If the angle is greater than 80 degrees, subsequent insulating layers and metal layers may not completely cover the sidewalls of the first semiconductor layer 201 , the second semiconductor layer 203 , and/or the active layer 202 , thus causing film cracks.

In one embodiment, in order to maintain the symmetry of the structure and reduce the mask alignment error during the manufacturing process, the angle difference between the first bevel angle and the second bevel angle is less than 20 degrees, preferably less than 10 degrees, more preferably less than 5 degrees.

In one embodiment, the first semiconductor layer 201 of each light emitting unit 20 includes a third slope S3, which has an oblique angle within a range relative to the outer surface 204as or the outer surface 204bs of the first semiconductor layer 201, such as an angle of 10 degrees to 80 degrees.

In another embodiment, the third slope S3 included in the first semiconductor layer 201 has an angle close to 90 degrees relative to the outer surface 204as or outer surface 204bs of the first semiconductor layer 201, preferably an angle of 60 degrees to 120 degrees, more preferably an angle of 80 degrees to 110 degrees.

In one embodiment, the third slope S3 of the first semiconductor layer 201 is directly connected to the outer sidewall S of the substrate 10 . The outer sidewall S of the substrate 10 can be flush with the third slope S3 of the first semiconductor layer 201, or have an angle relative to the third slope S3 of the first semiconductor layer 201 within a range, preferably an angle of 60° to 120°, more preferably an angle of 80° to 110°.

In another embodiment, as shown in FIG. 2, by removing the first semiconductor layer 11, the second semiconductor layer 12 and the active layer 13, the light-emitting element 1 includes a dicing line 10d to expose an upper surface 10s of the substrate 10, wherein the first surrounding portion 204a is located between the dicing line 10d and the first semiconductor platform 205a, and the second surrounding portion 204b is located between the dicing line 10d and the second semiconductor platform 205b. The third slope S3 has a third slope angle within a range relative to the horizontal extension surface of the upper surface 10s of the substrate 10 , such as an inner angle ranging from 10° to 80°, preferably less than 60°, more preferably less than 40°.

The outer sidewall S of the substrate 10 may be perpendicular to the upper surface 10s exposed by the scribe line 10d, or have a fourth oblique angle within a range relative to the upper surface 10s exposed by the scribe line 10d, preferably an angle of 60° to 120°, more preferably an angle of 80° to 110°.

In another embodiment, in order to allow the subsequent insulating layer and metal layer to completely cover the third slope S3 , the angle difference between the third slope and the second slope is greater than 15 degrees, preferably greater than 25 degrees, and more preferably greater than 35 degrees.

Viewed from the top view of the light-emitting element 1 , each of the plurality of light-emitting units 20 includes a polygon or rectangle, and the plurality of light-emitting units 20 are arranged to form a rectangular array with a plurality of sides. The cutting line 10d surrounds multiple sides of the rectangular array formed by the multiple light emitting units 20 and continuously exposes the upper surface 10s of the substrate 10 .

The cutting line 10d is located at the outermost side of the light emitting element 1 . The top view shape of the cutting line 10d is the same as that of the rectangular array formed by the plurality of light emitting units 20 , for example, a rectangular or polygonal ring surrounds the outermost side of the rectangular array formed by the plurality of light emitting units 20 .

In one embodiment, the exposed upper surface 10s of the cutting line 10d is a rough surface. The rough surface may be a surface with an irregular shape or a surface with a regular shape, such as a surface with multiple hemispherical shapes, a surface with multiple conical shapes, or a surface with multiple polygonal cone shapes.

FIG. 3 is a top view of forming a contact electrode and a reflective layer according to an embodiment of the present invention. Figure 4 is a sectional view along the tangent line A-A' of Figure 3. FIG. 5 is a continuation of FIG. 3 and is a top view of forming a first insulating layer, a contact electrode, a reflective layer and a second insulating layer according to an embodiment of the present invention. Fig. 6 is a sectional view along the tangent line A-A' of Fig. 5.

As shown in FIG. 5 , a first insulating layer 50 is formed on the substrate 10 and each light emitting unit 20 . One or more first insulating layer openings 500 are formed on the first light emitting unit 20a, the second light emitting unit 20b and the trench 21 by selective etching to jointly expose the substrate 10, the first semiconductor layer 201 of the first light emitting unit 20a and the first semiconductor layer 201 of the second light emitting unit 20b. In one embodiment, one or a plurality of first insulating layer openings 500 formed on the trench 21 simultaneously expose the first semiconductor layer 201 in the first inner recess 2041 a and the second inner recess 2041 b.

As shown in FIG. 5 and FIG. 6, the first recessed portion 2041a of the first light emitting unit 20a forms one or a plurality of first openings 501a of the first insulating layer on the side adjacent to the trench 21 to expose the first semiconductor layer 201 of the first light emitting unit 20a.

As shown in FIG. 5, one or a plurality of second openings 502a and 502b of the first insulating layer are respectively formed on the second semiconductor layer 203 of the first light emitting unit 20a and the second light emitting unit to expose the second semiconductor layer 203, the contact electrode 30 and/or the reflective layer 40.

As shown in FIG. 5, one or a plurality of third openings 503a of the first insulating layer are respectively formed on the plurality of first outer recesses 2042a of the first light emitting unit 20a to expose the first semiconductor layer 201 of the first light emitting unit 20a. Another or a plurality of third openings 503b of the first insulating layer are respectively formed on the plurality of second outer recesses 2042b of the second light emitting unit 20b to expose the first semiconductor layer 201 of the second light emitting unit 20b.

As shown in FIG. 5, a fourth opening 504a, 504b of the first insulating layer is formed on the first hole 200a of the first light emitting unit 20a and the second hole 200b of the second light emitting unit 20b to expose the first semiconductor layer 201 respectively. The remaining area shown in FIG. 5 is shielded by the first insulating layer 50 .

In one embodiment, the first insulating layer 50 may be formed of an insulating material with light penetration. For example, the material of the first insulating layer 50 includes SiO _x .

In one embodiment, the first insulating layer 50 may include two or more materials with different refractive indices stacked alternately to form a Bragg reflector (DBR) structure. In one embodiment, the first insulating layer 50 can be stacked with layers such as SiO ₂ /TiO ₂ or SiO ₂ /Nb ₂ O ₅ to selectively reflect light of a specific wavelength and increase the light extraction efficiency of the light emitting device. When the peak emission wavelength of the light emitting element 1 is λ, the optical thickness of the first insulating layer 50 can be set to be an integer multiple of λ/4. The peak wavelength refers to the wavelength with the strongest intensity in the light emission spectrum of the light emitting element 1 . On the basis of an integer multiple of the optical thickness λ/4, the thickness of the first insulating layer 50 may have a deviation of ±30%.

In one embodiment, the first insulating layer 50 is formed of non-conductive materials, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide) Or fluorocarbon polymer (Fluorocarbon Polymer), or inorganic materials, such as silicone (Silicone) or glass (Glass), or dielectric materials, such as alumina (Al ₂o ₃), silicon nitride (SiN _x), silicon oxide (SiO _x), titanium oxide (TiO _x), or magnesium fluoride (MgF _x).

In one embodiment, the thickness of the first insulating layer 50 may be 1000 angstroms to 20000 angstroms.

In one embodiment, the material of the first insulating layer 50 is SiO ₂ , TiO ₂ , SiN _x and other materials. If the thickness of the first insulating layer 50 is less than 1000 angstroms, the thinner thickness may weaken the insulating property of the first insulating layer 50 . Specifically, the first insulating layer 50 is formed on the etched first slope S1 and the second slope S2, and the first insulating layer 50 formed conforming to the slope also has a specific slope. If the thickness of the first insulating layer 50 is less than 1000 angstroms, the film layer may be cracked.

In one embodiment, the material of the first insulating layer 50 is SiO ₂ , TiO ₂ , SiN _x and the like. If the thickness of the first insulating layer 50 exceeds 20000 angstroms, it will increase the difficulty of selective etching on the first insulating layer 50 . However, the above embodiments do not exclude other materials with good coverage extension or high selective etching to avoid the problems caused by the first insulating layer 50 being too thin or too thick.

The first insulating layer 50 has one side surface, which is an inclined plane relative to the horizontal extension plane of the inner surface 200as or the surface 204as of the first semiconductor layer 201 exposed through selective etching, and the inclined plane has an oblique angle between 10 degrees and 70 degrees relative to the horizontal extension plane of the inner surface 200as or the surface 204as of the first semiconductor layer 201 exposed through selective etching.

If the bevel angle of the side surface of the first insulating layer 50 is less than 10 degrees, the substantial thickness of the first insulating layer 50 will be reduced. Therefore, there may be a problem that it is difficult to ensure insulating properties.

If the inclination angle of the side surface of the first insulating layer 50 is greater than 70 degrees, subsequent insulating layers and metal layers may not be completely covered, thus causing film cracks.

As shown in FIG. 4 and FIG. 6 , a contact electrode 30 is formed on the second semiconductor layer 203 of each light emitting unit 20 . Specifically, the contact electrode 30 is formed in one or a plurality of second openings 502 a and 502 b of the first insulating layer. In other words, the contact electrode 30 is exposed by one or a plurality of second openings 502 a and 502 b of the first insulating layer on each light emitting unit 20 . The contact electrode 30 includes a transparent electrode. The material of the transparent electrode includes transparent conductive oxide or transparent metal. Translucent conductive oxides include indium tin oxide (ITO), zinc oxide (ZnO), zinc indium tin oxide (ZITO), indium zinc oxide (zinc indium oxide, ZIO), zinc tin oxide (ZTO), gallium indium tin oxide (Gallium indium tin oxide, GITO), gallium indium oxide (g allium indium oxide (GIO), or gallium zinc oxide (GZO). The transparent conductive oxide may include various dopants, such as aluminum doped zinc oxide (AZO) or fluorine doped tin oxide (FTO). The translucent metal includes nickel (Ni) or gold (Au).

The thickness of the contact electrode 30 is not limited, but may have a thickness of about 0.1 nm to 100 nm. In one embodiment, the material of the contact electrode 30 is light-transmitting conductive oxide. If the thickness of the contact electrode 30 is less than 0.1 nm, the ohmic contact with the second semiconductor layer 203 cannot be effectively formed because the thickness is too thin. Moreover, if the thickness of the contact electrode 30 is greater than 100 nm, the light emitted by the active layer 202 will be partially absorbed due to the thickness being too thick, thereby causing the problem that the brightness of the light emitting element 1 is reduced. Since the contact electrode 130 has a thickness in the above-mentioned range, the current can be smoothly dispersed in the horizontal direction to improve the electrical performance of the light emitting element. However, the above embodiments do not exclude other materials with lateral current spreading.

The contact electrode 30 is formed on substantially the entire surface of the second semiconductor layer 203 of each light emitting unit 20, and forms a low-resistance contact with the second semiconductor layer 203 of each light emitting unit 20, such as an ohmic contact, so that current can be uniformly diffused through the second semiconductor layer 203 through the contact electrode 30. In one embodiment, viewed from the cross-sectional view of the light-emitting element, the contact electrode 30 includes an outermost side, which is separated from the second slope S2 of the light-emitting unit 20 by a horizontal distance of less than 20 μm, preferably less than 10 μm, more preferably less than 5 μm.

A reflective layer 40 is formed on the contact electrode 30 of each light emitting unit 20 . The reflective layer 40 is made of metals such as aluminum (Al), silver (Ag), rhodium (Rh) or platinum (Pt) or alloys of the above materials. The reflective layer 40 is used to reflect light and make the reflected light go out towards the substrate 10 , wherein the reflected light is generated by the active layer 202 of each light emitting unit 20 .

In another embodiment, the forming step of the contact electrode 30 may be omitted. A reflective layer 40 is formed in one of the light emitting units 20 or in the plurality of second openings 502 a and 502 b of the first insulating layer, and the reflective layer 40 can form an ohmic contact with the second semiconductor layer 203 .

In one embodiment, viewed from the cross-sectional view of the light-emitting element, as shown in FIG. 4 and FIG. 6, the reflective layer 40 includes an outermost side, which is separated from the second slope S2 of the light-emitting unit 20 by a horizontal distance of less than 20 μm, preferably less than 10 μm, more preferably less than 5 μm.

In one embodiment, the reflection layer 40 can be one or multi-layer structure, such as a Bragg reflection structure.

In one embodiment, a surface of the reflective layer 40 is an inclined plane relative to the upper surface of the second semiconductor layer 203 , and the inclined plane may have an oblique angle of 10 degrees to 60 degrees relative to the surface of the second semiconductor layer 203 . The material of the reflective layer 40 is silver (Ag). If the inclination angle of the reflective layer 40 is less than 10 degrees, the very gentle slope will reduce the reflection efficiency of the bottom light. In addition, it is difficult to ensure the thickness uniformity when the bevel angle is less than 10 degrees. If the bevel angle of the reflective layer 40 is greater than 60 degrees, the bevel angle greater than 60 degrees may cause cracks in subsequent film layers. However, the above embodiments do not exclude other materials with high reflectivity.

The adjustment of the bevel angle of the reflective layer 40 can be achieved by changing the configuration of the substrate and the advancing direction of the metal atoms in the thermal deposition process. For example, the position of the substrate is adjusted so that the surface of the substrate is an inclined surface relative to the deposition direction of evaporation or sputtering.

In one embodiment, a barrier layer (not shown) is formed on the reflective layer 40 of each light-emitting unit 20 to cover the upper surface and the side surface of the reflective layer 40, so as to prevent the surface of the reflective layer 40 from being oxidized, thus deteriorating the reflectivity of the reflective layer 40. The material of the barrier layer includes metal materials, such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), chromium (Cr), platinum (Pt) or alloys of the above materials. The barrier layer can be one or multi-layer structure, such as titanium (Ti)/aluminum (Al), and/or nickel-titanium alloy (NiTi)/titanium-tungsten alloy (TiW). In one embodiment of the present invention, the barrier layer includes a stacked structure of titanium (Ti)/aluminum (Al) and a stacked structure of nickel-titanium alloy (NiTi)/titanium-tungsten alloy (TiW), wherein the stacked structure of titanium (Ti)/aluminum (Al) is located on a side away from the reflective layer 40, and the stacked structure of nickel-titanium alloy (NiTi)/titanium-tungsten alloy (TiW) is located on a side close to the reflective layer 40. In one embodiment of the present invention, the materials of the reflective layer 40 and the barrier layer preferably include metal materials other than gold (Au) or copper (Cu).

The stacked structure of the barrier layer is nickel-titanium alloy (NiTi)/titanium-tungsten alloy (TiW)/platinum (Pt)/titanium (Ti)/aluminum (Al)/titanium (Ti)/aluminum (Al)/chromium (Cr)/platinum (Pt), and the barrier layer can have an off angle of 10 degrees to 60 degrees relative to the surface of the second semiconductor layer 203. In one embodiment, if the slope angle of the barrier layer is less than 10 degrees, the very gentle slope cannot completely cover the reflective layer 40 . In addition, it is difficult to ensure the thickness uniformity when the bevel angle is less than 10 degrees. If the bevel angle of the barrier layer is greater than 60 degrees, the bevel angle greater than 60 degrees may cause cracks in subsequent film layers.

In one embodiment, the reflective layer 40 or the barrier layer preferably has a thickness of 100 nm to 1 μm. If the thickness of the reflective layer 40 or the barrier layer is less than 100 nm, the light emitted by the active layer 203 cannot be effectively reflected. Moreover, if the thickness of the reflective layer 40 or the barrier layer is greater than 1 μm, excessive production time will result in loss in production.

In order to cover the upper surface and the side surface of the reflective layer 40 , the barrier layer includes a bottom surface to be in contact with the second semiconductor layer 203 and/or the contact electrode 30 .

As shown in FIG. 5, a second insulating layer 60 is formed on the substrate 10 and each light emitting unit 20, and one or a plurality of second insulating layer openings 600 are formed on the first light emitting unit 20a, the second light emitting unit 20b, and the trench 21 by selective etching to jointly expose the substrate 10, the first semiconductor layer 201 of the first light emitting unit 20a, and the first semiconductor layer 201 of the second light emitting unit 20b. In one embodiment, one or a plurality of second insulating layer openings 600 formed on the adjacent trench 21 exposes the first semiconductor layer 201 in the first inner recess 2041a and the second inner recess 2041b at the same time.

As shown in FIG. 5 and FIG. 6 , the first concave portion 2041 a of the first light emitting unit 20 a forms one or a plurality of first openings 601 a of the second insulating layer on the adjacent trench 21 to expose the first semiconductor layer 201 .

As shown in FIG. 5, one or a plurality of second openings 602a and 602b of the second insulating layer are respectively formed on the second semiconductor layer 203 of the first light emitting unit 20a and the second light emitting unit to expose the second semiconductor layer 203, the contact electrode 30 and/or the reflective layer 40.

As shown in FIG. 5 , viewed from a top view of the light-emitting element 1 , the positions of the plurality of first openings 601 a of the second insulating layer and the plurality of second openings 602 b of the second insulating layer are aligned with each other.

As shown in FIG. 5, one or a plurality of third openings 603a of the second insulating layer are respectively formed on the plurality of first concave portions 2042a of the first light emitting unit 20a to expose the first semiconductor layer 201 of the first light emitting unit 20a. Another or a plurality of third openings 603b of the second insulating layer are respectively formed on the plurality of second outer recesses 2042b of the second light emitting unit 20b to expose the first semiconductor layer 201 of the second light emitting unit 20b.

As shown in FIG. 5, a fourth opening 604a, 604b of the second insulating layer is formed on the first hole 200a of the first light emitting unit 20a and the second hole 200b of the second light emitting unit 20b to expose the first semiconductor layer 201 respectively. The remaining area shown in FIG. 5 is shielded by the second insulating layer 60 .

The number and/or positions of the first openings 601 a of the second insulating layer 60 are corresponding to the first openings 501 a of the first insulating layer 50 . The number and/or positions of the third openings 603a, 603b of the second insulating layer are respectively corresponding to the third openings 503a, 503b of the first insulating layer. The number and/or positions of the fourth openings 604a, 604b of the second insulating layer are respectively corresponding to the fourth openings 504a, 504b of the first insulating layer.

The positions of the second openings 602a, 602b of the second insulating layer partially overlap with the positions of the second openings 502a, 502b of the first insulating layer. The number of openings of the second openings 602a, 602b of the second insulating layer is different from the number of openings of the second openings 502a, 502b of the first insulating layer. In one embodiment, the plurality of second openings 602a, 602b of the second insulating layer are respectively located in the second openings 502a, 502b of the first insulating layer. The size of the first opening 502a, 502b of the first insulating layer is greater than the size of any one of the plurality of second openings 602a, 602b of the second insulating layer.

In one embodiment, the second insulating layer 60 may be formed of an insulating material with light penetration. For example, the second insulating layer 60 includes SiOx.

In one embodiment, the second insulating layer 60 may include two or more materials with different refractive indices stacked alternately to form a Bragg reflector (DBR) structure. For example, the second insulating layer 60 may include laminated layers such as SiO2/TiO2 or SiO2/Nb2O5 to selectively reflect light of a specific wavelength and increase the light extraction efficiency of the light emitting element 1 . When the peak emission wavelength of the light emitting element 1 is λ, the optical thickness of the second insulating layer 60 can be set to be an integer multiple of λ/4. The peak wavelength refers to the wavelength with the strongest intensity in the light emission spectrum of the light emitting element 1 . The thickness of the second insulating layer 60 may have a deviation of ±30% based on an integer multiple of the optical thickness λ/4.

The second insulating layer 60 is formed of non-conductive materials, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide) or fluorocarbon polymer (Flu orocarbon Polymer), or inorganic materials, such as silica gel (Silicone) or glass (Glass), or dielectric materials, such as aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), titanium oxide (TiOx), or magnesium fluoride (MgFx).

In one embodiment, the thickness of the second insulating layer 60 may be 1000 angstroms to 20000 angstroms.

In one embodiment, if the material of the second insulating layer 60 is SiO2, TiO2, SiNx and other materials, if the thickness of the second insulating layer 60 is less than 1000 angstroms, the thinner thickness may weaken the insulating property of the second insulating layer 60 . Specifically, the second insulating layer 60 is formed on the first slope S1 and the second slope S2 after etching, and the second insulating layer 60 formed conforming to the slope also has a specific slope. If the thickness of the second insulating layer 60 is less than 1000 angstroms, the film layer may be cracked.

In one embodiment, the material of the second insulating layer 60 is SiO2, TiO2, SiNx and other materials. If the thickness of the second insulating layer 60 exceeds 20000 angstroms, it will increase the difficulty of selective etching on the second insulating layer 60 . However, the above embodiments do not exclude other materials with good coverage extension or high selective etching, which can avoid the above-mentioned problems caused by the second insulating layer 60 being too thin or too thick.

The second insulating layer 60 has a surface, which is an inclined plane relative to the horizontal extension surface of the inner surface 200as or the outer surface 204as of the first semiconductor layer 201 exposed through selective etching, and the inclined surface has an oblique angle relative to the horizontal extension surface of the inner surface 200as or the outer surface 204as of the first semiconductor layer 201 exposed through selective etching, and the oblique angle is between 10 degrees and 70 degrees.

If the bevel angle of the surface of the second insulating layer 60 is less than 10 degrees, the substantial thickness of the second insulating layer 60 will be reduced. Therefore, there may be a problem that it is difficult to ensure insulating properties.

If the inclination angle of the surface of the second insulating layer 60 is greater than 70 degrees, subsequent insulating layers and metal layers may not be able to cover completely, thus resulting in cracking of the film layer.

Fig. 7 is a top view of forming an upper electrode, a lower electrode and a connecting electrode disclosed by an embodiment of the present invention. Figure 7A and Figure 7B are partially enlarged views of Figure 7. Figure 8 is a sectional view along the tangent line A-A' of Figure 7. One or more connecting electrodes 70 are formed between the first light emitting unit 20a and the second light emitting unit 20b. One or more connection electrodes 70 each include a first connection terminal 701 located on the first concave portion 2041a of the first light emitting unit 20a, covering the first opening 601a of the second insulating layer, and electrically connected to the first semiconductor layer 201 of the first light emitting unit 20a through the first opening 601a of the second insulating layer and the first opening 501a of the first insulating layer; a second connection terminal 702 is located on the second semiconductor layer 203 of the second light emitting unit 20b, b and the second opening 502b of the first insulating layer are electrically connected to the second semiconductor layer 203 of the second light emitting unit 20b;

In one embodiment, as shown in FIG. 7A, the first connection end 701 of the connection electrode 70 includes a first connection portion 7011 located in the first opening 601a of the second insulating layer on the first light emitting unit 20a. The second connection end 702 of the connection electrode 70 includes a second connection portion 7022 located in the second opening 602b of the second insulating layer on the second light emitting unit 20b.

In one embodiment, as shown in FIG. 7A, the first connection portion 7011 of the first connection end 701 located in the first opening 601a of the second insulating layer is in direct contact with the first semiconductor layer 201 of the first light emitting unit 20a, and the second connection portion 7022 of the second connection end 702 located in the second opening 602b of the second insulating layer is in contact with the barrier layer, the reflective layer 40 or the contact electrode 30.

In one embodiment of the present invention, as shown in FIG. 7A, viewed from the top view of the light-emitting element 1, the third connection end 703 includes a third connection first end 7031 bridged on the third slope S3 of the first light-emitting unit 20a, and a third connection second end 7032 bridged on the third slope S3 of the second light-emitting unit 20b. The third connection first end 7031 and/or the third connection second end 7032 include a width of at least 15 μm or more, preferably 30 μm or more, more preferably 50 μm or more.

In one embodiment, in order to uniformly inject the current from the first light emitting unit 20a into the second light emitting unit 20b, the total area that current can be injected into the second light emitting unit 20b is increased, and the cross-sectional current density of the second connection end 702 is reduced. As shown in FIG. 7 and FIG. 7A, from the top view of the light-emitting element 1, the second opening 602b of the second insulating layer located in the second light-emitting unit 20b includes a first opening area larger than the second opening area of the first opening 601a of the second insulating layer located in the first light-emitting unit 20a. The first connection portion 7011 of the first connection end 701 includes a first width W1 that is smaller than the second width W2 included in the second connection portion 7022 of the second connection end 702 . The third connection second end 7032 of the third connection end 703 includes a third width W3 smaller than the width of the third connection first end 7031 , and the width included between the third connection first end 7031 and the third connection second end 7032 is a gradual change.

In another embodiment (not shown), in order to uniformly inject the current from the first light emitting unit 20a into the second light emitting unit 20b, the total area that current can be injected into the second light emitting unit 20b is increased, and the cross-sectional current density of the second connection terminal 702 is reduced. The first width W1 included in the first connection portion 7011 of the first connection end 701 is smaller than the second width W2 included in the second connection portion 7022 of the second connection end 702, and the third width W3 included in the third connection second end 7032 of the third connection end 703 is the same as the width included in the third connection first end 7031.

In another embodiment (not shown in the figure), in order to distribute the current evenly between the first connection end 701 and the first surrounding portion 204a, the first connection portion 7011 of the first connection end 701 includes a first width W1 that is greater than the second connection portion 7022 of the second connection end 702.

In another embodiment (not shown), in order to avoid uneven current density of the connecting electrode 70, the first width W1 included in the first connecting portion 7011 of the first connecting end 701 is the same as the second width W2 included in the second connecting portion 7022 of the second connecting end 702. The third width W3 included in the third connecting portion 703 is larger than the first width W1 included in the first connecting portion 7011 and/or larger than the second width W2 included in the second connecting portion 7022 .

In one embodiment, one or a plurality of first upper electrodes 71a are respectively formed in one of the first light emitting unit 20a or in a plurality of second openings 602a of the second insulating layer, and are electrically connected to the second semiconductor layer 203 of the first light emitting unit 20a.

A first lower electrode 72a covers the first inner concave portion 2041a and the plurality of first outer concave portions 2042a of the first light emitting unit 20a. The first lower electrode 72a is in direct contact with the first semiconductor layer 201 located in the first concave portion 2041a of the first light emitting unit 20a through one or a plurality of second insulating layer openings 600 and one or a plurality of second insulating layer first openings 601a. The first lower electrode 72a is in direct contact with the first semiconductor layer 201 located in the plurality of first outer recesses 2042a through one or a plurality of third openings 603a of the second insulating layer, and forms an electrical connection with the first semiconductor layer 201 of the first light emitting unit 20a. The first lower electrode 72a is in direct contact with the first semiconductor layer 201 of the first hole portion 200a through a fourth opening 604a of the second insulating layer, and is electrically connected with the first semiconductor layer 201 of the first light emitting unit 20a. Viewed from the top view of the light-emitting element 1 , the plurality of second insulating layer openings 600 and the plurality of connection electrodes 70 are arranged alternately with each other. The first lower electrode 72a extends along the second slope S2 of the first light emitting unit 20a and covers the first semiconductor platform 205a to reflect the light emitted by the active layer 202 of the first light emitting unit 20a.

The second insulating layer opening 600, the second insulating layer first opening 601a and the second insulating layer third opening 603a expose the first semiconductor layer 201 located in the first surrounding portion 204a of the first light emitting unit 20a. From the top view of the light emitting element 1, the second insulating layer opening 600, the second insulating layer first opening 601a and the second insulating layer third opening 603a include different sizes.

The second insulating layer 60 is located between the first upper electrode 71a and the first lower electrode 72a to avoid contact between the first upper electrode 71a and the first lower electrode 72a to form a short circuit. A portion of the second insulating layer 60 is located under the first lower electrode 72 a extending to cover the first semiconductor platform 205 a, preventing the first lower electrode 72 a from contacting the barrier layer, the reflective layer 40 and/or the contact electrode 30 .

The first surrounding portion 204a on the first light emitting unit 20a includes a first inner concave portion 2041a and a plurality of first outer concave portions 2042a to form a rectangle, and is located around the first light emitting unit 20a, wherein compared with the plurality of first outer concave portions 2042a, the first inner concave portion 2041a is adjacent to one side of the trench 21. From the top view of the light-emitting element 1, as shown in FIG. 7, the plurality of second insulating layer openings 600 and the plurality of second insulating layer first openings 601a are alternately arranged to expose the first semiconductor layer 201 on the first light-emitting unit 20a. In a direction parallel to one side of the first inner concave portion 2041 a , the opening 600 of the second insulating layer includes a width larger or smaller than that of the first opening 601 a of the second insulating layer to uniformly disperse the current near the connection electrode 70 .

As shown in FIG. 7A, the first lower electrode 72a is formed in the opening 600 of the second insulating layer, extends to cover the second insulating layer 60, and is connected to the first connecting portion 7011 of the first connecting terminal 701 located on the first opening 601a of the second insulating layer.

Viewed from the top view of the light emitting element 1, as shown in FIG. 7, one or a plurality of first upper electrodes 71a located on the first light emitting unit 20a are respectively surrounded by the first lower electrodes 72a.

In one embodiment, viewed from the top view of the light-emitting element 1, as shown in FIG. 7, one or a plurality of first upper electrodes 71a located on the first light-emitting unit 20a respectively include a first upper surface area greater than a first lower surface area included in the first lower electrode 72a.

In another embodiment (not shown in the figure), viewed from the top view of the light-emitting element 1, one or a plurality of first upper electrodes 71a located on the first light-emitting unit 20a respectively include a first upper surface area smaller than a first lower surface area included in the first lower electrode 72a.

In another embodiment (not shown in the figure), viewed from the top view of the light-emitting element 1, one or a plurality of first upper electrodes 71a located on the first light-emitting unit 20a respectively include a first upper surface area equal to a first lower surface area included in the first lower electrode 72a.

A second lower electrode 72b covers the second inner concave portion 2041b and the plurality of second outer concave portions 2042b of the second light emitting unit 20b. The second lower electrode 72b can directly contact the first semiconductor layer 201 located in the second inner concave portion 2041b through one or a plurality of second insulating layer openings 600 . The second lower electrode 72b can be in direct contact with the first semiconductor layer 201 located in the plurality of second outer recesses 2042b through one or a plurality of third openings 603b of the second insulating layer, and form an electrical connection with the first semiconductor layer 201 of the second light emitting unit 20b. The second lower electrode 72b can directly contact the first semiconductor layer 201 located in the second hole portion 200b through the fourth opening 604b of the second insulating layer, and form an electrical connection with the first semiconductor layer 201 of the second light emitting unit 20b. Viewed from the top view of the light-emitting element 1 , the plurality of second insulating layer openings 600 and the plurality of connection electrodes 70 are arranged alternately with each other. The second lower electrode 72 b extends along the second slope S2 of the second light emitting unit 20 b to cover the second semiconductor platform 205 b to reflect the light emitted by the active layer 202 .

As shown in FIG. 8 , the second insulating layer 60 is located under the second lower electrode 72 b to prevent the second lower electrode 72 b from contacting the barrier layer, the reflective layer 40 and/or the contact electrode 30 .

In one embodiment, as shown in FIG. 7, viewed from the top view of the light-emitting element 1, the second lower electrode 72b located on the second light-emitting unit 20b includes a second lower surface area greater than the first lower surface area included in the first lower electrode 72a located on the first light-emitting unit 20a.

In another embodiment, as shown in FIG. 7, viewed from the top view of the light emitting element 1, the second lower surface area included in the second lower electrode 72b located on the second light emitting unit 20b is larger than the first upper surface area included in each first upper electrode 71a located on the first light emitting unit 20a.

In another embodiment, as shown in FIG. 7, viewed from the top view of the light emitting element 1, the second lower surface area included in the second lower electrode 72b on the second light emitting unit 20b is greater than the sum of the first upper surface areas included in the plurality of first upper electrodes 71a located on the first light emitting unit 20a.

As shown in FIG. 7, the trench 21 is located between the first concave portion 2041a of the first light emitting unit 20a and the second concave portion 2041b of the second light emitting unit 20b. The first insulating layer opening 500 and the second insulating layer opening 600 expose the surface 21s of the substrate 10 , the first semiconductor layer 201 located in the first concave portion 2041a and the first semiconductor layer 201 located in the second concave portion 2041b. In other words, the first insulating layer opening 500 and the second insulating layer opening 600 formed adjacent to the trench 21 expose the first semiconductor layer 201 of the first inner recess 2041 a and the second inner recess 2041 b at the same time. A portion of the first lower electrode 72 a is located in the first insulating layer opening 500 and the second insulating layer opening 600 , and is in direct contact with the first semiconductor layer 201 of the first inner concave portion 2041 a. A portion of the second lower electrode 72b is located in the first insulating layer opening 500 and the second insulating layer opening 600, and is in direct contact with the first semiconductor layer 201 of the second inner concave portion 2041b. The first lower electrode 72 a and the second lower electrode 72 b are separated from each other by the trench 21 .

As shown in FIG. 7B , the second lower electrode 72b includes one or a plurality of second lower electrode recesses 721b for accommodating one or a plurality of second connection terminals 702 respectively; The second lower electrode protrusion 722b includes a width W4 greater than or less than the width of the second connection end 702 . In order to uniformly inject the current of the second lower electrode 72b into the first semiconductor layer 201 of the second light emitting unit 20b, the second lower electrode protrusion 722b further includes one or a plurality of second lower electrode extensions 724b located on the second inner concave portion 2041b. The second lower electrode extension portion 724b extends into the second insulating layer opening 600 and directly contacts the first semiconductor layer 201 of the second inner concave portion 2041b. In order to increase the area where current can be injected, the second lower electrode extension 724b includes a width W5 greater than the width W4 of the second lower electrode protrusion 722b.

In one embodiment, as shown in FIG. 7 , viewed from a top view of the light-emitting element 1 , the width of the second lower electrode protrusion 722 b is smaller than the width of the second connection end 702 .

In another embodiment (not shown), viewed from a top view of the light-emitting element 1 , the width of the second lower electrode protrusion 722 b is greater than the width of the second connection end 702 .

As shown in FIG. 7, from a top view of the light-emitting element 1, a plurality of second lower electrode protrusions 722b and a plurality of second connection terminals 702 are alternately arranged to inject current into the first semiconductor layer 201 and the second semiconductor layer 203 of the second light-emitting unit 20b uniformly. A number included in the plurality of second lower electrode protrusions 722b is different from a number included in the plurality of second connection terminals 702, for example, the number included in the plurality of second lower electrode protrusions 722b is greater than or smaller than the number included in the plurality of second connection terminals 702.

The first lower electrode 72a located on the first light emitting unit 20a is in direct contact with the outer surface 204as of the first semiconductor layer 201 of the first light emitting unit 20a. The second lower electrode 72b located on the second light emitting unit 20b is in direct contact with the outer surface 204bs of the first semiconductor layer 201 of the second light emitting unit 20b. As shown in FIG. 8, when the first lower electrode 72a or the second lower electrode 72b completely covers the outer surface 204as or the outer surface 204bs of the first semiconductor layer 201, the first lower electrode 72a or the second lower electrode 72b respectively includes a first lower electrode outer sidewall 72as and a second lower electrode outer sidewall 72bs to be directly connected to the third slope S3 of the first semiconductor layer 201. In one embodiment, when the first lower electrode 72a or the second lower electrode 72b partially covers the outer surface 204as or the outer surface 204bs of the first semiconductor layer 201, the first lower electrode outer wall 72as or the second lower electrode outer wall 72bs included in the first lower electrode 72a or the second lower electrode 72b is separated from the third slope S3 of the first semiconductor layer 201 by a distance to partially expose the outer surface 204as or outer surface 204bs of the first semiconductor layer 201 (not shown).

In one embodiment, the first upper electrode 71a on the first light emitting unit 20a has an inclined side surface to reduce the risk of delamination from the reflective layer 40 or the barrier layer, and increase the coverage of subsequent stacked layers. The first lower electrode 72a on the first light-emitting unit 20a and the second lower electrode 72b on the second light-emitting unit 20b respectively have an inclined side surface to reduce the risk of delamination from the first semiconductor layer 201 and increase the coverage of subsequent stacked layers. There is an included angle between the inclined side surface of the first upper electrode 71 a and the surface of the reflective layer 40 or the barrier layer, which is between 30 degrees and 75 degrees. The inclined side surface of the first lower electrode 72 a and/or the second lower electrode 72 b has an included angle between 30 degrees and 75 degrees with the surface of the first semiconductor layer 201 .

The first upper electrode 71a, the first lower electrode 72a and/or the second lower electrode 72b include metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni) or platinum (Pt) or alloys of the above materials. The first upper electrode 71a, the first lower electrode 72a and/or the second lower electrode 72b may be composed of a single layer or multiple layers. For example, the first upper electrode 71a, the first lower electrode 72a, and/or the second lower electrode 72b may include a Ti/Au layer, a Ti/Pt/Au layer, a Cr/Au layer, a Cr/Pt/Au layer, a Ni/Au layer, a Ni/Pt/Au layer, or a Cr/Al/Cr/Ni/Au layer.

The thickness of the first upper electrode 71a, the first lower electrode 72a and/or the second lower electrode 72b is preferably 0.5 μm to 3.5 μm.

In one embodiment, the first upper electrode 71a includes a top surface lower than that of the first lower electrode 72a. In other words, there is a level difference between the top surface of the first upper electrode 71 a and the top surface of the first lower electrode 72 a, wherein the level difference is between 2000 angstroms and 20000 angstroms.

In one embodiment, the top surface of the first lower electrode 72a and the top surface of the second lower electrode 72b include a step difference, wherein the step difference is less than 2000 angstroms, preferably less than 1000 angstroms, more preferably less than 500 angstroms.

In one embodiment, the top surface of the first lower electrode 72a and the top surface of the second lower electrode 72b are substantially flush.

FIG. 9 is a top view of forming a third insulating layer disclosed by an embodiment of the present invention. Figure 10 is a sectional view along the tangent line A-A' of Figure 9. A third insulating layer 80 is formed on the substrate 10 and each light-emitting unit 20, and one or more first openings 801 of the third insulating layer and one or more second openings 802 of the third insulating layer are formed on each light-emitting unit 20 by selective etching. One or a plurality of first openings 801 of the third insulating layer respectively expose one of the first light emitting units 20a or a plurality of first upper electrodes 71a. One or a plurality of second openings 802 of the third insulating layer expose the second lower electrode 72b of the second light emitting unit 20b. The remaining area is shielded by the third insulating layer 80 .

In one embodiment, as shown in FIG. 9, viewed from the top view of the light-emitting element 1, one of the first light-emitting unit 20a or the plurality of third insulating layer first openings 801 has a width smaller than that of the second light-emitting unit 20b or the plurality of third insulating layer second openings 802. The widths of the plurality of third insulating layer first openings 801 may be the same or different from each other, and/or the plurality of third insulating layer second openings 802 may have the same or different widths.

In another embodiment (not shown in the figure), viewed from the top view of the light-emitting element 1, one of the first light-emitting unit 20a or the plurality of third insulating layer first openings 801 has a width greater than that of the second light-emitting unit 20b or the plurality of third insulating layer second openings 802.

In one embodiment, the light-emitting element includes the cutting line 10d located on the outermost side of the light-emitting element 1 . The third insulating layer 80 covers the exposed upper surface 10s of the substrate 10 , wherein the third insulating layer 80 includes a third insulating sidewall 80s directly in contact with the outer sidewall S of the substrate 10 or separated by a distance to expose part of the upper surface 10s of the substrate 10 .

In another embodiment, the third slope S3 of the first semiconductor layer 201 is directly connected to an outer wall of the substrate 10 . The third insulating layer 80 covers the outer surface 204as or the outer surface 204bs of the first semiconductor layer 201, wherein the third insulating sidewall 80s included in the third insulating layer 80 is in direct contact with the third slope S3 of the first semiconductor layer 201 or separated by a distance to partially expose the outer surface 204as or the outer surface 204bs of the first semiconductor layer 201.

In one embodiment, the third insulating layer 80 may be formed of an insulating material with light penetration. For example, the third insulating layer 80 includes SiO _x .

In another embodiment, the third insulating layer 80 may include two or more materials with different refractive indices stacked alternately to form a Bragg reflector (DBR) structure. In one embodiment, the third insulating layer 80 may include layers such as SiO ₂ /TiO ₂ or SiO ₂ /Nb ₂ O ₅ to selectively reflect light of a specific wavelength and increase the light extraction efficiency of the light emitting device. When the peak emission wavelength of the light emitting element 1 is λ, the optical thickness of the third insulating layer 80 can be set to be an integer multiple of λ/4. The peak wavelength refers to the wavelength with the strongest intensity in the light emission spectrum of the light emitting element 1 . The thickness of the third insulating layer 80 may have a deviation of ±30% on the basis of integer multiples of λ/4.

In one embodiment, the third insulating layer 80 is formed of non-conductive materials, including organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), cycloolefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide) Or fluorocarbon polymer (Fluorocarbon Polymer), or inorganic materials, such as silicone (Silicone) or glass (Glass), or dielectric materials, such as alumina (Al ₂o ₃), silicon nitride (SiN _x), silicon oxide (SiO _x), titanium oxide (TiO _x), or magnesium fluoride (MgF _x).

In one embodiment, the thickness of the third insulating layer 80 may be 2000 angstroms to 60000 angstroms.

In one embodiment, the material of the third insulating layer 80 is SiO ₂ , TiO ₂ , SiN _x and the like. If the thickness of the third insulating layer 80 is less than 2000 angstroms, the thinner thickness may weaken the insulating property of the third insulating layer 80 . Specifically, the third insulating layer 80 is formed on the etched first slope S1 and the second slope S2, and the third insulating layer 80 formed conforming to the slope also has a specific slope. If the thickness of the third insulating layer 80 is less than 2000 angstroms, the film layer may be cracked.

In one embodiment, if the material of the third insulating layer 80 is SiO ₂ , TiO ₂ , SiN _x and the like, if the thickness of the first insulating layer 50 exceeds 60000 angstroms, it will increase the difficulty of selective etching on the third insulating layer 80 . However, the above embodiments do not exclude other materials with good coverage extension or high selective etching, which can avoid the above-mentioned problems caused by the first insulating layer 50 being too thin or too thick.

The third insulating layer 80 includes a third insulating sidewall 80s, which is an inclined plane relative to the inner surface 200as, 200bs, outer surface 204as, 204bs of the first semiconductor layer 201 exposed through selective etching or the horizontal extension surface of the upper surface 10s exposed by the substrate 10. s or the horizontal extension surface of the exposed upper surface 10s of the substrate 10 has an inclination angle between 10° and 70°.

In one embodiment, if the bevel angle of the third insulating sidewall 80s of the third insulating layer 80 is less than 10 degrees, the substantial thickness of the third insulating layer 80 will be reduced. Therefore, there may be a problem that it is difficult to ensure insulating properties.

In one embodiment, if the inclination angle of the third insulating sidewall 80s of the third insulating layer 80 is greater than 70 degrees, subsequent insulating layers and metal layers may not be able to cover completely, resulting in cracking of the film.

As shown in FIG. 9 and FIG. 10, the formation positions of one or a plurality of first openings 801 of the third insulating layer on the first light emitting unit 20a respectively correspond to one or a plurality of second openings 602a of the second insulating layer, and overlap with the second openings 502a of the first insulating layer.

As shown in FIG. 9 and FIG. 10, one or a plurality of second openings 802 of the third insulating layer on the second light emitting unit 20b overlap with the second openings 502b of the first insulating layer below, and do not overlap with the second openings 602b of the second insulating layer.

Fig. 11 is a top view of forming a first electrode pad and a second electrode pad disclosed by an embodiment of the present invention. Fig. 12 is a sectional view along the tangent line A-A' of Fig. 11. Fig. 13 is a sectional view along the tangent line B-B' of Fig. 11. Fig. 14 is a sectional view along the tangent line C-C' of Fig. 11. The light-emitting device 1 includes one or a plurality of first electrode pads 901 respectively covering one or a plurality of first openings 801 of the third insulating layer and respectively contacting one or a plurality of first upper electrodes 71a. The first electrode pad 901 is electrically connected to the second semiconductor layer 203 on the first light emitting unit 20 a through the reflective layer 40 and/or the contact electrode 30 .

The light emitting device 1 includes one or a plurality of second electrode pads 902 respectively covering one or a plurality of second openings 802 of the third insulating layer and contacting the second lower electrode 72b. The second electrode pad 902 is electrically connected to the first semiconductor layer 201 on the second light emitting unit 20b through the second lower electrode 72b formed in the second hole portion 200b and the second surrounding portion 204b.

The current injected through the first electrode pad 901 and the second electrode pad 902 passes through the first connection end 701 and the second connection end 702 of the connection electrode 70 so that the first light emitting unit 20a and the second light emitting unit 20b are connected in series.

The upper surface of the first electrode pad 901 or the second electrode pad 902 may be planar or non-planar. When the upper surface of the first electrode pad 901 or the second electrode pad 902 is non-planar, the upper surface of the first electrode pad 901 or the second electrode pad 902 has a surface profile corresponding to the surface profile of the first opening 801 of the third insulating layer and the second opening 802 of the third insulating layer, such as a strip-shaped, circular or stepped surface. As shown in FIG. 11 , the upper surface of the first electrode pad 901 or the second electrode pad 902 may include at least one concave portion and at least one protruding portion to surround the concave portion. The position of the recess corresponds to the positions of the first opening 801 of the third insulating layer and the second opening 802 of the third insulating layer, and the recess is located in the first opening 801 of the third insulating layer and the second opening 802 of the third insulating layer. The protruding part is located outside the first opening 801 of the third insulating layer and the second opening 802 of the third insulating layer, and the protruding part is located on an upper surface of the third insulating layer. There is a stepped surface between the protruding part and the concave part, wherein the stepped surface includes a step difference between 200 angstroms and 60000 angstroms, preferably between 1000 angstroms and 30000 angstroms, more preferably between 2000 angstroms and 20000 angstroms. The depressions and protrusions may be formed in a circular shape, or in a rectangular shape as shown in FIG. 1 .

In another embodiment of the present invention (not shown in the figure), the first electrode pad 901 and the second electrode pad 902 are a thin pad structure, respectively including a thickness smaller than that of the third insulating structure 80 . The first electrode pad 901 and the second electrode pad 902 include metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt) and other metals or alloys of the above materials. The first electrode pad 901 and the second electrode pad 902 can be composed of a single layer or multiple layers. For example, the first electrode pad 901 and the second electrode pad 902 may include a Ti/Au layer, a Ti/Pt/Au layer, a Cr/Au layer, a Cr/Pt/Au layer, a Ni/Au layer, a Ni/Pt/Au layer or a Cr/Al/Cr/Ni/Au layer.

In an embodiment of the present invention, the first electrode pad 901 includes a dimension that is the same as or different from that of the second electrode pad 902 , and the dimension may be a width or an area. For example, the top view area of the first electrode pad 901 or the second electrode pad 902 may be 0.8 times or more and less than 1 time the value obtained by adding the top view areas of the first electrode pad 901 and the second electrode pad 902 .

In an embodiment of the present invention (not shown), the first electrode pad 901 or the second electrode pad 902 respectively includes an inclined side surface, so the side view cross-sectional area of the first electrode pad 901 or the second electrode pad 902 can change along the thickness direction. For example, the side view cross-sectional area of the side away from the first electrode pad 901 or the second electrode pad 902 of the semiconductor stack is smaller than the side view cross-sectional area of the other side near the first electrode pad 901 or the second electrode pad 902 of the semiconductor stack.

In one embodiment of the present invention (not shown in the figure), when the light-emitting element 1 is mounted on the packaging substrate in the form of a flip chip, in order to increase the contact area between the first electrode pad 901 and the second electrode pad 902 and the packaging substrate, the side view cross-sectional area of the side away from the first electrode pad 901 or the second electrode pad 902 of the semiconductor stack is larger than the side view cross-sectional area of the other side of the first electrode pad 901 or the second electrode pad 902 close to the semiconductor stack.

The first electrode pad 901 or the second electrode pad 902 includes a thickness between 1-100 μm, preferably between 1.5-6 μm.

There is a gap between the first electrode pad 901 and the second electrode pad 902, and the gap includes a shortest distance of about 10 μm or more and a longest distance of about 250 μm or less. Within the above range, by reducing the distance between the first electrode pad 901 and the second electrode pad 902, the top view area of the first electrode pad 901 and the second electrode pad 902 can be increased, thereby improving the heat dissipation efficiency of the light emitting element 1, and avoiding a short circuit between the first electrode pad 901 and the second electrode pad 902.

FIG. 15 is a schematic diagram of a light emitting device 2 according to an embodiment of the present invention. The light-emitting element 1 in the foregoing embodiments is mounted on the first pad 511 and the second pad 512 of the packaging substrate 51 in the form of a flip chip. The first spacer 511 and the second spacer 512 are electrically insulated by an insulating portion 53 including insulating material. In flip-chip mounting, the side of the growth substrate opposite to the surface where the electrode pads are formed is set upward as the main light extraction surface. In order to increase the light extraction efficiency of the light emitting device 2 , a reflective structure 54 can be provided around the light emitting element 1 .

Fig. 16 is a schematic diagram of a light emitting device 3 according to an embodiment of the present invention. The light emitting device 3 is a bulb lamp including a lampshade 602 , a reflector 604 , a light emitting module 610 , a lamp holder 612 , a heat sink 614 , a connection portion 616 and an electrical connection element 618 . The light emitting module 610 includes a carrying portion 606, and a plurality of light emitting units 608 are located on the carrying portion 606, wherein the plurality of light emitting bodies 608 can be the light emitting elements 1 or light emitting devices 2 in the foregoing embodiments.

The various embodiments listed in the present invention are only used to illustrate the present invention, and are not intended to limit the scope of the present invention. Any obvious modifications or changes made by anyone to the present invention will not depart from the spirit and scope of the present invention.

1: Light emitting element

2: Lighting device

3: Lighting device

10: Substrate

10d: cutting lane

10s: Upper surface

20: Lighting unit

20a: the first light emitting unit

20b: the second light emitting unit

21: Ditch

21s: surface

200: hole

200a: the first hole

200as: inner surface

200b: the second hole

200bs: inner surface

201: the first semiconductor layer

202: active layer

203: the second semiconductor layer

204: Surrounding part

204a: The first surrounding part

204as: outer surface

2041a: the first inner recess

2042a: first outer recess

204b: The second surrounding part

204bs: External surfaces

2041b: the first inner recess

2042b: first outer recess

205:Semiconductor Platform

205a: The first semiconductor platform

205b: Second semiconductor platform

30: contact electrode

40: reflective layer

50: The first insulating layer

500: Opening of the first insulating layer

501a: the first opening of the first insulating layer

502a, 502b: the second opening of the first insulating layer

503a, 503b: the third opening of the first insulating layer

504a, 504b: the fourth opening of the first insulating layer

60: Second insulating layer

600: Second insulating layer opening

601a: the first opening of the second insulating layer

602a, 602b: the second opening of the second insulating layer

603a, 603b: the third opening of the second insulating layer

604a, 604b: the fourth opening of the second insulating layer

70: Connecting electrodes

701: the first connection terminal

7011: The first connection part

702: the second connection terminal

7022: The second connection part

703: the third connection terminal

7031: The third connection first end

7032: The third connection to the second end

71a: the first upper electrode

72a: the first lower electrode

72as: the outer wall of the first lower electrode

72b: the second lower electrode

72bs: second lower electrode outer wall 721b: second lower electrode recess

722b: second lower electrode protrusion

724b: Second bottom electrode extension

80: The third insulating layer

801: the first opening of the third insulating layer

802: the second opening of the third insulating layer

80s: third insulating sidewall

901: first electrode pad

902: second electrode pad

51: Package substrate

511: The first gasket

512: second gasket

53: Insulation part

54: Reflection structure

602: lampshade

604: Mirror

606: bearing part

608: Luminous body

610: Lighting module

612: lamp holder

614: heat sink

616: connection part

618: Electrical connection components

b1: lower surface

t1: upper surface

S: Outer wall

S1: first slope

S2: second slope

S3: The third slope

FIG. 1 is a top view of a trench and a hole formed in a semiconductor stack disclosed by an embodiment of the present invention.

Fig. 2 is a sectional view along the tangent line A-A' of Fig. 1.

FIG. 3 is a top view of forming a contact electrode and a reflective layer on a semiconductor stack disclosed by an embodiment of the present invention.

Figure 4 is a sectional view along the tangent line A-A' of Figure 3.

Fig. 5 is a top view of forming a first insulating layer and a second insulating layer disclosed by an embodiment of the present invention.

Fig. 6 is a sectional view along the tangent line A-A' of Fig. 5.

FIG. 7 is a top view of forming an upper electrode, a lower electrode and a connecting electrode on a semiconductor stack disclosed by an embodiment of the present invention.

Figure 7A is an enlarged view of part of Figure 7.

Figure 7B is a partially enlarged view of Figure 7.

Figure 8 is a sectional view along the tangent line A-A' of Figure 7.

FIG. 9 is a top view of forming a third insulating layer on the semiconductor stack disclosed by an embodiment of the present invention.

Figure 10 is a sectional view along the tangent line A-A' of Figure 9.

FIG. 11 is a top view of forming a first electrode pad and a second electrode pad on a semiconductor stack disclosed by an embodiment of the present invention.

Fig. 12 is a sectional view along the tangent line A-A' of Fig. 11.

Fig. 13 is a sectional view along the tangent line B-B' of Fig. 11.

Fig. 14 is a sectional view along the tangent line C-C' of Fig. 11.

FIG. 15 is a schematic diagram of a light emitting device 2 according to an embodiment of the present invention.

Fig. 16 is a schematic diagram of a light emitting device 3 according to an embodiment of the present invention.

none

1: Light emitting element

10: Substrate

10s: Upper surface

20: Lighting unit

20a: the first light emitting unit

20b: the second light emitting unit

21: Ditch

21s: surface

200: hole

200as: inner surface

200bs: inner surface

201: the first semiconductor layer

202: active layer

203: the second semiconductor layer

2041a: the first inner recess

2041b: Second inner recess

2042a: first outer recess

2042b: second outer recess

205:Semiconductor Platform

205a: The first semiconductor platform

205b: Second semiconductor platform

30: contact electrode

40: reflective layer

50: The first insulating layer

502a: the second opening of the first insulating layer

502b: the second opening of the first insulating layer

60: Second insulating layer

602a: the second opening of the second insulating layer

602b: the second opening of the second insulating layer

70: Connecting electrodes

701: the first connection end

702: the second connection terminal

703: the third connection terminal

71a: the first upper electrode

72a: the first lower electrode

72b: the second lower electrode

80: The third insulating layer

801: the first opening of the third insulating layer

802: the second opening of the third insulating layer

901: first electrode pad

902: second electrode pad

Claims (10)

A light-emitting element, comprising: a substrate including a surface; a first light-emitting unit and a second light-emitting unit located on the substrate, the first light-emitting unit and the second light-emitting unit each comprising a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; a trench located between the first light-emitting unit and the second light-emitting unit, and exposing the surface of the substrate; a first surrounding portion located on the first light-emitting unit, surrounding the first light-emitting unit and exposing the first semiconductor layer located on the first light-emitting unit; On the second light-emitting unit, surrounding the second light-emitting unit and exposing the first semiconductor layer on the second light-emitting unit; a connecting electrode includes a first connection end located on the first light-emitting unit and electrically connected to the first semiconductor layer of the first light-emitting unit, a second connection end located on the second light-emitting unit and electrically connected to the second semiconductor layer of the second light-emitting unit, and a third connection end located in the trench to connect the first connection end and the second connection end; an insulating layer includes a first opening below the first connection end and a second opening below the second connection end, wherein the light emitting Viewed from a top view of the element, the second opening includes an opening area larger than that of the first opening; and a first lower electrode is located on the first surrounding portion of the first light-emitting unit and the second semiconductor layer, wherein on a side adjacent to the trench, the first opening of the insulating layer is covered by the first lower electrode. The light-emitting element described in item 1 of the scope of the patent application further includes a first upper electrode located on the second semiconductor layer of the first light-emitting unit, wherein viewed from a top view of the light-emitting element, the first upper electrode is surrounded by the first lower electrode, and viewed from a side view of the light-emitting element, part of the insulating layer is located between the second semiconductor layer and the first lower electrode. The light-emitting device as described in item 2 of the scope of the patent application, wherein on one side adjacent to the trench, the insulating layer further includes a plurality of first openings of the first insulating layer located on the first surrounding portion and covered by the first lower electrode. The light-emitting device as described in claim 2 of the patent application further includes a second lower electrode located on the second semiconductor layer of the second light-emitting unit and electrically connected to the first semiconductor layer of the second light-emitting unit by contacting the second surrounding portion. The light-emitting device as described in claim 4 of the patent application, wherein the insulating layer further includes a plurality of third openings located on the second surrounding portion and covered by the second lower electrode. The light-emitting device as described in claim 4 of the patent application further includes a first electrode pad located on the first light-emitting unit and contacting the first upper electrode, and a second electrode pad located on the second light-emitting unit and contacting the second lower electrode. The light-emitting device as described in claim 4 of the patent application, wherein the second lower electrode includes a second lower electrode concave portion for accommodating the second connection terminal. The light-emitting device as described in claim 1 of the patent application, wherein the second connection end includes a second width greater than the first connection end includes a first width. The light-emitting device as described in claim 1 of the patent application, wherein the second connection end includes a second width that is smaller than the first connection end includes a first width. According to the light-emitting device described in item 1 of the patent claims, wherein the second connection end includes a second width that is the same as the first connection end includes a first width.