GB2178545A - Offset compensation - Google Patents

Description

GB 2178545 A 1

SPECIFICATION

Power metering system Technical Field

The invention relates generally to circuits for producing one or more signals proportional to power or to another selected measurement parameter, and more particularly to an im- proved power metering circuit and method which employs delta-minus-sigma modulation and an offset compensation system.

Background Art

Meters which accurately measure electric en- ergy flowing on a line are an essential part of an electric utility system The most common type of meter used by the electric utility in- dustry today is the rotating disc meter, which in its basic form is accurate and reliable but provides only limited information to the utility about power usage In addition to total power consumption in kilowatt-hours, utilities often need to measure other parameters to properly determine the cost of supplying certain loads.

Some highly reactive loads, for example, are more expensive to supply because they induce a current/voltage phase mismatch known as power factor To determine power factor, utili- ties have devised certain standard power mea- surements Two widely used measurements are VARS (for reactive volt-amperes) and Q.

Both are power measurements proportional to the product of line current and voltage, with the voltage phase lagging the current by 90 for VARS, and by 600 for Q Together with overall power consumption, readings of VARS and Q allow the utility to measure power fac- tor for which a penalty is usually charged.

Another parameter of interest to utilities is po- larity, or the direction of power flow, since some applications both consume power and feed power back into the distribution system.

There is a continuing need in the electric util- ity industry for metering systems which are able to measure such parameters as VARS, Q and polarity, in addition to total power con- sumption.

Various electronic metering systems have been designed or proposed to replace the ro- tating disc meter Examples of prior art elec- tronic metering systems include those shown in the following patents: U S 3,875,508; U S.

3,955,138 and U S 4,182,983 Those sys- tems all employ modulators which produce a pulse-width modulated signal proportional to either current or voltage, and then use time- division or markspace multiplication, which gates or reverses the polarity of the other signal, to obtain a product signal The product signal pulses vary in amplitude with respect to one analog value (current or voltage), and var- ies in width with respect to the other analog value A low pass filter extracts the DC com- ponent of the product signal, which is propor- tional to power consumption It would be ad- vantageous to have a highly accurate metering system which is electronic and which is capable of producing power readings continu- ously in both kilowatt-hours and VARS or Q, at the lowest possible cost It would also be advantageous if such a metering system could separately measure net power flow in each direction The metering system should also be substantially free of errors due to voltage off- sets in the active circuit elements The system should therefore more advantageously include an offset compensation system which can economically compensate for errors in multiple amplifier elements.

According to the invention of our copending application No 8507289 (serial No 2154329) from which the present Application is divided and which has a disclosure substantially identi- cal with that of the present application there is provided a metering system for measuring electric power carried on a line, comprising:

means for monitoring current and voltage sig- nals on said line, including first signal means for producing a first analog signal proportional to one of said current and voltage signals and second signal means for producing a second analog signal proportional to the other of said current and voltage signals; modulator means for converting said first analog signal to a first modulated signal changeable between two levels at predetermined times, with said first modulated signal having an average level over time which is first clock proportional to said first analog signal; and multiplying means re- sponsive to said first modulated signal and said second analog signal for producing a pro- duct signal indicative of the power carried on said line.

According to the present invention there is provided a metering system for measuring electric power carried on a line, which in- cludes means for monitoring current and vol- tage signals on said line and for producing a first analog signal proportional to one of said current and voltage signals and a second an- alog signal proportional to the other of said current and voltage signals, means for multi- plying said first and second analog signals to- gether to produce a product signal propor- tional to the power transported on the line, and means for converting said product signal to an output signal which is proportional over time to the value of said product signal and to the power carried on said line, and which includes N number of amplifier elements each having a plurality of inputs in at least one of said monitoring, multiplying and converting means, an offset compensation system for substantially eliminating errors due to voltage offset between selected inputs of each of said N amplifier elements, said offset compensation system comprising: N number of offset sto- rage elements one of which is connected re- spectively to a selected first input of each GB 2178545 A 2 said amplifier elements for receiving a com- pensating voltage which substantially reduces the offset error at a selected second input of the amplifier element, wherein any difference between said compensating voltage and the voltage offset of the amplifier element is an offset error voltage appearing at said second input, and including a nulling circuit to be coupled sequentially to each of said N ampli- fier elements and to the offset storage ele- ment associated therewith such that each said amplifier element sequentially becomes the se- lected amplifier element being offset compen- sated, said nulling circuit first being coupled to said second input of said selected amplifier element during an intermittent transfer period to store said offset error voltage and then being coupled to said offset storage element coupled to said first input of said selected amplifier element to transfer charge to said offset storage element during an intermittent charging period following said transfer period, said offset compensation system including means for sequentially providing transfer and charging periods for each of said N amplifier elements such that offset errors in said meter- ing system are substantially eliminated.

Attention is drawn to our copending applica- tions Nos 86, 86 and 86 all divided from the above mentioned application No.

8507289 and having a disclosure substantially identical therewith.

The system also may include an offset com- pensation system which corrects for voltage offsets in the various operational amplifiers of a metering system to eliminate offset errors and provide high accuracy The offset com- pensation system described will correct for voltage offset between the inputs of N ampli- fier elements The offset compensation sys- tem includes N offset storage elements which are connected respectively to one input of each of the amplifier elements for receiving a compensating voltage which substantially re- duces the offset error at the other input of the amplifier element Any difference between the compensating voltage and the voltage offset of the amplifier element is termed an error voltage, which appears at the other amplifier input The system includes a nulling circuit which can be connected sequentially to each of the N amplifier elements and to the offset storage element associated therewith so that each of the amplifier elements sequentially be- comes the selected amplifier element being offset compensated The nulling circuit first is connected to the other input of the selected amplifier element during an intermittent trans- fer period to determine the error voltage.

Then the nulling circuit is connected to the offset storage element connected to the one input of the selected amplifier element during an intermittent charging period which follows the transfer period The offset compensation system includes means for sequentially provid- ing the transfer and charging period for each of the N amplifier elements sucht that offset errors in the metering system are substantially eliminated.

Brief Description of the Drawings

Figure 1 is a schematic block diagram of a metering system for measuring power of a line according to the present invention.

Figure 2 is a schematic circuit diagram of the first modulator portion of the metering system shown in Fig 1.

Figure 3 is a schematic circuit diagram of the first output convertor portion of the met- ering system shown in Fig 1.

Figure 4 is a series of graphical illustrations, designated Figs 4 a through 4 g, showing cer- tain selected internal and output signals produced during the operation of the metering system of Figs 1 through 3.

Figure 5 is a series of graphical illustrations, designated Figs 5 a through 5 i, showing vari- ous internal and output signals produced by the convertor of Fig 3, during the measure- ment of signals of different polarities.

Figure 6 is a schematic circuit diagram of an alternative embodiment modulator for use in the subject power metering system which pro- vides a phase lead in the modulated output signal.

Figure 7 is a series of graphical illustrations, designated Figs 7 a through 7 g, showing cer- tain selected internal and output signals produced by the Fig 6 modulator.

Figure 8 is a schematic block diagram of a metering system according to the present in- vention which includes apparatus for produc- ing measurements of VARS and Q.

Figure 9 is a schematic diagram of a signal multiplier which can be used in the metering system of Fig 8 and which includes digital circuitry for phase adjustment to enable the production of VARS and Q measurements.

Figure 10 is a series of graphical illustra- tions, designated Figs 1 Oa through 1 Oh, showing certain selected internal and output signals produced in the Fig 9 multiplier.

Figure 11 is a schematic diagram showing further details of the digital phase adjustment circuitry of Fig 9.

Figure 12 is a series of graphical illustra- tions, designated Figs 12 a through 12 d, showing a selected phase adjustment of modulated signal produced by the multiplier of Fig 9.

Figure 13 is a schematic diagram of one embodiment of a voltage offset compensation system for use in the present invention.

Figure 14 is a graphical illustration of the change in error voltage produced by the Fig.

13 compensation system.

Figure 15 is a schematic diagram of a vol- tage offset compensation system of the type shown in Fig 13 for an entire power measur- ing system.

GB 2178545 A 3 Figure 16 is a timing diagram illustrating the operation of the offset compensation system of Fig 15.

Figure 17 is a schematic diagram of a sec- ond embodiment modulator for use in the Fig.

1 power measuring system.

Figure 18 is a series of graphical illustra- tions, designated Figs 18 a through 18 e, showing various signals produced by the Fig.

17 modulator.

Figure 19 shows the Fig 17 modulator with an alternative embodiment voltage offset com- pensation system.

Figure 20 is a timing diagram showing the control signals for operating the voltage offset compensation system of Fig 19.

Figure 21 is an alternative embodiment of a modulator for use with the Fig 1 measuring system which includes voltage offset compen- sation circuitry.

Figure 22 is a timing diagram showing the control signals for operating the offset com- pensation system of Fig 21.

Figure 23 shows an alternative embodiment modulator and associated dual polarity output circuitry.

Figure 24 is a series of graphical illustra- tions, designated Figs 24 a through 24 j, showing various signals produced by the Fig.

23 modulator and associated output circuitry.

Best Mode For Carrying Out The Invention

Referring to Fig 1, the metering system of the present invention is schematically illus- trated as a means for measuring the electrical power carried on a power line 10, from a source 12 to a load 14 The current on line is indicated generally as 1,, and the voltage as V, The system includes a signal monitor- ing and conditioning means such as transformers 16 and 18, for monitoring V, and I, respectively Transformer 16, designated the first signal means, produces a first analog sig- nal 1 Al proportional to V, on line 20 Transfor- mer 18, designated the second signal means, produces a second analog signal 1 A 2 propor- tional I, on line 22 A shunt resistance 24 is connected across the secondary winding of transformer 18, through which most of the current on line 22 flows Shunt resistance 24 provides a low impedance current path and may be selected to control the overall range of the current signal 'A 2 on line 22.

The metering system and method of the present invention operates to multiply together the first and second analog signals 'Al and 1 A 2 ' carried respectively on lines 20 and 22, and then to convert the multiplied product signal to a suitable digital form Broadly, this is accomplished by modulating one of the signals and then gating, or switching, the other of the signals to yield a composite or product signal having an average value proportional to power It will be understood by those skilled in the art that either the current or voltage could be modulated, and the resultant modu- lated signal used to gate the other of the two analog signals, to produce the product signal.

Accordingly, the designation of the first and second analog signals as the voltage and cur- rent signals, respectively, could be reversed without altering the fundamental operation of the metering circuit shown in Fig 1 Similarly, the designations for the first and second mon- itors could likewise be reversed.

The metering system provides a multiplying means for multiplying signals I Al and 'A 2 to- gether to produce a product signal which is proportional to the power transported on the line To provide the necessary multiplication, the voltage signal 'Al is first supplied to a first modulator circuit 30 Modulator 30 constitutes a modulator means for converting the analog voltage signal 'Al to a first modulated signal, which is changeable between two levels at predetermined clock intervals In accordance with the principles of delta-minus-sigma modu- lation, the first modulated signal output has an average level over any sufficient interval which is proportional to the first analog signal sup- plied to modulator input 32.

Referring to Fig 2, the analog (voltage) sig- nal 1 A 1, is supplied to a summing node 36, through an impedance 38 Modulator 30 in- cludes modulator feedback means for produc- ing a feedback signal IF, which is also supplied to summing node 36 IF is controlled by the modulator output, called the first modulated signal, which appears on line 34 One or the other of a pair of reference sources V 1 + and V 1 are alternately connected to summing node 36 through an impendance 40 in re- sponse to the level of the first modulated sig- nal Feedback signal IF switches between the positive and negative reference sources in a manner which balances the first analog signal I Al over time Instantaneous differences betwen IF and the first analog signal result in a difference signal 1 d,H out of summing node 36.

The instantaneous difference between the in- put and feedback signals, namely Id,,,, is inte- grated and measured by a modulator measur- ing circuit 42 Measuring circuit 42, includes an active integrator having a capacitor 44 as the feedback element of an inverting opera- tional amplifier 46 The signal at amplifier out- put 48 ramps up or down, depending on the polarity of Id,, The integrated signal at 48 is compared against a modulator threshold level by a comparator 50, which goes high when the signal is above the modulator threshold level and low when the signal is below the modulator threshold level.

The output of comparator 50 is supplied to the D input of a modulator bistable circuit 52.

The Q output of bistable circuit 52 is the first modulated signal Bistable circuit 52 changes only at a predetermined first clock intervals which are determined by an external clock A suitable clock for this purpose is provided by 4 GB 2178545 A 4 a conventional oscillator 54 and frequency di- vider circuit 56, shown in Figs 1 and 2 For simplicity, the time interval between the pulses produced by frequency divider 56 will be referred to as the first clock Bistable cir- cuit 52 has a O output as well as Q, with O being the inverse of Q Both the a and Q outputs are used to control feedback signal IF by operating a pair of switches 58 and 60, respectively Since Q and O are understood to be the inverse of one another, only the Q output is referred to herein as the first modu- lated signal It should be understood, how- ever, that both the Q and O outputs contain the information represented by the term "first modulated signal", and line 34 designates the lines carrying both the Q and a signals.

Because the first modulated signal is output through bistable circuit 52, the first modulated signal on line 34 is changeable between two levels at the predetermined first clock inter- vals Although the level may not change at each clock interval, the modulator circuit pro- vides that when the first modulated signal does change levels, such change occurs only at the predetermined first clock intervals, and at no other times Changes between the high and low levels of the first modulated signal produce simultaneous switching of switches 58 and 60, and corresponding reversals in the polarity of feedback signal 1 F to summing node 36 As the integrated difference signal ramps either up or down across the threshold level of comparator 50, changes in the level of the output of the comparator are produced At each clock interval, bistable circuit 52 determines whether the output of comparator 50 has changed, and if so, produces a corre- sponding change in the Q and O outputs The magnitude of the analog input signal causes a direct proportional change in the amount of time the first modulated signal is at a given level Consequently, the first modulated signal has an average level or amplitude which lies either at or between its two levels and, over any sufficient interval, such average amplitude is proportional to the analog input signal.

As an example of the operation of modula- tor 30, if the input signal at input 32 is zero, the Q output of bistable circuit 52 will be high exactly the same amount of time it is low, producing an average level exactly midway be- tween the high and low levels of Q If the input signal at input 32 has a positive value, the positive current into summing node 36 must be balanced by a larger negative current supplied to the summing node by negative ref- erence V 1 -, through switch 58 Conse- quently, Q will be low proportionately longer than it is high and switch 58 will be closed and switch 60 will be open a greater amount of time than vice versa If the input signal is negative, the positive feedback reference will need to be supplied more of the time in order for IF to balance the input signal, and Q will be high more than it is low It is a feature of the modulator of the present invention that Q can remain high or low for however long it takes IF to balance the input signal at the summing node.

To produce a current signal for multiplication with the modulated voltage signal, the system includes means for providing inverted and non-inverted representations of the line current I Referring to Fig 1, the current analog signal 1 A 2 is first supplied to a gain amplifier 70, after which the signal is supplied to a signal inver- ter circuit 72 The illustrated inverting circuit includes an operational amplifier 74 and gain setting resistors 76 and 78 The amplified sig- nal 1 A 2 is supplied to the inverting input of amplifier 74, which is configured to produce a gain of 1 The inverted signal is then sup- plied to one of two switches, which together form first gating means 80 The inverted sig- nal goes to switch 82, and a second line 84 carries the non-inverted amplified signal, 1 A 2, to switch 86 It will be understood that a suit- able center tap transformer could be used in place of second transformer 18, in which case the signals to switches 82 and 86 could be supplied directly from the transformer.

The Q and Q outputs of modulator bistable circuit 52 are used to operate switches 82 and 86, to gate the second analog signal 1 A 2 in response to the first modulated signal Since Q is the inverse of Q, switches 82 and 86 are switched in alternate fashion, such that the output of gating means 80, at 88, is an an- alog signal switched in a modulated manner between positive and negative polarities Such a gating operation is generally termed time division or amplitude-markspace modulation.

Switches 82 and 86 accomplish the multiplica- tion of the two analog signals representing the current and voltage of the power carried on line 10 The resultant signal, termed a product signal, appears at first gate output 88, and is proportional to the power carried on power line 10.

As shown in Fig 1, the product signal out- put from the first gating means is supplied to a first convertor circuit 90 The convertor cir- cuit converts the product signal to a first out- put signal, on line 92, which is changeable between the two levels at predetermined con- vertor clock intervals in a manner proportional to the product signal Convertor 90 operates essentially as a low pass filter which extracts the DC component or average value of the product signal The resultant first output signal is proportional to the power carried on line 10.

Referring to Fig 3, convertor 90 is essen- tially a delta-minus-sigma modulator of type similar to modulator 30, which is designed to produce separate modulated output signals proportional to each polarity of the input sig- nal To simplify the description, convertor 90 and its operation will initially be described GB 2178545 A 4 GB 2178545 A 5 with respect to a first polarity of operation.

The components within box 94 encompass all the elements used in single polarity operation.

In the following example it will be assumed that the product signal to be converted is pre- dominantly positive, which will be assumed to correspond with power flow on line 10 from source 12 into load 14 As in the modulator 30, the input signal to convertor 90, desig- nated l, (product signal), is initially supplied to a summing node 96 through an impendance A feedback means supplies a second sig- nal 12 to the summing node from one of a plurality of reference sources For positive po- larity opearation, the reference sources will al- ternate between a negative reference source 98 (VR-), supplied through a switch 100, and a ground connection 102, supplied through a switch 104 Since only positive values of the product signal are being considered, switching 12 between ground and a negative value will be sufficient to balance the product signal at summing node 96, over time.

As previously described for modulator 30, any difference between product l, and 12 is a difference signal, which is supplied to a mea- suring circuit 106 The measuring circuit inte- grates the difference signal and compares the difference signal to a first threshold level The preferred embodiment measuring circuit shown in Fig 3 includes an active integrator 107 consisting of amplifier element 108, and a capacitor 110 as a feedback element The vol- tage at amplifier output 112 ramps upward or downward, depending on the polarity of the difference signal at summing node 96 The integrated difference signal at 112 is supplied to a first comparator 114, which has a thresh- old set at a selected first threshold level.

When the integrated difference signal at 112 is above the first threshold level, the output of comparator 114 is high When the integrated difference signal is below the first threshold level, the output of comparator 114 is low.

The comparator output, termed a first con- trol signal, is supplied to the D input of a bistable circuit 118, by way of line 116 The Q output of bistable circuit 118 is changeable only at predetermined convertor clock inter- vals, which are preferably longer than the first clock intervals for modulator 30 The conver- tor clock intervals can be produced by adding a second frequency divider 120 to first clock 56 The time intervals between the pulses produced by frequency divider 120 will be re- ferred to as convertor clock intervals, and the frequency divider will be referred to as the convertor clock The Q output of bistable cir- cuit 118 is the first output signal, which con- trols switches 100 and 104 to determine the operation of the feedback system which sup- plies second signal 12 to summing node 96.

Switch 104 is operated through a gate 122, which outputs a high signal to close the switch only when both inputs 124 and 126 are low Gate 122, as shown, is a conven- tional negative AND gate During periods of positive product signals, input 126 will remain low, as will be described below Conse- quently, whenever Q is high, switch 100 is closed, connecting VR to summing node 96, and when Q is low, switch 100 is open and switch 104 is closed.

The operation and method of the metering system of the present invention will now be described with reference to Figs 1-4 For simplicity, it will be assumed that power on line 10 flows predominantly in the positive direction The voltage on line 10 is shown in Fig 4 a as a sinusoidal AC waveform Current 1, is shown in Fig 4 f as an increasing value, represented by curve 128 The first step is for transformers 16 and 18 to monitor the current and voltage signals and to produce analog signals IA, and IA 2 which are propor- tional to line voltage and current, respectively.

One of the analog signals, voltage signal 1 A 1 in the preferred embodiment, is then supplied first to first modulator 30 Fig 4 c shows the integrated difference signal produced within modulator 30 by the delta-minus-sigma modu- lation technique described above The inte- grated difference signal is supplied to measur- ing circuit 42 Fig 4 b illustrates the first clock intervals produced by first clock 56 As can be seen, the slope of the integrated difference signal in Fig 4 c changes only at the predeter- mined clock intervals determined by the first clock signal Since bistable circuit 52 clocks on the leading edge of each upwardly moving pulse, the predetermined first clock intervals are shown to begin at, the points identified as a, b, c, d, etc in Fig 4 b The integrated difference signal is then supplied to compara- tor 50 Line 130 in Fig 4 c represents the modulator threshold level in comparator 50.

Note that the integrated difference signal re- verses slope at the beginning of each clock interval after threshold 130 has been crossed.

The output of comparator 50 is shown in Fig.

4 d Whenever the integrated difference signal is below threshold 130 the comparator output is low and when the integrated difference sig- nal is above threshold 130 the comparator output is high The comparator output is then supplied to the D input of bistable circuit 52, which produces the Q, or first modulated sig- nal output, illustrated in Fig 4 e The Q output is the result of modulating the voltage signal and is changeable between two levels at the predetermined first clock intervals.

Because the bistable circuit is changeable only at the predetermined clock intervals shown in Fig 4 b, the changes in Q slightly lag changes in the comparator output shown in Fig 4 d Depending on the level of accuracy required in the signal multiplication system, it may be desirable tocompensate for the slight lag in the modulated signal introduced by bistable circuit 52 Such correction can be ac- GB 2178545 A 6 complished by inserting an RC network in line to introduce a small phase lead in signal IA 1 as it enters modulator input 32 Another tech- nique would be to induce a slight lag in the current analog signal 'A 2 l A third alternative, utilizing a delta-minus-sigma modulator having digital phase lead circuitry will be subsequently described The phase adjustment introduced, which will only be a fraction of one first clock interval, should be the average of the delay induced by the lag of O relative to the com- parator output.

Fig 4 f illustrates equal and opposite analog signals proportional to line current 1, Line 128 is representative of a growing current signal and line 129 is the inverse signal produced by inverter 72 The next step is to gate the cur- rent analog signal using gating means 80 The output of gating means 80 is the product sig- nal, curve 131, shown in Fig 4 g Curve 131 is generated by switching between signals 128 and 129, in response to the first modu- lated signal shown in Fig 4 e The average level or DC component of curve 131 is repre- sented by line 132 of Fig 4 g.

In the example given, power is assumed to be flowing predominantly in one direction, into load 14 Consequently, the product signal 131 shown in Fig 4 g is predominantly of a posi- tive polarity, represented by line 132 It will be assumed, for the purpose of describing the operation of convertor 90 below, that the pro- duct signal has a predominant and average value which is positive Although the actual polarity of the product signal is a matter of design choice, the product signal will be pre- dominantly of a first polarity when power on line 10 is of a first polarity, with power flow in one direction, and will be predominantly of a second polarity when power on line 10 is of a second and opposite polarity, with the power flowing in the other direction.

The next step is to convert the product sig- nal l, to a first output signal changeable be- tween two levels at predetermined intervals in a manner proportional to I Reference will be made to Figs 3, 4 and 5 Product signal Is, as shown in Fig 4 g, is supplied to convertor 90.

Both l, and second signal 12, are supplied to summing node 96, where the instantaneous difference is integrated in integrator 106 The time constant of integrator 106 is selected to be long in comparison to the switching fre- quency of first modulator 30 Convertor 90 can therefore act as a low pass filter, re- sponding only to the DC component, or aver- age value, of product signal I For this rea- son, l is depicted in Fig 5 a as a smooth analog curve, although it will in fact vary in the manner shown in Fig 4 g Fig 5 a shows only the average value of I The time scale of Fig 5 a is considerably compressed, compared with the scale in Fig 4 g For the purpose of illustration, it will be assumed that interval 134 of Fig 5 a is equivalent to the entire length of curve 132, shown in Fig 4 g Fig 5 b shows the convertor clock intervals produced by clock 120.

Considering only positive power flow, illus- trated between to and t 1, in Fig 5 a, integrator 106 will output an integrated difference signal (IDS) as shown in Fig 5 c The integrated dif- ference signal ramps up and down around the first threshold level TL 1 of comparator 114.

The integrated difference signal (IDS) is sup- plied to comparator 114, where it is com- pared to first threshold level TL 1 Comparator 114 outputs a control signal 133 on line 116 as shown in Fig 5 d The next signal gener- ated is the first output signal shown in Fig.

e, which is output through bistable circuit 118 Control signal 133 changes levels de- pending on the level of the integrated differ- ence signal relative to threshold TL 1 When IDS is above TL 1, signal 133 is high and when IDS is below TL 1, signal 133 is low.

The next step is to output the first output signal shown in Fig 5 e through first bistable circuit 118 The first output has an average level proportional to a first polarity of power on line 10 over any sufficient interval It is changeable only at the predetermined conver- tor clock intervals illustrated as w, x, y and z in Fig 5 b.

Single polarity operation of convertor 90 in- volves switching the feedback signal 12 be- tween first reference source 98 and a second reference source 102, depending on the level of the first output signal (Fig 5 e) Since the second reference source 102 is a ground con- nection, the porition of convertor 90 thus far described will not accommodate negative power flow on line 10 When power flow (l,) goes negative, as it does between times t, and t 2 in Fig 5 a, additional circuitry in convertor 90 is employed Referring to Fig 3, con- vertor 90 includes a second comparator 140 which receives the output of integrator 107.

Comparator 140 has a second threshold level TL 2 which is different from the first threshold level of comparator 114 The threshold levels should be set far enough apart to accommo- date the widest anticipated variations in the intregrated difference signal output from inte- grator 107, without crossing the threshold levels of both comparators simultaneously.

The integrated difference signal is supplied to the non-inverting input of comparator 114 and to the inverting input of comparator 140, so that their outputs will be of opposite polarity.

The output of comparator 140 goes high when the integrated difference signal is below the second threshold level in comparator 140 and goes low when the integrated difference signal is above the second threshold level in comparator 140.

The output of comparator 140 is supplied to the D input of a second bistable circuit 142 Second bistable circuit 142 outputs a second output signal from its Q output The v GB 2178545 A 7 second output signal is at one of two levels, depending on the level of the integrated differ- ence signal relative to the second threshold level at each of the convertor clock intervals.

The second output signal is supplied to input 126 of negative AND gate 122 and to a switch 146 for connecting a third reference source VR+ to summing node 96 The feed- back signal 12 is thus governed by the level of the second output signal, which has an aver- age level proportional to the second polarity power carried on power line 10.

Second polarity operation of convertor 90 will be described with reference to Figs 3 and 5 After time t, the direction of power flow reverses and product signal I, begins drawing charge from summing node 96 Referring to Fig 5 c, just prior to time t, the integrated difference signal is descending, meaning that the negative reference source VR is con- nected to the summing node through switch At the clock pulse following the crossing of the first threshold level TL 1, switch 100 will open and switch 104 will close, connect- ing the summing node to ground Since the product signal l, is negative after t, the inte- grated difference signal will continue integrat- ing downward until reaching the second threshold level TL 2 of comparator 140, when its output 135 will go high (see Fig 5 g) At the next comparator clock interval after con- vertor 140 goes high, the Q output of bistable circuit 142 (the second output signal) will go high, as shown in Fig 5 h When the second output signal goes high, a switch 148 con- nected to third reference source 146 (VR+) is closed The third reference source supplies a positive current 1 I to summing node 96 to counterbalance the negative product signal l, and drive IDS back across TL 2 When TL 2 is crossed, signal 135 again goes low, causing the second output signal to go low at the next clock interval During second polarity op- eration the first output signal (Fig 5 e) remains low and, whenever the second output signal (Fig 5 h) is low, both inputs to gate 122 are low and its output goes high When the out- put of gate 122 goes high, switch 104 is closed and the ground connection reference source 102 is connected to summing node 96 When switch 104 is closed, IDS is al- lowed to recross TL 2 in the other direction.

During the interim between times t, and t 2, when the power flow is negative, the inte- grated difference signal is maintained in the vicinity of second threshold level TL 2.

The convertor 90 shown in Fig 3 is pro- vided with three different reference sources, the second of which is a connection to the common ground for the metering circuit Be- cause of the configuration of circuit elements, the ground connection is used whenever the integrated difference signal is in the region be- tween the first and second thresholds TL 1 and TL 2 It is not essential that the second reference source be a ground connection Se- parate positive and negative reference sources could be used for each polarity of operation, if desired In such a case, the first and second reference sources would be used to supply the second signal 12 to summing node 96 when the product signal l, is of a first polarity and separate third and fourth reference sources could then be used to supply the sec- ond signal 12 to summing node 96 when pro- duct signal I, is of the other polarity In prac- tice, the selection of the values for the refer- ence sources is governed by the necessity of maintaining the integrated difference signal in the vicinity of the threshold level of the com- parator in use The magnitudes and polarities of the reference sources are otherwise entirely a matter of design choice.

Using reference sources in converter 90 which include at least one ground connection improves the overall accuracy of the modu- lated signals output While variations may oc- cur in the positive and negative voltage reference sources, the ground connection remains fixed If one or both of the positive and nega- tive reference sources is above or below its correct value, an error will be at one level slightly longer or shorter than it should be, since during the time the voltage reference source supplieds the feedback signal it will supply slightly too much or too little current.

The closer the input signal is to ground (zero) the smaller will be the error Equal and oppo- site reference sources, such as those used in the feedback system of modulator 30, have a greater potential for error if there is mismatch between the reference voltages V 1 + and V 1 - Since the feedback system of modulator always switches between V 1 + and V 1-, any error resulting from a reference voltage mismatch will tend to cause the modulated output to be at one or the other level an incorrect amount of time regardless of the magnitude of the input signal This does not present a problem in the case of modulator because it is modulating the line voltage signal, which generally varies by only a small amount Accuracy, therefore, need only be maintained over a narrow range Converter 90, however, requires greater accuracy because of the wide variations in the product signal repre- senting line power For this reason, the separ- ation of the convertor operations between positive and negative polarities of power has distinct advantages Since only one polarity is measured by each comparator, the reference sources can use a ground connection to pro- vide the feedback signal, improving overall convertor accuracy The information provided about power flow of each polarity is also de- sirable since it provides additional data about the nature of the load and its power require- ments.

The first and second output signals on lines 92 and 144 from convertor 90 (see Fig 1) GB 2178545 A 8 are changeable between two levels at the convertor clock intervals To provide a suitable digitized output in which pulse density is pro- portional to power flow, a system for convert- ing the output signals to pulse trains is pro- vided Referring to Figs 1 and 5, the first and second output signals are supplied to respec- tive first and second AND gates 150 and 152 A second input to the AND gates is supplied from convertor clock 120 Fig 5 f shows the pulse train produced for first polar- ity power from AND gate 150 The pulse train has a pulse density proportional to the magni- tude of power flow in one direction on line 10 Similarly, for power flow in the opposite direction, Fig 5 i shows a pulse train for sec- ond polarity power from AND gate 152 Vari- ous means are available for processing the first and second digital output signals shown, respectively, in Figs 5 f and 5 i For example, it would be convenient to supply the digital sig- nals to a counter means for counting the posi- tive and negative polarity pulses The counter could then output a display, or record total power consumption Counter 154 is illustrative of such a display concept If, in addition, a gate signal is supplied to counter 154, mea- surements of power in appropriate units, such as kilowatts, could be readily obtained Sepa- rate readings of power flow in each direction could also be obtained.

As previously noted since bistable circuit 52 (Fig 2) is changeable only at a predetermined clock intervals, a slight lag is introduced in the modulated output signal Fig 6 shows a novel delta-minus-sigma modulator 30 ' having digital phase lead circuitry to compensate for the phase lag Like elements in the Fig 2 and Fig.

6 modulators are designated by like reference numerals It should be noted that such digital phase lead circuitry has applications other than power metering systems Moreover, if desired, phase lead can be provided which is more than sufficient to compensate for the phase lag caused by the output bistable 52 of Fig.

2.

The modified modulator 30 ' of Fig 6, like the modulator of Fig 2, includes a bistable circuit 52 controlling a source of feedback cur- rent IF through switches 58 and 60 A summ- ing node 36 receives the input signal 'Al through input resistor 38 Instantaneous differ- ences between the feedback and input signals are represented by Id,,, and that difference sig- nal is measured by measuring circuit 42 The control signal output from comparator 50 is high when the integrated difference signal is above the threshold of the comparator and is low when the integrated difference signal is below the threshold.

Modulator 30 ' differs from modulator 30 in Fig 2 in that it includes a digital shifter be- tween measuring circuit 42 and bistable circuit 52 The digital shifter introduceds a time delay in the control signal output from comparator In Fig 6, the digital shifter is a bistable circuit 59, which receives the control signal output from the comparator at its D input For the purposes of the example given below, bis- table circuit 59 is clocked at the same rate as bistable circuit 52, but one-half clock interval out of phase.

Operation of the modulator shown in Fig 6 to achieve phase lead in the modulated output signal will be described with reference to Fig.

7 Input signal IA, to modulator 30 ' is shown in Fig 7 a The output of first clock 56 is shown in Fig 7 b First clock 56 also supplies the signal to bistable circuit 59 through an inverter 57, and the second clock signal is shown in Fig 7 c If IA 1, is positive at clock pulse a and the Q output of bistable circuit 52, shown in Fig 7 g, is initially high, IF will be positive into summing node 36 That will pro- duce a positive d Id, which is supplied to the inverting input of integrating amplifier 46, causing the integrated difference signal at po- int 47 to intially ramp downward, at 21 of Fig 7 d Line 22 in Fig 7 d represents the threshold of comparator 50 When the inte- grated difference signal crosses threshold 22, the control signal shown in Fig 7 e goes from high to low Assuming bistable circuit 59 clocks on upwardly moving pulses a', b', c', d', e', etc, the output of bistable circuit 59 will go from high to low at clock pulse a'.

The output of bistable circuit 59 (Q') is re- ferred to herein as the delayed control signal, which is subsequently supplied to the D input of bistable circuit 52 Fig 7 f shows the de- layed control signal and Fig 7 g shows the O output of bistable circuit 52 When Q' goes from high to low, the Q output of bistable circuit 52 will go from high to low at its next clock pulse b The change in Q opens switch and closes switch 58, causing IF to go negative The integrated difference signal then ramps upward, crossing comparator threshold 22 and again causing the control signal to go high At clock pulse d' of the second clock, the Q' output of bistable circuit 59 again goes high That causes the Q output of first bista- ble circuit 52 to go high at its subsequent clock pulse e.

The process described above will continue, with the Q output of bistable circuit 52 pro- viding the signals for controlling the feedback loop of the modulator Assuming the time de- lay introduced by the digital shifter repre- sented by bistable circuit 59 is not large enough to create instability in the feedback loop, modulator 30 ' will produce a modulated signal equivalent, but not identical to that out- put from modulator 30 By equivalence, what is meant is that the Q output of bistable cir- cuit 52 will be modulated signal changeable at predetermined first clock intervals in a manner proportional to the signal input to the modula- tor The Q' output bistable 59 will lead the Q output of first bistable circuit 52 by an GB 2178545 A 9 amount dependent on the differences in the clock signals supplied to the two bistable cir- cuits This lead occurs as a natural conse- quence of the fact that the Q output of bista- ble circuit 52 will change only at the next clock pulse following a change in the Q' out- put of bistable 59 The Q' output is a true "leading" signal to the Q output.

The output signal on line 34 will have a phase lead of one-half of a first clock interval, as compared with the Q and Q outputs of bistable circuit 52 Since the clock intervals supplied to both bistable circuit 59 and bista- ble circuit 52 are the same, the delayed con- trol signal output on lines 34 will be changea- ble at the same intervals as the Q and a outputs of bistable circuit 52 and will other- wise resemble any other delta-minus-sigma modulated signal The clock signal supplied to bistable circuit 59 in effect becomes the de- termining clock signal governing changes in the output of the modulator It would be pos- sible to substitute another type of digital shifter, such as a multi-stage shift register, for bistable circuit 59, if the delay introduced is not so long as to destabilize the feedback loop The digital shifter used might also be clocked at a different rate than the first bista- ble circuit 52, although that would change the characteristics of the delayed control signal If, for example, a multi-stage shift register clocked at a high rate were inserted in place of bistable circuit 59, it would delay the con- trol signal by a selected number of short inter- vals The output of such a shift register would be a delayed control signal which is changea- ble at the higher clock rate A shift register could also be employed, having different stages clocked at different rates In such a configuration, the longest clock interval used to clock any of the stages would determine the intervals at which the final delayed control signal would be changeable Any system for delaying the control signal should include at least one bistable circuit clocked at discrete intervals in order that the modulated output of the modulator (the delayed control signal) will be changeable at those discrete intervals.

The phase lead produced in modulator 30 ' can be selected Such selection is accom- plished by adjusting the clock signals supplied to bistable circuits 52 and 59 Assuming a first clock signal producing pulses at first clock intervals is supplied to bistable circuit 52 and a second clock signal producing pulses at second clock intervals is supplied to the digital shifter (bistable circuit 59), and both first and second clock intervals are equal, the phase offset between the clock signals will determine the amount of lead in the modulator output In the example discussed with respect to Fig 7, the second clock was the inverse of the first clock and the total offset was one- half a clock interval If the clock pulses sup- plied by the second clock to bistable circuit 59 were three-quarters of a clock interval ahead of the pulses supplied to bistable circuit 52, a phase lead of three-quarters of a clock interval would be produced It is the amount of delay between a change in the Q' output of bistable circuit 59 and the Q output of bista- ble 52 which determines the amount of lead time in the signal output on lines 34.

The amount of phase lead that can be achieved by the Fig 6 modulator is dependent on the degree of delay that can be introduced into the feedback loop of a delta-minus-sigma modulator without causing it to destabilize It is known, however, that a delay of a fraction of a clock pulse in the manner described in the example above is functional and produces the phase lead in the modulated signal as de- scribed.

Fig 8 shows a metering system according to a further embodiment of the present inven- tion which provides additional output power measurement in either VARS or Q As de- scribed in the background section above.

VARS and Q represent power measurements in which a specified phase relationship is intro- duced between the current and voltage sig- nals VARS is obtained by multiplying current with a voltage signal which lags by 90 de- grees; Q is obtained by multiplying current with a voltage signal which lags by 60 de- grees In the metering system of this embodiment of the present invention, VARS, Q or any other desired phase relationship power value can be readily obtained by delaying the output of modulator 30 by a selected amount.

The delay can be conveniently produced using time delay means such, as a shift register, in the manner described below.

The Q output of modular 30 of the Fig 8 embodiment is supplied both to gating means and to a shift register 160 Shift register delays the output of modulator 30 by a selected delay interval The amount of delay depends on the selected phase relationship power value desired (VARS or Q), and also on the frequency of the AC waveform being mea- sured ( 50 or 60 Hz) To simplify the circuit, only the Q output of modulator 30 is supplied to shift register 160 The time delayed output of the shift register is then supplied to an inverter 161, and both the inverted and non- inverted signals become the time delayed sig- nal on line 162 As used herein, the term 'time delayed signal" is used interchangeably with "phase modified signal" and it should be understood that the phase modification introduced is accomplished by means of a time delay introduced in the signal.

Further processing of the time delayed modulated signal is exactly the same as for the first modulated signal of the embodiment of Fig 1 The time delayed modulated signal is supplied to a second gating means 164, which includes a pair of switches 166 and 168 controlled by the time delayed modulated GB 2178545 A 10 signal The inverted and non-inverted current analog signal 'A 2 is supplied to switches 166 and 168 The phase modified modulated sig- nal alternately closes switches 166 and 168 to multiply the current and voltage signals to- gether and produce a second product signal, at 170 The second product signal is then supplied to the input of a VARS/Q convertor 172, which is exactly like convertor 90 shown in Fig 3 VARS/Q convertor 172 outputs first and second output signals, depending on the polarity of the power on line 10, in exactly the same manner as convertor 90 The out- puts of convertor 172 are first and second output signals changeable between two levels at the convertor clock intervals in a manner proportional to the second product signal and to the selected phase relationship power value (VARS or Q, 50 or 60 Hz) of the power on line 10 Subsequent processing of the first and second output signals from VARS/Q con- vertor 172 is exactly the same as for the outputs from convertor 90 shown in Fig 1, including use of counter means suitable for outputting selected power values.

A selector (not shown) can be provided for selecting either VARS or Q as the second out- put of the metering system The selector will adjust shift register 160 to produce the vol- tage lag needed to generate the selected phase relationship, and simultaneously select an appropriate display.

The exemplary and novel digital phase se- lection technique depicted in Fig 8 is not lim- ited to power metering applications The tech- nique may be used in any signal multiplication applications where the phase relationship be- tween input signals may be adjusted in order to measure selected phase relationship pro- duct values.

Fig 9 depicts a multiplier similar to the mul- tiplier used in the power metering system of Fig 8 Like elements are designated by like reference numeral signals 'A, and 'A, are the signals to be multiplied together and are as- sumed to be periodic waveforms, not neces- sarily sinusoidal, having a predetermined phase relationship to one another As with the Fig 8 power metering system, multiplication is ac- complished by the technique known as time- division or markspace multiplication, in which one of the signals IA, is modulated and then used to gate or reverse the polarity of the other signal IA, to obtain a product signal Sig- nal IA? is supplied to a gating means in both inverted and non-inverted forms A conven- tional inverter 72 supplies the signal to switch 82 The non-inverted signal is supplied to switch 65 The modulated signal for control- ling switches 65 and 66 is supplied to the gating means by way of line 34.

Modulator 30 of Fig 9 is equivalent in con- struction and operation to corresponding mo- dulator 30 of Figs 1 and 2 In order to achieve a selected phase relationship between signal I Al and IA 2, a digital shifter 160 is used which introduces a selected delay in the out- put of modulator 30 Digital shifter 160 can take numerous forms, a simple version being illustrated in element 198 of Fig 11 The op- eration of a shift register can be illustrated conveniently as a series stages made up of bistable circuits 200 through 204 connected so that the Q output of one bistable circuit is supplied to the D input of the adjacent bista- ble circuit A clock signal supplied to each of the bistable circuits via line 196 causes each stage to be clocked simultaneously A digital pulse on line 53 into shift register 198, either going from low to high or from high to low, will be delayed one input clock interval by each bistable circuit it passes through For example, if the signal on line 53 goes from low to high, the Q output of bistable circuit 200 will go from low to high at the next clock pulse Because of inherent switching de- lays, when the Q output of bistable circuit goes from low to high and that signal is supplied to the D input of bistable circuit 201, its Q output must wait for the succeeding clock pulse to go high In this manner, digital signals can conveniently be delayed by any desired number of discreet intervals simply by providing enough delaying stages in the shift register Customarily, shift registers are pro- vided with a plurality of output lines 206 at which the signal can be extracted The loca- tion of the pin determines the overall delay introduced, as a function of the clock fre- quency.

The digital time delay means 160 of the multiplier system shown in Fig 9 is assumed to be a conventional shift register such as shift register 198 of Fig 11 The multiplier system calls for the introduction of a selected time adjustment in one of the signals to be multiplied using a digital shifter to introduce a delay which is a selected number of discrete intervals Shift register 198 is a suitable digital shifter for producing such a delay Referring now to Fig 10, it will be assumed that sig- nals 'Al and IA? are to be multiplied together and that a 90 degree phase lag will be intro- duced into signal 1 A? Fig 10 a shows an ex- emplary first input signal IA, (VJ) and Fig l Og shows an exemplary second input signal 1 A? to be multiplied together Fig 10 b shows the clock signal provided by clock 56 and Fig. c shows the output signal of the integrator 42 which results from input

signal IAI Fig.

d shows the resultant output of comparator The output of modulator 30 is shown in Fig 10 e, and is carried on line 53 of Figs 9 and 11 The clock signal from modulator clock 56 is supplied to shift register 198 via line 196 In the example given, the clock intervals, shown in Fig 10 b, are twenty-four times the frequency of signal IA A 90 degree phase lag will therefor require a delay of six clock inter- vals Assuming pin 206 ' of shift register 198 GB 2178545 A 11 to be the sixth pin, signal 'A 2 ' modulated and delayed by 90 degrees, will thus have been delayed by a total of six clock intervals output from clock 56 The pin 206 ' output of shift register 198 is illustrated in Fig 10 f The de- layed modulated signal shown in Fig 10 f is an exact reproduction of the modulated Q output of modulator 30, shown in Fig 10 e, moved to the right six clock intervals.

Signal multiplication is accomplished by sup- plying the delayed modulated signal shown in Fig 10 f to the signal gating means, via line 34 Line 34 includes both inverted and non- inverted versions of the delayed modulated signal by supplying the signal to a conven- tional digital inverter 161 Signal IA 1 is that shown in Fig 1 Og both in inverted and non- inverted forms Multiplication is carried out by means of switches 82 and 86, which are opened and closed alternately from one another, switching point 88 of Fig 9 between the non-inverted versions of signal A 1, The re- sultant signal is shown in Fig 10 h The signal in Fig 10 h can then be passed through a suitable low pass filter 90 to produce an aver- aged or D C value, as shown with the line 132 of Fig 10 h Line 132 represents a product signal proportional to the product value of IA, and IA, with a phase lag of 90 degrees introduced in 'A 2 If, for example, signal 1 Al was proportional to current carried on a power line and signal IA 2 was proportional to line voltage, the product signal represented by line 132 of Fig 10 h would be proportional to VARS.

A particular advantage of using a delta- minus-sigma modulator such as modulation 30 in conjunction with the subject multiplier is that the modulated signal is changeable only at predetermined clock intervals Digital time delay techniques necessarily divide an incom- ing signal into discrete units or intervals The length or duration of those intervals is a mat- ter of design choice Digital-type signals carry information at pulse edges, when the signal goes from low to high or high to low A shift register made up of a series of bistable circu- its will "look" for such pulse edges each time it is clocked The higher the clock frequency, the more frequently is the incoming signal sampled for a pulse edge Since the delay introduced in a signal at each stage of a shift register depends on the clock frequency, shift registers clocked at a high frequency require more stages to produce a given delay than shift registers clocked at a low frequency Of course, clocking a shift register at a low fre- quency means that the incoming signal is sampled less often for pulse edges, and this can be a disadvantage if the location of the pulse edges is not known, as is the case with conventional pulse width modulated signals.

Modulator 30 outputs a signal having pulse edges which occur only at predetermined clock intervals By synchronizing the clock sig- nals supplied to the modulator and to shift register 198, the shift register will "look" for pulse edges only at the times required This means that fewer register stages are needed to introduce a given delay in a modulated sig- nal than would be the case if the location of the pulse edges were not precisely known In fact, in the example given above, the shift register can be clocked at the same rate as modulator 30, with no loss of information whatsoever It is therefore possible to use an economical shift register, possessing relatively few stages, to produce a given delay in a delta-minus-sigma modulated signal, which when a far larger shift register would be needed to produce a comparable delay in a signal having pulse edges at random locations.

Even if a relatively high frequency shift register was employed to delay a substantially lower frequency randomly modulated signal, some loss of information would occur whenever a pulse edge was not precisely synchronized with the shift register clock No such loss of information occurs in the embodiment of the present invention described above since the modulator and shift register are synchronized with one another and pulse edges are there- fore not displaced.

The clock intervals by which the shift regis- ter is clocked need not be exactly the same as the first clock intervals of the modulator It is, however, preferable that the shift register clock be synchronized with the modu- lator clock To avoid loss of information, the shift register clock should operate at a fre- quency no lower than that of the modulator, but may operate at higher rates to achieve virtually any desired time delay A convenient way of increasing the frequency of the shift register clock while maintaining synchroniza- tion with the first clock intervals of the modu- lator is to use a frequency divider for the mo- dulator clock While in the example described above, the desired time delay in the modu- lated signal corresponded with an integer number of first clock intervals, that may not always be the case In order to achieve addi- tional flexibility in the selection of a time delay it may be desirable to include either a second shift register or additional stages within a sin- gle shift register which are clocked at a higher frequency and which therefore introduce incre- mental delays in the modulated signal The shift register states within element 212 of Fig.

11 illustrates a technique for providing further selectivity in the digital time adjustment of the present invention In this example, the delayed signal output from any selected stage of shift register 198 is supplied to a second group of shift register stages shown in Fig 11 as a second shift register 212 A plurality of bista- ble circuits 216 make up shift register 212.

The delayed signal from register 198 is sup- plied to the input 214 of shift register 102 A clock signal, via line 208 preferably having a higher frequency than first clock 56, is sup- GB 2178545 A 12 plied to the bistable circuits which form shift register 212 The higher clock frequency can conveniently be provided by means of an os- cillator 220 operating at a higher frequency than first clock 56 Through use of a suitable frequency divider 210, clock signals of differ- ent frequencies can be supplied to the various shift register stages, as well as to modulator 30, if desired.

As used herein, the term first clock intervals generally refer to the clock signals output from first clock 56 and second clock intervals will be those output from second clock 220.

In addition, the shift register stages illustrated in Fig 11 can be thought of either as a first shift register 198 and a second shift register 212, or a single shift register having a plural- ity of stages which are clocked at various se- lected frequencies Either through use of sepa- rate oscillators or a single oscillator with a frequency divider, the provision of different clock signals increases the flexibility of the di- gital shifting techniques used in the present invention Delaying a signal with a shift regis- ter having a number of stages all clocked at the same rate allows a signal to be delayed by any number of discrete intervals, up to the maximum number of changes in the shift register By providing additional stages clocked by a different clock signal, additional selected delay intervals can be provided A signal can be passed through a first shift register and delayed a certain number of first intervals, and then passed through a second set of shift register stages and delayed an additional number of second intervals Thus, a delay of virtually any desired whole and frac- tional increments of the first intervals can be provided Similar flexibility in signal delays by digital means can be achieved by using a sec- ond clock which operates at the same fre- quency as the first clock, but is offset in time by a selected amount For example, if a signal is passed through a first shift register clocked at first intervals and then supplied to an addi- tional stage clocked with the inverse of the first interval clock signal, an additional delay of one-half of a first clock interval will be introduced Depending on the offset between the clock signals supplied to the first and sec- ond group of shift register states, almost any amount of delay can be introduced.

An example of the operation of the modula- tor and digital time delay means of Figs 9 and 11 is given in Fig 12 Assuming a first clock signal supplied by clock 56 to be that shown in Fig 12 b and a second clock signal supplied by second clock 220 to be that shown in Fig 10 a, a modulated signal input to the shift register will be delayed in the manner described below In this example, second clock 220 is exactly twice the frequency of first clock 56 If, for example, a delay in the modulated signal of two-and-a-half first clock intervals is desired, the shift register will be configured so that otuput pin 206 " is con- nected to the second shift register input 214.

In that way, a modulated signal input via line 53 will pass through two first shift register stages 200 and 201 and into the first stage of second shift register 212, after which the signal is output at pin 218 The signal will be delayed two full first clock intervals and an additional second clock interval by such a sys- tem Assuming a modulated signal as appears in Fig 12 c is input to the configuration de- scribed above, the output at pin 218 will be the signal shown in Fig 12 d The delayed modulated signal shown in Fig 12 d is exactly the same as the modulated signal shown in Fig 12 c, delayed by two-and-a-half first clock intervals.

The digital shifting technique of the subject multiplier has the advantage inherent in digital electronics of being relatively drift-free and error-free Furthermore, the time adjustment is made in a manner independent of the signal being adjusted In other words, it is not de- pendent on the frequency of the signal being adjusted in time The system shown in Fig 9 allows for phase adjustment in the multiplica- tion of two analog signals without the use of R.C networks and their associated signal perturbations If delta-minus-sigma modulation is employed in the multiplication, the size of the shift registers employed need not be prohibi- tively large, while yielding a high level of accu- racy.

In order to achieve high accuracy from the subject power metering system of the present invention over a wide dynamic range, it is im- portant that offset errors be eliminated from the active circuit elements Offset errors of sufficient magnitude to adversely affect mea- surement accuracy are commonly found in low cost operational amplifiers The term voltage offset is generally defined as the voltage dif- ference between a pair of inputs to an active circuit element, such as an operational ampli- fier, when the output is zero It is a mismatch between the amplifier inputs, and the metering system of the present invention incorporates offset compensation means which correct for such mismatch.

Fig 13 illustrates a novel offset compensa- tion system, as applied to a single amplifier.

The basic theory of the offset compensation system involves use of a capacitor or other storage element which is connected to one input of the amplifier and then charged to a compensating voltage It will be understood that other equivalent systems for storing and supplying a voltage to an amplifier input could be used in place of a capacitor Operational amplifiers often have more than two inputs, and sometimes include one or more inputs specifically designed for offset compensation purposes The present invention will work equally well to offset compensate amplifiers having additional inputs Whichever input is GB 2178545 A 13 designated to receive a compensating voltage to correct for voltage offset will be the input to which the capacitor is connected The sys- tem further includes means for charging the capacitor to an offsetting voltage which substantially cancels out the effect of the voltage offset another amplifier input For simplicity, only amplifier 70 (Fig 1) is shown in Fig 13, although the offset compensation means of the present invention can sequentially correct a plurality of amplifiers, as set forth below.

The amplifier offset compensation means as applied to amplifier 70 includes an offset sto- rage element, such as capacitor C, connected to a first selected input 181 of the amplifier.

A nulling circuit 182, connected through swit- ches to both the offset storage element and the second selected input 183 of amplifier 70, is also provided Nulling circuit 182 includes a charging amplifier 184 connected to the sec- ond input of amplifier 70, through a switch Al The nulling circuit also includes a tempo- rary storage element, capacitor 186, and a series of switches, B, D and E, which connect capacitor 186 in to charging amplifier 184 as described below Additional switches G, and H, connect charging amplifier 184 in a charg- ing circuit, which adjusts the voltage stored on capacitor C,.

The line current signal 1 A 2 is supplied to the inverting input 183 of amplifier 70, which is ideally a virtual earth Any voltage offset in amplifier 70 will appear initially as a voltage at inverting input 183 As capacitor C, becomes charged, the voltage at inverting input 183 will decrease until a virtual earth condition is reached The difference between the compen- sating voltage V,, on C, and the actual vol- tage offset of amplifier 70 is termed an error voltage V It is V,,,,,, which appears at input 183 It is the purpose of the offset compen- sation means of the present invention to re- duce V,,,, to a minimum.

The offset compensation means includes control means for accomplishing the functions set forth in box 190 Essentially, the control means operates switches Al, B, D, E, Gl, and Hi to produce a series of transfer and charging periods, sequentially During an initial transfer period, switches Al, B and D are closed and switches E, Gl and Hi are open.

With switch Al closed, V,,,, r is supplied to the non-inverting input of charging amplifier 184, which is configured as a unity-gain am- plifier Switch B, which is closed during the transfer periods, makes a feedback connection between the output 192 of charging amplifier 184 and the non-inverting input 226 A first terminal 228 of temporary storage capacity 186 is also connected to inverting input 226.

Switch D, when closed, connects a second terminal 230 of capacitor 186 to ground.

Thus, during the transfer period, Varo, appears at amplifier output 192 and is stored on tem- porary storage capacitor 186, together with the voltage offset of charging amplifier 184 (Voffset-Ap 184).

During a subsequent charging period, control means 190 opens switches Al, B and D and closes switches E, Gl and Hi That serves to disconnect the second terminal 230 of capaci- tor 186 from ground and connects it to ampli- fier output 192, in a second feedback loop.

The result is that a voltage -Vermr appears at amplifier output 192 The internal offset of charging amplifier 184 (Vof Se,Amp 184) is cancelled by the equal and opposite value of the com- ponent Voffet -Amp 184 which is supplied to out- put 192 from capacitor 186 The closure of switch Gl and the opening of switch Al dur- ing the charging period also supplied the vol- tage Vc Omp on offset storage capacitor Cl to the non-inverting input of charging amplifier 184 With -Vr, at charging amplifier output 192 and Vcom, at its input (during the charging period), a current -terror is set up through im- pedance 224 and switch Hi which adjusts Vorp in the direction necessary to reduce Verror during the next transfer period.

go Fig 14 illustrates the operation of the offset compensation means during startup condi- tions Assuming the voltage V Otf Se-At AP 70 represents the voltage offset between the inputs of amplifier 70, and the charge on capacitor C, (Vco_,p) is initially zero, then Verrr, during the initial transfer period will equal V Off Se,-Amp 70 Dur- ing the subsequent charging period a voltage -Vwror will appear at amplifier output 192 A current -,rror will then be supplied to capacitor 186, increasing the value of Vcomp The voltage Vcop on capacitor C, will serve to substantially reduce the offset error of amplifier 70 until the next transfer period The values of resistor 224 and capacitor C 1 are chosen to produce a current -I which will not excessively change the voltage on capacitor C, during any single charging period Capacitor C, will therefor not become charged to the full offsetting voltage during the first few transfer and charg- ing cycles As Vcmp approaches (V Of S Ct Am P 70) V error will become progressively smaller Even- tually, Verro will approach a stable minimum value sufficient to correct for leakage currents and other transient signals present in the cir- cuitry At that point the offset errors will be virtually eliminated.

Subsequent transfer and charging periods can either follow immediately after previous transfer and charging periods, or be separated by a time delay In the preferred embodiment, where additional amplifiers are being offset compensated using the same nulling circuit 182, the transfer and charging periods associ- ated with any one amplifier are separated by predetermined time intervals Referring to Fig.

14, the next transfer period shows a Ve,,,r which is smaller, as shown at 222 As before, Verror is first stored on capacitor 186 and then, during the following charging period, appears at charging amplifier output 92 an A GB 2178545 A 14 -Verror During this charging period the current -1 erori S added to the charge on capacitor C 1, further reducing the magnitude of Vurror during the following transfer period During subse- quent cycles, Vom, P on capacitor C, will ap- proach the actual voltage offset of amplifier 70, reducing Verrmr to approximately zero.

The offset compensation system described above with respect to amplifier 70 can simi- larly offset compensate a plurality of amplifier elements Fig 15 shows the preferred em- bodiment of the offset compensation system used to provide offset compensation for five different amplifiers The five amplifiers to be offset compensated by the compensating means of the metering system are as follows:

current signal gain amplifier 70, current signal inverting amplifier 74, first modulator integrat- ing amplifier 46, Watts output convertor integrating amplifier 108 and VARS/Q output con- vertor integrating amplifier 180 Each of the amplifiers is similar to gain amplifier 70 dis- cussed with respect to Fig 13 in that all have virtual earth inverting inputs to which a signal is supplied Each of these amplifiers is pro- vided with respective offset storage elements, capacitors C, through C The non-inverting in- puts of the amplifiers are connected to the charging amplifier 184 of nulling circuit 182 through respective switches Al through A 5, as shown in Fig 15 Pairs of switches equiva- lent to Gl and Hi of Fig 13, namely Gl through G 5 and Hi through H 5, connect charging amplifier 184 to the respective offset storage capacitor of each amplifier.

A single nulling circuit 182 will store the error voltage and charge the offset storage capacitor of each amplifier, by means of the sequence described below For clarity, the control circuitry for operating the various swit- ches shown in Fig 15 is omitted A conven- tional controller of any suitable type can be used to control the switches in accordance with the timing diagram illustrated in Fig 16.

The controller first closes switches Al, B and D during an initial transfer period for amp 70, then open switches Al, D and B and closes switches E, G 1 and H 1 during a charging per- iod The controller then provides additional successive transfer and charging period for each of the other amplifiers being offset com- pensated After the charging period of ampli- fier 70 the transfer period of amplifier 74 be- gins, with the controller closing switches A 2, D and B and then opening those switches and closing switches E, G 2 and H 2 during the sub- sequent charging period For amplifier 46, switches A 3, B and D are closed during the transfer period and switches E, G 3 and H 3 are closed during the charging period For ampli- fier 108, switches A 4, B and D are closed during the transfer period and switches E, G 4 and H 4 are closed during the charging period.

Finally, for amplifier 180 switches A 5, B and D are closed during the transfer period and switches E, G 5 and H 5 are closed during the charging period.

After a transfer and charging period has been completed for an amplifier, all the swit- ches associated with the amplifier, namely switches A, G and H, are left open The charge stored on the respective offset storage capacitors will remain until the controller se- quence produces a new charging period asso- ciated with that capacitor Although some charge decay will occur, errors due to voltage offset are substantially reduced for each of the amplifiers The frequency of operation of the controller for opening and closing the switches associated with the offset compensation means is a matter of design choice, but can be substantially slower than the clocks associ- ated with the metering system.

The disclosed offset compensation system can be used to correct for offset errors in any number of amplifier elements associated with a metering system A single nulling circuit like circuit 182 can be sequentially connected to up to N amplifier elements and to their associ- ated storage elements during a sequence of transfer and charging periods Such an offset compensation system is economical, and is ideally suited to the use of CMOS integrated circuitry where offset errors can present prob- lems Although described with respect to the metering system of the present invention, the offset compensation system can be applied equally well to other types of power metering circuits employing operational amplifiers Such a metering circuit might include, for example, any suitable means for multiplying the analog signals representing current and voltage, as well as any suitable convertor or filter circuit for producing an output signal from the pro- duct signal Assuming that the metering sys- tem employs up to N amplifier elements in its various components, the offset compensation system of the present invention can substan- tially eliminate offset errors in the manner de- scribed below.

The N amplifier elements, each will include plurality of inputs A first selected input in any such amplifier is the input for receiving a compensating voltage to correct for voltage offset.

N offset storage elements, such as capacitors, are also provided One of the N offset storage elements is connected to the first selected in- put of each of the N amplifier elements The offset storage elements receive compensating voltages which substantially reduce the offset error at another input of the amplifier element to which it is connected, the other input being designated the second selected input Any dif- ference between the compensating voltage on the offset storage element and the voltage offset of the amplifier element is an error vol- tage which appears at the second selected input of the amplifier element A nulling circuit such as circuit 182 is also provided for the power metering system The nulling circuit can GB 2178545 A15 be connected sequentially to each of the N amplifier elements and to the offset storage associated therewith In the description below, the amplifier element to which the nulling cir- cuit is connected, including its associated sto- rage element, is termed the selected amplifier element In the same manner as the system described above, the nulling circuit is first con- nected to the second input of the selected amplifier element, during an intermittent trans- fer period The nulling circuit is then con- nected to the offset storage element associated with the selected amplifier element during the intermittent charging period following the transfer period A control system then con- nects the nulling circuit sequentially to the re- maining of the N amplifier elements to provide transfer and charging periods for each of the amplifier elements The sequence is continu- ously repeated, whereby all of the amplifier elements are offset compensated and the off- set errors in the metering system are substan- tially eliminated.

Through incorporation of the offset compen- sation means described above, the metering system of the present invention meters power to a high degree of accuracy over a wide dynamic range The neded for relatively high cost calibrated or error-free amplifiers is elimi- nated, which makes the metering system rela- tively inexpensive The system provides con- tinuous parallel readings of power in both Watts and in VARS or Q Because the modu- lator output from modulator 30 is clocked pre- cisely at the first clock intervals, it is possible to manipulate the signal with digital logic A shift register can be conveniently employed to introduce the time delay necessary to provide an appropriate phase shift for the VARS and Q measurement By simply selecting the ap- propriate stage in the shift register, the delay in the modulated signal can be adjusted to produce the desired output (VARS or Q, 50 or 60 Hz) The invention thus eliminates the need for tuned analog phase shifters to pro- duce the desired voltage lag Because the out- put of the modulator can be supplied both to a power and a VARS/Q converter, simulta- neous readings can be produced with only a single modulator The system further provides digital outputs for each polarity of power flow on the line Maximum information is therefore provided to a high degree of accuracy in an efficient and economical manner.

Fig 17 shows a portion of an alternative embodiment modulator which is somewhat simpler in construction than modulator 30 shown in Fig 2 In this emobdiment, a capaci- tor 44 is connected between the summing node 36 and ground Capacitor 44 serves as the modulator integrator The inverting input of a comparator 50 is also connected to node 36 with the non-inverting input being con- nected to ground Comparator 50 develops a control signal in response to voltage changes on node 36 which is coupled to a bistable circuit 52 Circuit 52 is used to control a pair of switches which supply a feedback signal to node 36, as will be subsequently described.

Fig 18 illustrates several of the signals pro- duced by the Fig 17 modulator Input signal VL is represented in Fig 18 a Of course, in A.C power metering applications, VL will be sinusoidal Initially, switch 58 is assumed to be closed, and a negative reference current is applied to summing node 36 through resistor The values of Vi 1 and resistor 40 are chosen to produce a current 1, which is large relative to input signal A 1, 'd 01 Will therefore have a net negative value, with current being drawn from capacitor 44 Consequently, the integrated difference voltage signal initially de- creases, as shown in Fig 18 c.

Clock 56 outputs signal shown in Fig 18 b.

Bistable circuit 52 clocks on the leading edge of each upwardly-moving pulse At clock pulse a, the integrated difference signal of Fig 18 c has not yet crossed the threshold of compara- tor 50, so Q remains low and a high and the difference signal continues to integrate down- ward Since the difference signal is supplied to the inverting input of comparator 50, when the signal crosses the threshold, the compara- tor output switches from low to high The control signal shown ini Fig 18 d represents the output of comparator 50 Consequently, at clock pulse b, bistable circuit 52 will change states and Q will go from low to high When Q goes high O goes low and switch 60 is closed and switch 58 is open A positive ref-erence signal is then supplied to summing node 36, causing integrated ldlff to increase un- til the next clock pulse at c Between clock pulses b and c, the integrated difference signal again crosses the threshold level of compara- tor 50, causing the first control signal to go low Q then goes low at the next clock pulse, causing the reference signal supplied to summing node 36 to again go negative As V, increases, the slope of the difference signal changes and its value decreases until again crossing the threshold level Q remains low until detecting a change in the first control signal at clock pulse f Q then goes high, again switching the reference signal from negative to positive.

The above-described circuit and method op- erates as a delta-minus-sigma convertor in which only the difference between the input and reference signals is integrated and mea- sured The circuit always maintains the inte- grated difference signal around the threshold level of comparator 50 The Q output of bis- table circuit 52 is chosen as the first output signal, having an average level or amplitude over time which is proportional to the magni- tude of VL.

Fig 19 shows a modulator circuit as in Fig.

1 7 which incorporates an alternative offset compensation system In this embodiment, GB 2178545 A 16 comparator 50, which is an operational amplifier element, is provided with compensating means for substantially eliminating any offset error resulting from a voltage offset existing between the amplifier inputs 306 and 308 As described above, a voltage offset is generally defined as the voltage required between in- puts of an amplifier to produce a zero output.

Ideally, voltage offset is zero, but in most real-world operational amplifiers an offset of unknown value is usually present With the present invention, a first storage element, such as capacitor 302 is connected to one of the amplifier inputs, and an offsetting voltage substantially equal to the voltage offset of the amplifier is stored on the storage element to compensate for the voltage offset In the example shown in Fig 19, capacitor 302 is located in the electrical path between summ- ing node 36 and inverting amplifier input 306.

It should be understood that capacitor 302, like capacitor 44 and the other storage ele- ments used in the embodiments described be- low, represent one type of storage element which can be used, and that other types of circuit elements, such as registers with D to A convertors and the like, could be used for the various storage elements of the present inven- tion.

The offset compensation system also in- cludes a feedback loop 300, which is intermit- tently connected around amplifier 50, between inverting input 306 and the amplifier output through a switch, C When switch C is closed, the voltage offset appears at a low impedance at input 306 In order to store the voltage produced by the feedback loop on capacitor 302, switches A and B are provided to disconnect one end of the capacitor from summing node 36 and connect it to common ground 305.

The means for controlling the offset com- pensation system shown in Fig 19 is clock 56, and Fig 20 illustrates the control function.

Bistable circuit 52 clocks at the leading edge of each clock cycle, as indicated by arrows 312 Each upward moving pulse represents one clock pulse Just as the clock signal be- gins to go from low to high, switches B and C are off and switch A is on, meaning that the feedback loop around amplifier 50 is dis- connected and capacitor 302 is connected to summing node 36 As soon as the clock pulse begins, switches B and C turn on and switch A turns off, connecting the feedback loop around amplifier and connecting one ter- minal of capacitor 302 to ground During this period, called the nulling period, the voltage offset +V,,,s,, of amplifier 50 appears at input 306 Since capacitor 302 is connected be- tween input 306 and ground, the voltage +Vofset is stored on the capacitor During the last half of each clock cycle, called the mea- suring period, switches B and C again turn off and switch A turns on With non-inverting in- put 308 tied to ground, the error at inverting input 306 is the negative value of the voltage offset -V ff S,, Consequently, the signal being compared to the threshold level by compara- tor 50, when A is closed and B and C are open, is the voltage at summing node 36, the integrated difference signal, plus +Vo,,se, plus -VO,,Set The voltage offset of comparator 50 is therefore cancelled, and the error it would otherwise produce in the threshold measure- ment is essentially eliminated.

Another embodiment of a modulator utilizing an offset compensation system is shown in Fig 21 In this embodiment, measuring means 298 has first and second amplifier elements 328 and 336, respectively, which serve as comparators and are alternately connected be- tween summing node 36 and bistable circuit 52 First amp 328 is provided with a switcha- ble feedback loop 324 connecting output 330 with inverting 326 through switch D A first storage element in the form of capacitor 316 is connected in the electrical path between summing node 36 and inverting input 320 through switch E A path is provided between one terminal 318 of capacitor 316 and ground, through switch F Second amplifier element 336 also includes a switchable feed- back loop 332 connected between output 338 and inverting input 334 through switch G, and a storage element such as capacitor 320 is in the electrical path between inverting input 334 and summing node 36, through switch H A path between one terminal 322 of capacitor 320 and ground is provided, through switch J.

The embodiment of Fig 21 is designed to provide two parallel offset compensated com- parator circuits for measuring the integrated difference signal at summing node 36 When switches E and K are closed, first amplifier element 328 supplies the first control signal to bistable circuit 52 and when switches H and L are closed, second amplifier element 336 supplies the first control signal to bistable circuit 52 By closing switches E, G, J and K and opening switches D, F, H and L, first amplifier element 328 is in a measuring mode supplying the control signal to bistable circuit 52, and second amplifier element 336 is in a nulling mode in which the voltage offset of amplifier element 336 is stored on capacitor 320 Storage of V,,,,, on capacitors 316 and 320 is accomplished in exactly the same man- ner as with amplifier element 50 and capacitor 302 in the embodiment of Fig 19 By revers- ing all the switches, i e, closing switches D, F, H and L and opening switches E, G, J and K, amplifier 328 is in the nulling mode and amplifier 336 is in the measuring mode in which the integrated difference signal at summing node 30 is supplied to inverting in- put 334 through capacitor 320, compensating for the voltage offset of amplifier 336 and providing and error-free first control signal to the D input of bistable circuit 52.

GB 2178545 A 17 One advantage of the embodiment shown in Fig 21 over that shown in Fig 19 is that one offset compensated amplifier is available at all time in its measuring mode Furthermore, switching between measuring and nulling modes in the embodiment of Fig 19 occurred at the clock frequency of clock 56 If the sampling frequency, as determined by the frequency of clock 56, is sufficiently high, the amplifier elements which serve as comparators will be unable to stabilize after each nulling period, and errors will be introduced The em- bodiment of Fig 21, which uses conventional control logic for operating switches D, E, F, G, H, J, and L, represented by element 340, can be operated at a frequency different from clock 56 A conventional frequency divider can be used to reduce the frequency of the control operations, for example.

In order to insure that adequate time is pro- vided for the amplifiers in the embodiment of Fig 21 to stabilize after each nulling period, control logic 340, which serves as control means for operating switches D, E, F, G, H, J, K and L, extends the measuring period for each amplifier element to allow time for stabil- ization Fig 22 shows the timing diagram for the operation of switches D, E, F, G, H, J, K and L by control logic 340 Switches K and L, which connect the outputs of the first and second amplifier elements, respectively, to bis- table circuit 52, are operated out of phase with one another Switch K is on half the time, and off half the time and switch L being off when K is on, and vice versa In addition to controlling the switches which connect the amplifiers to bistable circuit 53, control logic 340 also controls the switches which deter- mine the nulling and measuring periods of am- plifiers 328 and 336 Switches D, E and F serve to connect a feedback loop around am- plifier 328 and connect the one terminal 318 of capacitor 316 to ground, in exactly the same manner as the embodiment of Fig 19.

Switches G, H and J perform the same func- tion for amplifier 336 As can be seen from Fig 22, the amplifier nulling and measuring periods of each amplifier element are not of the same duration The nulling period for first amplifier 328, for example, begins when switch K turns off and ends before switch K again is turned on Similarly, the nulling period of second amp 336 begins when switch L turns off and ends before switch L turns on again Consequently, the nulling period of each amplifier is shorter than the measuring period by a predetermined interval This is done to allow time for the amplifiers to stabilize before being connected to bistable circuit 52.

It should be noted that, in addition to allow- ing extra time for amplifier stabilization before connecting either the first or second amp to the bistable circuit, control logic 340 operates inherently slower than clock 56 As can be seen from Fig 22, the clock signal, which is not drawn to scale, operates at a substantially higher frequency than any of the switches in Fig 21 Control logic 340 preferably includes a frequency divider for this purpose The em- bodiment shown in Fig 21 can thus employ a relatively high frequency clock, for example 10 K Hz, to provide frequent sampling and rela- tively high resolution, while nulling and offset compensating the amplifier elements at a low enough frequency to minimize errors due to slow amplifier response.

The method of the present invention per- formed by the embodiment of Fig 21 includes an additional step in the measuring step, for switching between the first and second ampli- fier elements, 328 and 336, respectively The compensating step includes measuring with the first amplifier element and nulling the sec- ond amplifier element and then measuring with the second amplifier element and nulling the first amplifier element, in a continuous cycle, such that at least one of the offset compen- sated amplifier elements is connected to the summing node at all times In the preferred embodiment of the method, the nulling periods and measuring periods are different, and preferably slower than the clock intervals Fur- ther, the nulling periods are shorter than the measuring periods for each amplifier element, in accordance with the timing diagram of Fig.

22 The measuring period of one amplifier ele- ment is begun prior to ending the measuring period of the other amplifier element such that any errors due to slow comparator response of the first amplifier elements as it is initially switched from nulling to measuring is elimi- nated.

Operation of the embodiment of Fig 21 will produce the results illustrated in Fig 18 As- suming V, is as shown in Fig 18 a, the inte- grated difference signal appearing at summing node 36 will be that shown in Fig 18 c Both the first control signal of Fig 18 d and Q out- put of Fig 18 e will be unaffected by the inter- mittent operation and cyclical nulling and mea- suring periods of amplifiers 328 and 336 The embodiment of Fig 21 provides greater accu- racy at higher clock frequencies, but is otherwise functionally identical to the embodiment of Fig 19.

Modulator 30 used in the Fig 1 metering system can be used in other applications where it is necessary to provide modulated output signals which are indicative of the po- larity of the input signal Referring now to Fig.

23, an alternative embodiment modulator which provides such output signals may be seen Input signal IA, is supplied to summing node 36 through resistor 38 One of the two reference signals, which are preferably of equal magnitude and opposite polarity, are also supplied to the summing node through resistor 40 The reference voltages V 1 and V 1 + are connected to the summing node through a pair of switches 58 and 60, respec- GB 2178545 A 18 tively, which are controlled by the modulator output Instantaneous differences between in- put current 'Al and feedback current 'F at node 36 are supplied to an integrator, which pro- duces an ascending or descending ramp vol- tage The integrated signal is then compared against a threshold level by a comparator 50, which outputs a control signal indicating whether the output of the integrator is above or below the threshold level The output of comparator 50 is supplied to a bistable circuit, such as flip-flop 52.

The bistable circuit changes states only at predetermined clock intervals, as determined by clock 56 When the integrated signal crosses the threshold level of comparator 50, the outputs of bistable circuit 52 reverse states at the next clock pulse The Q output of bistable circuit 52, which is the first modu- lated signal of the present invention, controls switch 60, which connects the positive refer- ence voltage V 1 + to summing node 36 The d output, which is always the inverse of the Q output, operates switch 58, connecting the negative reference voltage V 1 to summing node 36 Switches 58 and 60 are always op- erated alternatively, meaning that one or the other of the reference signals is always sup- plied to summing node 36.

The Q output of bistable circuit 52 is con- nected to the D input of a second bistable circuit 53 and both receive clock signals from the same clock 56 Because of gating delays, changes in the Q output of bistable circuit 53 will always follow changes in the Q output of bistable circuit 52 delayed by one clock pulse.

An AND gate 350 is also provided to receive the Q outputs from both bistable circuits 52 and 53, as well as a clock signal from clock 56 The AND gate serves as means for out- puting a first digital signal which is propor- tional to the magnitude of one polarity of the input signal.

Fig 24 illustrates the operation of the above-described circuit elements Assuming, for illustrative purposes that the voltage wave- form at node 32 supplied to the alternative embodiment modulator is as depicted in Fig.

24 a, the signal is converted to a first modu- lated signal at the Q output of bistable circuit 52 in the manner described above The Q output of bistable circuit 52 is assumed to be that shown in the waveform of Fig 24 d The output of clock 56 is represented by the wa- veform of Fig 24 b The output of second bistable circuit 53 is termed "delayed Q" and is depicted by the waveform of Fig 24 e De- layed Q is substantially equal to Q, but de- layed in time by one clock interval The pre- sent invention calls for combining Q, Delayed Q and a clock signal at an AND gate 350 (see Fig 23).

Although not necessarily in idealized circuits in which component delays are nonexistent, for real-world components it is preferable to include an inverter 57 between clock 56 and AND gate 350 Inverter 57 inverts the clock signal to yield an inverted clock signal shown in Fig 24 c The reason for supplying an in- verted clock signal to the AND gate is because propagation delays in bistable circuits 52 and 53 will tend to cause their outputs to lag slightly behind the output of clock 56, and will produce short simultaneous "high" condi- tions in all three signals at thl wrong time.

The result of not inverting the clock is an extraneous spike output from AND gate 350, which would represent an error pulse For this reason, inverter 57 is included in Fig 23 The resultant waveform output by AND gate 350 is shown in Fig 24 f.

The Fig 24 f waveform is essentially a digi- tal representation of the amount by which the time Q is high exceeds the time Q is low In the example of Fig 24, waveform 24 f con- tains only two pulses, generated successively, and appearing at the right side of the illustra- tion Those two pulses roughly coincide with the region where the Fig 24 a input is most negative Preferably, the frequency of the clock will greatly exceed the variations of the analog input signal, to produce higher resolu- tions than that shown in Fig 24 The principle of operation is exactly the same, however In essence, combining a delayed modulated sig- nal with the original modulated signal at an AND gate produces an output which will go high only when Q remains high for at least two successive clock pulses The clock signal causes the AND gate output to be a pulse train, having pulses at intervals of not less than the clock intervals of the clock signal In the example just described, the AND gate out- puts pulses only when all signals supplied to it are high If Q is low for two or more suc- cessive clock pulses, it will have no effect on the output of AND gate 350 since only high inputs are measured Thus, the output of the AND gate is a representation of the magnitude of only one polarity of the input signal The output is, in effect, a half wave rectified sig- nal, represented digitally.

In order to produce a digital output propor- tional to the other polarity of the input wave- form, the alternative embodiment modulator utilizes the Q outputs of bistable circuits 52 and 53 as first and second inverse modulated signals, respectively Assuming the same input signal and clocks as shown in Fig 24, Q will be as shown in the waveform of Fig 24 g.

Bistable circuit 53 provides a delayed Q signal as shown in Fig 24 h Both signals are sup- plied to a second AND gate 352 (Fig 23), together with the inverted clock signal shown in Fig 24 C The output of second AND gate 352 is shown in the waveform of Fig 24 i and is termed a second digital signal The second AND gate serves as means for outputting a second digital signal which contains pulses in proportion to the amount of time by which GB 2 178545 A 19 one level of said first inverse modulated signal exceeds the other level When all three inputs to the AND gate are high, pulses are pro- duced at intervals of not less than the clock intervals of clock 120 In the present example, the waveform 24 i represents the positive polarity component of the input signal As can be seen The location of the pulses roughly correspondes with the regions where the Fig.

24 a input signal is high The Fig 24 i wave- form provides a digital representation of the magnitude of the positive half wave compo- nents of input signal.

Referring back to Fig 23, the present inven- tion can be further employed to produce a digital signal proportional to the magnitude of the full waveform of input signal This is ac- complished by supplying the first digital signal output of AND gate 350 and second digital signal output of AND gate 352 to an OR gate 351, which serves as gate means for combin- ing the digital signals and for outputting a summation digital signal shown in Fig 24 j.

The Fig 24 j waveform is proportional to the magnitude of the full input signal, including both polarities, which is termed herein "abso- lute magnitude" The outputs of AND gates 350 and 352 are coupled up and down inputs of an up/down counter 354 so that the num- ber of positive and negative pulses can be compared over any selected time interval.

Claims (14)

1 A metering system for measuring elec- tric power carried on a line, which includes means for monitoring current and voltage sig- nals on said line and for producing a first an- alog signal proportional to one of said current and voltage signals and a second analog sig- nal proportional to the other of said current and voltage signals, means for multiplying said first and second analog signals together to produce a product signal proportional to the power transported on the line, and means for converting said product signal to an output signal which is proportional over time to the value of said product signal and to the power carried on said line, and which includes N number of amplifier elements each having a plurality of inputs in at least one of said moni- toring, multiplying and converting means, an offset compensation system for substantially eliminating errors due to voltage offset be- tween selected inputs of each of said N ampli- fier elements, said offset compensation sys- tem comprising: N number of offset storage elements one of which is connected respec- tively to a selected first input of each said amplifier elements for receiving a compensat- ing voltage which substantially reduces the offset error at a selected second input of the amplifier element, wherein any difference be- tween said compensating voltage and the vol- tage offset of the amplifier element is an off- set error voltage appearing at said second in- put, and including a nulling circuit to be coup- led sequentially to each of said N amplifier elements and to the offset storage element associated therewith such that each said am- plifier element sequentially becomes the se- lected amplifier element being offset compen- sated, said nulling circuit first being coupled to said second input of said selected amplifier element during an intermittent transfer period to store said offset error voltage and then being coupled to said offset storage element coupled to said first input of said selected amplifier element to transfer charge to said offset storage element during an intermittent charging period following said transfer period, said offset compensation system including means for sequentially providing transfer and charging periods for each of said N amplifier elements such that offset errors in said meter- ing system are substantially eliminated.

2 A metering system as claimed in claim 1, in which said nulling circuit includes a charging amplifier, a temporary storage ele- ment coupled to said charging amplifier, and means for transferring said offset error voltage at said second input of said selected amplifier element to said temporary storage element during said transfer period utilizing said charg- ing amplifier.

3 A metering system as claimed in claim 2, wherein said offset compensation system includes means for coupling said temporary storage element between an input of said charging amplifier and a common ground dur- ing each said transfer period, such that vol- tage indicative of said offset error voltage is transferred to said temporary storage element, and including means for coupling said tempo- rary storage element between said charging amplifier input and output during each said subsequent charging period, such that a vol- tage proportional to said offset error voltage of said selected amplifier element appears at said output of said charging amplifier during said charging period.

4 A metering system as claimed in claim 3, wherein said offset compensation system further includes means for coupling said out- put of said charging amplifier to said offset storage element coupled to said selected am- plifier element during said charging period, such that a current is supplied to said offset storage element proportional to said offset er- ror voltage of said selected amplifier element to thereby adjust the voltage on said offset storage element in a direction which reduces said offset error voltage during the next trans- fer period of said selected amplifier element.

A system for offset compensating a plu- rality of amplifier elements up to N number of amplifier elements, each having a plurality of inputs, to substantially eliminate errors due to voltage offset between selected inputs of each of said amplifier elements, comprising: N num- ber of storage elements coupled to said N GB 2178545 A 20 amplifier elements such that one of said sto- rage elements is coupled to a selected input of said amplifier element, wherein said storage elements receive a compensating voltage which substantially reduces said voltage offset error at a selected second input of the associ- ated amplifier element which is indicative of a difference between said compensating voltage and said voltage offset of said amplifier ele- ment, and including a nulling circuit for se- quentially coupling to each of said N amplifier elements and to said storage element associ- ated therewith such that each said amplifier element sequentially becomes the selected amplifier element being offset compensated, said nulling circuit first being coupled to said second input of a selected amplifier element during an intermittent transfer period to deter- mine said voltage offset error and then being coupled to said storage element coupled to said first input of said selected amplifier ele- ment to transfer charge to said storage ele- ment during an intermittent charging period following said transfer period, said offset com- pensation system including means for sequen- tially providing transfer and charging periods for each of said N amplifier elements such that said offset errors at said second input are substantially eliminated.

6 An offset compensation system as claimed in claim 5, in which said nulling circuit includes a charging amplifier, a temporary sto- rage element coupled to said charging ampli- fier, and means for transferring said offset er- ror voltage at said second input of said se- lected amplifier element to said temporary sto- rage element during said transfer period utiliz- ing said charging amplifier.

7 An offset compensation system as claimed in claim 6, wherein said offset com- pensation system includes means for coupling said temporary storage element between an input of said charging amplifier and a common ground during each said transfer period such that a voltage indicative of said offset error voltage is transferred to said temporary sto- rage element, and including means for cou- pling said temporary storage element between said input and an output of said charging am- plifier during each said subsequent charging period, such that a voltage proportional to said offset error voltage of said selected am- plifier element appears at said output of said charging amplifier during said charging period.

8 An offset compensation system as claimed in claim 7, further including means for coupling the output of said charging amplifier to said storage element coupled to said se- lected amplifier element during said charging period, such that a current is supplied to said storage element proportional to said offset er- ror voltage of said selected amplifier element to thereby adjust the voltage on said storage element in a direction which reduces said error voltage during the next said transfer period of said selected amplifier element.

9 A method of metering electric power carried on a line by monitoring current and voltage signals on the line, producing a first analog signal proportional to one of said cur- rent and voltage signals and a second analog signal proportional to the other of said current and voltage signals, multiplying said first and second analog signals together to produce a product signal proportional over time to the power transported on the line, converting said product signal to an output signal which is proportional to the value of said product sig- nal and to the power carried on the line, wherein the metering system for accomplish- ing the method includes N number of amplifier elements each having a plurality of inputs, said N amplifier elements being used in performing at least one of the steps of monitoring, multi- plying and converting, and including the addi- tional steps of offset compensating said N amplifier elements to eliminate errors due to voltage offset between selected inputs of each of said N amplifier elements, each of said am- plifier elements being coupled respectively to an offset storage element at a first input thereof on which a compensating voltage is stored by the offset compensation steps of the method to substantially correct for any offset errors at a second input of the amplifier element, and wherein any difference between said compensating voltage on said offset sto- rage element and said voltage offset of the amplifier element is an offset error voltage appearing at said second input, said offset compensation steps including sequentially cou- pling a nulling circuit to each of said N ampli- fier elements and to the offset storage ele- ment associated therewith to offset compen- sate each selected amplifier element in se- quence, including first coupling said nulling cir- cuit to said second input of said selected am- plifier element during an intermittent transfer period to determine said offset error voltage, then coupling said nulling circuit to said offset storage element coupled to said first input of said selected amplifier element during an inter- mittent charging period following said transfer period to adjust the charge on said offset sto- rage element during said charging period, such that said offset error voltage during the next said transfer period of said selected amplifier element is reduced, and including the steps of sequentially providing for transfer and charging periods for each of said N amplifier elements in a continuous cycle.

A method as claimed in claim 9, in which said nulling circuit includes a charging amplifier and a temporary storage element having first and second terminals, said offset compensation steps further including coupling one input of said charging amplifier to said second input of said second amplifier element coupling said first terminal of said temporary storage element to a feedback path between i GB 2178545 A 21 an input and output of said charging amplifier and coupling said second terminal of said temporary storage element to a common ground during said transfer period, such that said off- set error voltage is transferred utilizing said charging amplifier to said temporary storage element, and then decoupling said second ter- minal from said common ground and coupling said second terminal to said output of said charging amplifier during the subsequent charging period whereby a voltage which is proportional to said offset error voltage ap- pears at sai output of said charging amplifier during said charging period.

11 A method as claimed in claim 10, in which said offset compensation steps further include the steps of coupling during each said charging period the output of said charging amplifier to said offset storage element through an impedance such that a current is supplied to said offset storage element pro- portional to said offset error voltage to thereby adjust said compensating voltage on said offset storage element in a direction which reduces said offset error voltage during the next said transfer period of the selected amplifier element.

12 A method of offset compensating a plurality of amplifier elements up to N number of amplifier elements, each having a plurality of inputs, to substantially eliminate errors due to voltage offset between selected inputs of each of said amplifier elements wherein each of said amplifier elements is coupled respec- tively to a storage element at a first input thereof on which a compensating voltage is stored by the steps of the method to sub- stantially correct for any offset errors at a second input of the amplifier element, and wherein any difference between said compensating voltage on said storage element and the voltage offset of the amplifier element is an offset error voltage appearing at said sec- ond input, comprising the steps of sequentially coupling a nulling circuit to each of said N amplifier elements and to the storage element associated therewith to offset compensate each selected amplifier element in sequence, including the steps of coupling said nulling cir- cuit to said second input of said selected am- plifier element during an intermittent transfer period to determine said offset error voltage, then coupling said nulling circuit to said sto- rage element coupled to said first input of said selected amplifier element during an inter- mittent charging period following said transfer period to adjust the charge on said storage element during said charging period, such that said offset error voltage during the next trans- fer period of said selected amplifier element is reduced, and including the steps of sequenti- ally providing for transfer and charging periods for each of said N amplifier elements in a continuous cycle.

13 A method as claimed in claim 12, in k which said nulling circuit includes a charging amplifier and a temporary storage element having first and second terminals, said method further including the steps of coupling one in- put of said charging amplifier to said second input of said selected amplifier element, cou- pling said first terminal of said temporary sto- rage element to a feedback path between an input and output of said charging amplifier and coupling said second terminal of said tempo- rary storage element to a common ground during said transfer period, such that said off- set error voltage is transferred utilizing said charging amplifier to said temporary storage element, and then decoupling said second ter- minal from said common ground and coupling said second terminal to said output of said charging amplifier during the subsequent charging period whereby a voltage which is proportional to said offset error voltage ap- pears at said output of said charging amplifier during said charging period.

14 A method as claimed in claim 12, fur- ther including the step of coupling during each said charging period the output of said charg- ing amplifier to said storage element such that a current is supplied to said storage element proportional to said offset error voltage to thereby adjust the voltage on said storage ele- ment in a direction which reduces said error voltage during the next said transfer period of the selected amplifier element.

Printed for Her Majesty's Stationery Office by Burgess & Son (Abingdon) Ltd Dd 8817356, 1987.

Published at The Patent Office, 25 Southampton Buildings, London, WC 2 A IAY, from which copies may be obtained.