FR2555381A1 - SYSTEM FOR PRODUCING DIGITAL SIGNALS PROPORTIONAL TO PARAMETERS CHOSEN FROM AN ENTRY SIGNAL - Google Patents

Abstract

THE INVENTION RELATES TO A SYSTEM FOR PRODUCING DIGITAL SIGNALS PROPORTIONAL TO SELECTED PARAMETERS OF AN INPUT SIGNAL CONVERTED INTO A FIRST MODULE SIGNAL VARIING BETWEEN TWO LEVELS. THE SYSTEM INCLUDES MEANS 56 FOR PRODUCING CLOCK PULSES AT DETERMINED CLOCK INTERVALS, DELAY MEANS 59 FOR RECEIVING THE FIRST MODULE SIGNAL AND DELIVERING A SECOND MODULE SIGNAL SENIABLY EQUAL TO THE FIRST AND DELAYED BY AN INTERVAL OF ' CLOCK AND MEANS 52 FOR DELIVERING A FIRST DIGITAL SIGNAL CONTAINING OUTPUT PULSES, AT INTERVALS WHICH ARE NOT LOWER THAN SAID INTERVALS, WHEN THE FIRST AND SECOND MODULATED SIGNALS ARE SIMULTANEOUSLY AT DETERMINED LEVELS, IN ORDER THAT THE FIRST SIGNAL IS NOT LESS THAN THE SAID INTERVALS AMPLITUDE AND POLARITY INFORMATION REGARDING THE INPUT SIGNAL. FIELD OF APPLICATION: MEASUREMENT OF ELECTRICAL ENERGY.

Description

The invention generally relates to circuits intended for

  producing one or more signals proportional to the power or other selected measurement parameter, and more particularly to an improved power measurement circuit and

  has a process that uses delta-less modulation

  sigma and an offset compensation system.

  Instruments for accurately measuring the electrical energy flowing through a line are an essential part of a user system

  electrical energy. The most common type of

  The measuring instrument used by the electricity user industry is currently the rotating disk meter which, in its basic form, is accurate and reliable, but which gives only limited information to the user regarding the use of power. In addition to total energy consumption in kilowatt hours, users often need to measure other parameters to properly determine the cost of supplying certain loads. Some highly reactive charges, for example, are more expensive to power because they induce a phase shift current / voltage known as the power factor. To determine the power factor, some measures have been

  standardized power. Two widely used measures

  These are the VARS (reactive volt-amperes) and Q. These are two power measurements proportional to the product of the line current and the voltage, the voltage being in backward phase shift, relative to the current, of 90 for VARS. and 60 for Q. At the same time as the overall power consumption, the VARS and Q values allow the user to measure the power factor for which it is usually

  penalized. Another interesting parameter for users

  is the polarity or direction of circulation of energy

  because some applications consume both

  energy and return it to the distribution network.

  There is a continuing need in the industry

  electrical current, measuring systems capable of measuring parameters such as VARS, Q and polarity, in addition to the total energy consumption. Various electronic measuring systems have been designed or proposed to replace the rotating disc measuring instrument. Examples of prior art electronic measuring systems are given in U.S. Patent Nos. 3,875,508, 3,955,138 and 4,182,983. These systems all use modulators that produce a signal at a time. Pulse modulation in width, proportional to the current or voltage, then use a time division or multiplication of intervals, which triggers or reverses the polarity of the other signal to obtain a signal produced. The pulses of the produced signal vary in amplitude with respect to an analog value (current or voltage) and vary in width with respect to the other analog value. A low-pass filter extracts the DC component of the produced signal, which is proportional to the power consumption. It would be advantageous to have a very precise measuring system, of electronic type, capable of displaying in

  know about energy values, both in kilowatts-

  hours and in VARS or Q. at the lowest possible cost.

  It would also be advantageous if such a measurement system could separately measure the net energy flow in each direction. The measurement system must also be virtually free of errors due to voltage offsets in the active circuit elements. The

  system must therefore advantageously include a

  offset compensation that can economically compensate for errors in elements

multiple amplifiers.

  The invention therefore relates to a measurement system and method for measuring the electrical power carried by a line. The system comprises means for controlling current signals

  and voltage present on the line. A first transducer

  The signal generator produces a first analog signal proportional to one of the current and voltage signals, and a second signal transducer produces a second analog signal proportional to the other of the current and voltage signals. A modulator modulates one of the analog signals to produce a first modulated signal that can alternate between two levels at first predetermined clock intervals so that the first modulated signal has a mean level, over any sufficient interval, proportional to the one, chosen, analog signals. First means of multiplication are intended to trigger

  the other analog signals in response to changes

  level of the first modulated signal, multiplying the analog signals together to give a product signal which is proportional to the power carried by the line. A converter then converts the produced signal into a first output signal which, in the preferred embodiment, can alternate

  between two levels at clock intervals of

  weaver, in a manner that is proportionate

  the signal produced and the power

line.

  The preferred measurement system according to the invention comprises a converter which separately measures the power at each polarity of the line and which comprises digital means for modifying the phase relationship between the analog signals to give a product signal proportional to a value. selected phase-related power system, such as VARS or Q. The system also includes an offset compensation device which corrects for voltage offsets in the various operational amplifiers of a measurement system to eliminate offset errors and

  to give a high precision. The compensation scheme

  The offset offset described corrects the voltage offset between the inputs of N amplifier elements. This offset compensation device comprises N elements

  offset memory which are connected to each other

  at one input of each of the amplifying elements to receive a compensation voltage which substantially reduces the offset error at the other input of the amplifier element. Any difference between the compensation voltage and the voltage offset of the amplifier element is expressed by a voltage

  of error that appears at the other input of the amplifier.

  The device comprises a cancellation circuit which can be successively connected to each of the N amplifier elements and to the offset storage element associated with each amplifier element so that all the amplifying elements are subject to

  turn, offset compensation. The cancellation circuit

  lation is first connected to the other input of the selected amplifier element during a transfer period

  intermittent to determine the error voltage.

  Then the cancellation circuit is connected to the offset storage element connected to the first input of the selected amplifier element during an intermittent charging period following the transfer period. The offset compensation device includes means for sequentially establishing the transfer and charge periods for each of the N amplifier elements to substantially eliminate

  offset errors of the measuring system.

  The invention will be described in more detail

  with reference to the accompanying drawings as examples

restrictions and on which:

  FIG. 1 is a simplified diagram of a system for measuring the power of a line according to the invention; FIG. 2 is a diagram of the circuit of the first modulation part of the measurement system shown in FIG. 1; FIG. 3 is a diagram of the circuit of the first output conversion part of the measurement system shown in FIG. 1; FIGS. 4A to 4G are timing diagrams showing selected internal and output signals generated during operation of the measurement system shown in FIGS. 1 to 3; FIGS. 5A to 5I are timing diagrams showing various internal and output signals produced by the converter of FIG. 3 during the measurement of signals of different polarities; FIG. 6 is a diagram of a circuit of another embodiment of a modulator that can be used in the power measurement system according to the invention, introducing a forward phase shift in the modulated output signal; FIGS. 7A to 7G are timing diagrams showing selected internal and output signals produced by the modulator of FIG. 6; FIG. 8 is a simplified diagram of a measurement system according to the invention which comprises an apparatus for producing VARS and Q measurements; Fig. 9 is a diagram of a signal multiplier circuit which may be used in the measurement system of Fig. 8 and which includes a digital phase control circuit for producing VARS and Q measurements; FIGS. 10A-10H are timing diagrams showing selected internal and output signals produced in the multiplier of FIG. 9; Fig. 11 is a diagram showing further details of the digital phase setting circuit of Fig. 9; FIGS. 12A to 12D are timing diagrams showing a selected phase adjustment of a

  modulated signal produced by the multiplier of the

  re 9; FIG. 13 is a diagram of one embodiment of a voltage offset compensation device used in the system according to the invention; FIG. 14 is a graph showing the variation of the error voltage produced in FIG. the compensation device of FIG. 13; FIG. 15 is a circuit diagram of a voltage offset compensation device of the type shown in FIG. 13, for an entire power measurement system; Fig. 16 is a timing chart showing the operation of the offset compensation device of Fig. 15; FIG. 17 is a diagram of a second embodiment of the modulator used in the power measurement system of FIG. 1; FIGS. 18A to 18E are diagrams

  times showing various signals produced by the modula-

  of Figure 17; Fig. 19 is a circuit diagram of the modulator of Fig. 17 including an alternative voltage offset compensation device; - Figure 20 is a timing diagram

  showing the control signals of the compensating device

  voltage shift arrangement of FIG. 19; Fig. 21 is a diagram of another embodiment of a modulator for use with the measurement system of Fig. 1, including a voltage offset compensation circuit; - Figure 22 is a timing diagram

  showing the control signals of the compensating device

  offset arrangement of Fig. 21; Fig. 23 is a diagram of another embodiment of a modulator and an associated dual polarity output circuit; and - Figures 24A-24J are diagrams

  times showing various signals produced by the modula-

  Figure 23 and the associated output circuit.

  FIG. 1 diagrammatically represents the measurement system according to the invention which constitutes a means for measuring the electrical power traveling through a line of energy, from a source 12 to a load 14. The current of the line 10 is indicated globally in I and the voltage-in VL. The system includes control and signal conditioning means

  such as transformers 16 and 18, intended to control

  or detect respectively VL and IL. Transformer 16, constituting the first signal means, produces a first analog signal IA1 proportional to VL on line 20. Transformer 18, constituting the second signal means, produces a second analog signal IA2 proportional to IL on a line 22. A shunt resistor 24 is connected across the secondary winding of the transformer 18 so as to be traversed by most of the current flowing on the line 22. The shunt resistor 24 provides a low impedance path for the passage of the current and it can be chosen so as to determine the

  overall range of current signal IA2 of line 22.

  A2 The system and measurement method according to the invention work by multiplying together the first and second analog signals IA1 and IA2 carried

  lines 20 and 22 respectively and then

  weaving the signal of the multiplication product into a suitable digital form. In general, this is done by modulating one of the signals and then triggering, or switching, the other of the signals to give a complex signal or product having

  an average value proportional to the power.

  It is obvious to those skilled in the art that the current or voltage could be modulated, and that the resulting modulated signal could be used to trigger the other of the two analog signals to provide the produced signal. Therefore, the designation of the first and second analog signals as voltage and current signals, respectively, could be reversed without the fundamental operation of the

  measuring circuit shown in Figure 1 be modified.

  Similarly, the designations of the first and second signal detectors could be reversed

in the same way.

  The measurement system comprises a device for multiplying between them IA1 and IA2 signals to give a product signal which is proportional to the power transported on the line. To achieve the necessary multiplication, the voltage signal IA1 is first applied to a first modulator circuit which constitutes a modulator means for converting the analog voltage signal IA1 into a first signal.

  modulated which can alternate between two levels at inter-

  predetermined clock valleys. In accordance with

  In the case of delta-less-sigma modulation, the first modulated output signal has a mean level, over any sufficient interval, which is proportional to the first analog signal applied to the input 32 of the modulator. As shown in FIG. 2, the analog signal (voltage) IA1 is applied to a node 36

  summation via impedance 38.

  The modulator 30 includes a feedback element for producing a feedback signal IF which is also applied to the summing node 36. IF depends on the output signal of the modulator, called the first modulated signal, which appears on a line 34. One or the other of two reference sources Vl + and Vl- are connected

  alternatively at the summing node 36 via

  impedance 40 as a function of the level of the first modulated signal. The IF feedback signal oscillates between the positive and negative reference sources in a manner that, over time, balances the first analog signal IA1. The instantaneous differences between IF and the first analog signal give an Idiff difference signal at the output of the summing node 36. The instantaneous difference between input and feedback signals, ie Idiff, is integrated

  and measured by a measurement circuit 42 of the modulator.

  The measurement circuit 42 comprises an active integrator comprising a capacitor 44 as part of

  reaction of an operational amplifier 46 to inversion.

  The signal appearing at the output 48 of the amplifier has a slope increasing or decreasing according to the polarity of Idiff. The integrated signal at 48 is compared to a threshold level of the modulator by a comparator

  which goes high when the signal is higher than

  at the modulator threshold level and at a low level when the signal is below

of the modulator.

  The output signal of the comparator 50 is

  applied to the input D of a bistable circuit 52 of the modula-

  tor. The Q output of the bistable circuit 52 gives the first modulated signal. The bistable circuit 52 changes only at first predetermined clock intervals which depend on an external clock. A clock suitable for this purpose consists of a conventional oscillator 54 and a frequency divider circuit.

  56, shown in Figures 1 and 2. For simplicity,

  cited, the time interval between the pulses produced by the frequency divider 56 is called the first clock signal. The bistable circuit 52 has a Q output and an Q output. The Q output is the inverse of the Q output. The two Q and Q outputs are used to control the IF feedback signal by acting on two switches 58 and 60 , respectively. Since the outputs Q and Q are in inverse relation to each other, only the output Q is considered here as giving the first modulated signal. It suits

  note, however, that both Q and Q outputs contain

  denote the information represented by the expression "first modulated signal", and that the line 34 designates the lines traversed by the two Q and Q signals. Since the first modulated signal is emitted via the bistable circuit 52, the first modulated signal present on line 34 can alternate between two levels at the first predetermined clock intervals. Although the level may not change at each clock interval, the modulator circuit ensures that when the first modulated signal changes level, this change occurs only at the first predetermined clock intervals and not at other times. . Changes between the high and low levels of the first modulated signal produce a simultaneous switchover of the switches 58 and 60 and corresponding inversions of the polarity of the IF feedback signal at the summing node 36. When the integrated difference signal passes through the threshold level of the comparator 50 when going up or down, level changes appear at the output of the comparator. At each clock interval, the bistable circuit 52 determines whether the output of the comparator 50 has changed and, if so, produces a corresponding change of the Q and Q outputs. The amplitude of the analog input signal causes a directly proportional variation of the time interval during which the first modulated signal is at a given level. Therefore, the first modulated signal has a mean level or an average amplitude at one or both of its two levels, or between its two levels.

  and, over any sufficient period of time, this ampli-

  average study is proportional to the analog signal

input.

  As an example of how the modula-

  If the signal at the input 32 is zero, the output Q of the bistable circuit 52 will be high for exactly the same duration as it is low, giving an average level situated exactly midway between the high and low levels. of the Q output. If the signal at the input 32 is of positive value, the positive current arriving at the summing node 36 must be balanced by a larger negative current applied to the summing node by the negative reference Vl-, by the switch 58. Therefore, the Q output will be proportionally

  is high and the switch 58 will be closed and the switch

  60 for a longer duration than in the opposite situation. If the input signal is negative, the positive feedback reference must be applied longer for IF to balance the input signal, and the Q output will be high for longer than it is low. A characteristic of the modulator according to the invention is that the output Q can remain high or

  low for the time it takes for IF to balance

  break the input signal to the summing node.

  To produce a current signal to be multiplied with the modulated voltage signal, the system comprises means for producing inverted and non-inverted representations of the line current IL. With reference to FIG. 1, the current analog signal IA2 is first applied to a

  gain amplifier 70, after which the signal is applied

  An inverting circuit 72. The inverting circuit shown comprises an operational amplifier

  74 and gain control resistors 76 and 78.

  The amplified signal IA2 is applied to the invert input

  amplifier of the amplifier 74 which is mounted to have a gain of 1. The inverted signal is then applied to one of two switches which together form a first trigger device 80. The inverted signal arrives at a switch 82 and a second line

  84 transmits the non-inverted amplified signal IA2 to a

  It should be noted that a suitable center-plug-in transformer could be used in place of the second transformer 18, in which case the signals transmitted to the switches 82 and 86 could

  come directly from the transformer.

  The Q and Q outputs of the bistable circuit of

  modulator 52 are used for controlling the

  82 and 86 to trigger the second signal

  analog IA2 in response to the first modulated signal.

  Since the Q output is the inverse of the Q output, the switches 82 and 86 are controlled in a controlled manner.

  alternate, so that the output 88 of the trigger means

  This provides a modulated analog signal modulated between positive and negative polarity. Such a triggering operation is usually called

  temporal division or amplitude-interval modulation.

  The switches 82 and 86 perform the multiplication of the two analog signals representing the current

  and the voltage of the power carried by line 10.

  The resulting signal, called the generated signal, appears at the first output 88 of the triggering device and is proportional to the power output.

by line 10.

  As shown in FIG. 1, the signal produced coming out of the first triggering device

  is applied to a first converter circuit 90.

  The converter circuit converts the produced signal into a first output signal, on a line 92, this first signal being able to alternate between the two levels,

  at predetermined clock intervals of the converts

  proportional to the signal produced.

  The converter 90 essentially operates as a low-pass filter which extracts the DC component or the average value of the signal produced. The first resulting output signal is proportional to the power

carried by line 10.

  With reference to FIG. 3, the converter is essentially a delta-less-sigma modulator of a type similar to modulator 30, designed to produce

  separate modulated output signals which are proportionally

  each polarity of the input signal. To simplify

  the description, we will first describe the converter

  and its operation according to a first working polarity. The components inside the frame 94 include all the elements used in one-polarity operation. In the following example, we assume that the signal produced to convert

  is predominantly positive, which is assumed to correspond to

  to a flow of energy on the line 10 of the source 12 to the load 14. As in the modulator 30, the input signal of the converter

  , designated I (product signal), is initially

  It is provided by a summing node 96 via an impedance 95. A feedback device applies a second signal 12 to the summing node from one of a plurality of reference sources. For a positive polarity operation, the reference sources alternate between a negative reference source 98 (VR-), connected via a switch

  , and a ground connection 102, connected by the

  As a result of the fact that only the positive values of the signal produced are considered, the switching of the signal I2 between the mass value and the negative value will be sufficient to balance

  with time the signal produced, at the summing node 96.

  As previously described for the modulator

  , any difference between the product signal I and the

  Fig. 12 is a difference signal which is applied to a measurement circuit 106. The latter integrates the difference signal and compares it with a first threshold level. The preferred embodiment of the measuring circuit shown in FIG. 3 comprises an active integrator 107 consisting of an operational amplifier 108 and a capacitor 110 as a reaction element. The voltage at the output 112 of the amplifier has a rising or falling slope depending on the polarity of the difference signal at the summing node 96. The integrated difference signal at 112 is applied to a first comparator 114 which has a threshold set at a first selected level. When the integrated difference signal at 112 is greater than the first threshold level, the output of the comparator 114 is high. When the integrated difference signal is less than the first threshold level, the output

comparator 114 is low.

  The output signal of the comparator, called the first control signal, is applied to the input D of a bistable circuit 118 via a line 116. The output Q of the bistable circuit 118 must alternate only at different intervals. predetermined converter clock, which are advantageously

  longer than the first clock intervals associated with

  to the modulator 30. The converter clock intervals may be produced by adding a second frequency divider 120 to the first clock

  56. The time intervals between the pulses produced

  by the frequency divider 120 are called inter-

  clock valleys of the converter, and the frequency divider is called converter clock. The Q output of the bistable circuit 118 gives the first output signal which controls the switches 100 and 104 to determine the operation of the feedback device.

  which applies the second signal 12 to the summing node 96.

  The switch 104 is controlled via a gate 122 which delivers a high level signal so as to close the switch only when its two inputs 124 and 126 are low. Gate 122, as shown, is a conventional NAND gate. During the periods of presence of positive product signals,

  input 126 remains low, as described below.

  Therefore, when the Q output is high, the switch 100 is closed, connecting VR- to the node 96 of

  summation, and when the output Q is low, the switching

  100 is open and the switch 104 is closed.

  The procedure and the method implemented by the measuring system according to the invention will be

  now described with reference to Figures 1 to 4G.

  For simplicity, it is assumed that the energy

  runs line 10 mainly in the positive direction.

  The voltage on line 10 is shown in FIG. 4A as a sinusoidal alternating current. The current IL is represented in FIG. 4F as having an increasing value indicated by a curve 128. The first step consists of a detection, by the transformers 16 and 18, of the current and voltage signals and in the production thereof, in response to this

  detection, analog signals IA1 and IA2 which are pro-

  proportional to the voltage and current of the line, respectively. One of the analog signals, the voltage signal IA1 in the preferred embodiment, is then applied first to the first modulator 30. FIG. 4C shows the integrated difference signal

  produced in the modulator 30 by the modula-

  delta-less-sigma described above. The integrated difference signal is applied to the measuring circuit 42. FIG. 4B illustrates the first clock intervals produced by the first clock 56. As can be seen, the slope of the integrated difference signal of FIG. changes only at predetermined clock intervals established by the signal of the first clock. Since the bistable circuit 52 is triggered by the passing of the leading edge of each progressively increasing pulse, the predetermined intervals of the first clock are represented as starting at the points identified in a, b, c, d, etc. in the figure. 4B. The integrated difference signal is then applied to the comparator 50. The line 103 in FIG. 4C represents the threshold level of the modulator in the comparator 50. It should be noted that the integrated difference signal changes slope at the beginning of each interval. clock after passing through the threshold 130. The output signal

  comparator 50 is shown in FIG. 4D.

  When the integrated difference signal is below the threshold 130, the output of the comparator is low, and when the integrated difference signal is greater than the threshold 130, the output of the comparator is high. The output signal of the comparator is then applied to the input D of the bistable circuit 52 which produces the output signal Q or the first modulated output signal, illustrated in FIG. 4E. The output signal Q is the result of the modulation of the voltage signal and it can alternate between two levels at predetermined intervals of

the first clock.

  Since the bistable circuit alternates only at the predetermined clock intervals shown in FIG. 4B, the variations in the output

  Q are slightly behind those of the release of the

  shown in Figure 4D. Next level

  precision requested. in the multiplication device

  signal, it may be desirable to compensate for this slight delay of the modulated signal introduced by the bistable circuit 52. Such a correction can be made by inserting an RC network in the line to introduce a small phase shift before in

  the signal IA1 on arrival at the input 32 of the modulator.

  Another technique may be to induce a slight

  delay in the current analog signal IA2. A third

  second variant, using a delta-less modulator

  sigma comprising a digital phase shift circuit before, will be described below. The entered phase setting, which is equal to only a fraction of an interval of the first clock, must correspond to the delay average induced by the delay of the Q signal.

  relative to the output signal of the comparator.

  Figure 4F shows analog signals

  equal and opposite, proportional to the current IL of the line.

  Line 128 represents a rising current signal and line 129 represents the inverse signal produced

  by the inverter 72. The next step consists in

  the analogue current signal with the aid of

  trigger 80. The output of this trigger device gives the product signal indicated by curve 131 in FIG. 4G. Curve 131 is obtained by switching between signals 128 and 129 in response to the first modulated signal shown in FIG. 4E. The average level or the continuous component of the curve 131 is represented by a line 132 on the

Figure 4G.

  In the example given, it is assumed that the energy flows mainly in one direction, towards the load 14. Consequently, the signal produced 131 shown in FIG. 4G is mainly of positive polarity, represented by the line 132. It is assumed, to describe the operation of the converter 90, below, that the produced signal has a positive predominance and a positive average value. Although the actual polarity of the signal produced is a matter of choice, the signal produced is mainly of a first polarity when the energy traveling on the line 10 is of a first polarity, the energy flowing in a first direction, and it is mainly of a second polarity when the energy of the line 10 is of a second polarity, opposite & the first, the energy

then moving in the opposite direction.

  The following step consists in converting the product signal Ip into a first output signal that can alternate between two levels at predetermined interlinks, in a manner proportional to I. Reference will now be made to FIGS. 3, 4A to 4G. and 5A to 5I. the product signal Ip, shown in FIG. 4G, is applied to the converter 90. The signal Ip and the second signal 12 are all

  both applied to the summation node 96 where the difference

  The integrator 106's constant is selected to be long relative to the switching frequency of the first modulator 30. The converter can thus behave as a low-pass filter. , only reacting to the DC component, or their average, of the product signal I. This is the reason why I is represented in FIG. 5A as an unbroken analog curve, although in

  it varies in the manner shown in Figure 4G.

  Figure 5A represents only the average value

  of Ip. The time scale of Figure 5A is consid-

  compressed compared to that of the figure

  4G. For purposes of illustration, it is assumed that an interval

  134 of Figure 5A is equivalent to the entire length of curve 132 of Figure 4G. Figure 5B shows the converter clock intervals

by the clock 120.

  Considering only a positive energy flow, illustrated between the times to and t1 in FIG. SA, it can be seen that the integrator 106 delivers at its output an integrated difference signal (IDS) as represented in FIG. 5C. The integrated difference signal rises and falls relative to the first threshold level TL1 of the comparator 114. The integrated difference signal (IDS) is applied to the comparator 114 where it is compared to the first threshold level TL1. The comparator 114 outputs a control signal 133 on a line 116, as shown in FIG. 5D. The next signal produced is the first output signal shown in FIG. 5E which is transmitted via a bistable circuit 118. The control signal 133 changes level according to the level of the integrated difference signal with respect to the threshold TL1 . When the signal (IDS) is greater than the threshold TL1, the signal 133 is high and when the signal (IDS) is lower than TL1, the signal 133 is low. The next step consists in transmitting the first output signal represented in FIG. 5E, via the first bistable circuit 118. The first output has a mean level proportional to a first power polarity

  on line 10, on any sufficient time interval.

  It can alternate only at predetermined converter clock intervals, illustrated in w, x,

y and z in Figure 5B.

  The single-polarity operation of the converter 90 involves a switching of the feedback signal 12 between a first reference source 98 and a second reference source 102, as follows.

  the level of the first output signal (Figure 5E).

  Since the second reference source 102 is a ground connection, the portion of the converter 90 described so far does not deal with a negative direction of energy flow on the line 110. When the flow of energy ( Ip) becomes negative, as is the case between the times t1 and t2 in FIG. A, another circuit forming part of the converter 90 is used. As shown in FIG. 3, the convector 90 comprises a second comparator 140 which receives the output signal from the integrator 107. The comparator has a second threshold level TL2 which is different from the first threshold level of the comparator 114. Threshold levels must be set to be sufficiently spaced to accommodate the greatest expected variations of the integrated difference signal output from integrator 107, without the latter going through

  simultaneously by the threshold levels of the two comparisons

  tors. The integrated difference signal is applied to the direct input of comparator 114 and to the inverting input of comparator 140, so that their

  Outputs are of opposite polarity. The output of the

  140 becomes high when the integrated difference signal is less than the second threshold level in the comparator 140, and goes to a low level when the integrated difference signal is higher than the second threshold level in the comparator 140;

  at the second threshold level in the comparator 140.

  The output signal of the comparator 140 is applied to the input D of a second bistable circuit 142 which, by its output Q, delivers a second output signal placed at one of two levels according to the level of the difference signal. integrated with respect to the second threshold level at each of the converter clock intervals. The second output signal is applied to an input 126 of a NAND gate 122 and a switch 146 for connection of a third reference source VR + to the summing node 96. The feedback signal 12 is therefore controlled by the level of the second output signal, which has a mean level proportional to the power of second polarity

by line 10.

  The operation at the second polarity of the converter 90 will be described with reference to FIGS. 3 and 5A to 5I. After time t1, the flow direction of the energy is reversed and the product signal I begins P to withdraw from the summing node 96. In reference

  in FIG. 5C, immediately before the instant t1, the

  The integrated difference signal goes down, which means that the negative reference source VR- is connected to the summing node via the switch 100. At the clock imph! sioh following the passage through the first threshold level TL1 , switch 100 opens and switch 104 closes, connecting the summing node to ground. Since the product signal Ip is negative after time t1, the integrated difference signal continues its integration downwards until it reaches the second threshold level TL2 of the comparator 140 when its output 135 passes. at the high level (see Figure 5G). At the next clock interval of the converter, after the high level of the comparator 140 has passed, the Q output of the bistable circuit 142 (the second output signal) becomes high, as shown in FIG. 5H. When the second output signal goes high, a switch 146 connected to the third reference source 148 (VR +) closes. The third reference source supplies a positive current 12 to the summing node 96 so

  counterbalance the negative product signal I and

  p pass the IDS signal by the threshold TL2. As this threshold TL2 passes, the signal 135 becomes low again, causing the second output signal to go low.

  at the next clock interval. During the operation

  at the second polarity, the first output signal (FIG. 5E) remains low and, when the second output signal (FIG. 5H) is low, the two inputs of FIG.

  the gate 122 are low and its output becomes high.

  When the output of the gate 122 becomes high, the switch 104 is closed and the reference source 102 connected to the ground is connected to the summing node 96. When the switch 104 closes, the IDS signal is allowed to go back in the other direction by the threshold TL2. During the interval between times t1 and t2, when the energy flows in negative direction, the integrated difference signal is maintained in the vicinity

the second threshold level TL2.

  The converter 90 shown in Figure 3 has three different reference sources, the second is a common ground connection for the measuring circuit. Given the configuration of the circuit elements, the ground connection is used when the integrated difference signal is in the area between the first and second threshold TL1 and TL2. It is not essential that the second

  reference source is a connection to the ground.

  Separate positive and negative reference sources

  could be used for each polarity of function

  if desired. In this case, the first and second reference sources are used

  to apply the second signal 12 to the node 96 of

  when the signal produced I is of a first p polarity, and the third and fourth separate sources

  reference data could then be used to

  send the second signal 12 to the summing node 96 in

  the case where the product signal Ip is of the other polarity.

  In practice, the selection of the values for the reference sources depends on the need to maintain the integrated difference signal in the vicinity of the threshold level of the comparator in use. Amplitudes and polarities of reference sources

  are otherwise totally a matter of choice.

  Using in the converter 90 of

  reference sources which include at least one

  grounding, the overall accuracy of the modulated output signals is improved. While variations may affect the reference sources of voltage

* positive and negative, the ground connection remains fixed.

  If one of the positive and negative reference sources, or both sources, are above or below their correct value, an error will appear at a level slightly longer or shorter than it should be, because, while the voltage reference source provides the feedback signal, it also provides slightly too much or slightly too little current; The closer the input signal is to ground (zero), the smaller the error. Equal and opposite reference sources, such as those used in the feedback device of the modulator 30, have a greater error potential in case of disagreement between the reference voltages V1 + and V1-. Since the modulator 30 feedback device always alternates between V1 + and V1, any error resulting from a mismatch of the reference voltages tends to place the modulated output signal at one or other of the levels for a period of time. incorrect, regardless of the amplitude of the input signal. This is not a problem in the case of the modulator 30, since the latter modulates the line voltage signal, which generally varies only by a small value. Precision must therefore be maintained only over a narrow range. However, the converter requires greater precision because of the wide variations in the signal produced representing the power of the line. This is the reason why the separation of the operations carried out by the converter between positive and negative polarity of power presents clear advantages. Since only one polarity is measured by each comparator, the reference sources may use a ground connection to produce the feedback signal, which improves the overall accuracy of the converter. The information provided regarding the energy flow of each polarity is also desirable, as it provides additional data regarding the nature of

  the load and its energy requirements.

  The first and second output signals appearing on lines 92 and 144 of the converter (see FIG. 1) can alternate between two levels at the converter clock intervals. To produce an output signal appropriately in digital form, a signal in which the pulse density is proportional to the energy flow rate, a device for converting the output signals into pulse trains is provided. With reference to FIGS. 1 and 5, the first and second output signals are respectively applied to first and second AND gates 150 and 152. A second input of each

  doors AND is connected to the clock 120 of the converts

  sor. Figure 5F shows the pulse train produced

  by the AND gate 150 for a first polarity of

  ciency. This train has a proportional pulse density

  This is similar to the amplitude of the energy flowing in a direction on the line 10. Similarly, in the case of a flow of energy in the opposite direction, FIG. 5I represents a pulse train corresponding to a power of a second polarity and issued by the AND gate 152. Various means can be used to process the first and second digital output signals respectively shown in Figures F and 5I. For example, it is convenient to apply the digital signals to a device for counting the positive and negative polarity pulses. The meter can then deliver a display signal

  or a signal recording the total energy consumption

  ogy. The counter 154 represents an example of this display concept. If, in addition, a trigger signal is applied to the counter 154, power measurements in appropriate units, for example in kilowatts, can be easily obtained. Separate measurements of energy flow in each direction can also be obtained. As noted above, since the bistable circuit 52 (FIG. 2) can only alternate at predetermined clock intervals, a light

  delay is introduced into the modulated output signal.

  Figure 6 shows a new delta modulator

  less-sigma 30 'having a digital circuit of

  forward phase shift to compensate for phase delay.

  The elements common to the modulators of FIGS. 2 and 6 bear the same numerical references. It should be noted that such a forward phase shift digital circuit is suitable for applications other than power measurement systems. In addition, if desired, a phase shift can be established before more than enough to compensate for the rear phase shift due to the bistable circuit.

52 of the output of FIG.

  The modified modulator 30 'of FIG. 6, as well as the modulator of FIG. 2, comprises a bistable circuit 52 controlling a source of feedback current IF via switches 58 and 60. A summing node 36 receives the signal

  IA1 through a resistance of

  38. The instantaneous differences between the reaction and input signals are represented by Idiff and this

  difference signal is measured by a circuit 42.

  The control signal output from the comparator 50 is high when the integrated difference signal is greater than the threshold of the comparator and is low when the integrated difference signal

is below the threshold.

  The modulator 30 'differs from the modulator

  of Figure 2 in that it includes a device

  digital shifter between the measuring circuit 42 and the bistable circuit 52. The digital shifting device introduces a delay in the control signal output from the comparator 50. In FIG. 6, the digital shifting device is constituted by a bistable circuit. 59 which receives at its input D the control signal coming out of the comparator. For the purposes of an example given below, the bistable circuit 59 is controlled at the same frequency as the bistable circuit 52, but with a phase shift corresponding to

  an interval of half a clock period.

  The operation of the modulator shown in Fig. 6 to introduce a forward phase shift into the modulated output signal will be described with reference to Figs. 7A-7G. The input signal IA1 of the modulator is shown in FIG. 7A. The output signal

  of the first clock 56 is shown in Figure 7B.

  The first clock 56 also provides the signal to the bistable circuit 59 through an inverter 57, and the second clock signal is shown in Figure 7C. If the signal IA1 is positive at the clock pulse a and the output Q of the bistable circuit 52, represented in FIG. 7G, is initially high, IF will be positive on arriving at the node 36 of

  summons. This gives a positive signal Idiff which is ap-

  plicated to the inverting input of the integration amplifier 46, which has the effect on the signal of

  integrated difference, in point 47, to descend initially

  as shown at 21 in Figure 7D. Line 22 of FIG. 7D represents the threshold of comparator 50. When the integrated difference signal passes through threshold 22, the control signal shown in FIG. 7E changes from the high level to the low level. If it is assumed that the bistable circuit 59 is triggered by the upwardly moving pulses a ', b', c ', d', e ', etc., the output of the bistable circuit 59 is leveled. high at the low level at clock pulse a '. The output Q 'of the bistable circuit 59 here gives the delayed control signal, which is then applied to the input D of the flip-flop circuit 52. Fig. 7F shows the delayed control signal and Fig. 7G shows the output signal Q of the bistable signal 52. When the output Q 'goes from the high level to the low level, the output Q of the bistable circuit 52 also switches from

  high to low level at the next clock pulse

  te b. The change of the Q output causes the switch 60 to open and the switch 58 to close and negates the IF signal. The integrated difference signal then has an upward slope, passing through the threshold 22 of the comparator and making again

  go high on the control signal. At the impulse

  clock of the second clock, the output

  Q 'of the bistable circuit 59 becomes high again.

  This causes the high level of the Q output of the first flip-flop 52 to go to the clock pulse.

next e.

  The process described above continues, the Q output of the bistable circuit 52 providing the signals for controlling the modulator feedback loop. Assuming that the delay introduced by the digital offset device constituted by

  the bistable circuit 59 is not sufficient to generate

  to cause instability in the feedback loop, the modulator 30 'produces a modulated signal which is equivalent to

  without being identical to that of the output of the modula-

  30. By equivalence, it is meant that the Q output of the bistable circuit 52 is a modulated signal

  alternating with first predetermined clock intervals

  in proportion to the input signal of the modulator. The output Q 'of the bistable circuit 59 is ahead of the output Q of the first bistable circuit 52 by a value depending on the difference between the

  clock signals applied to the two bistable circuits.

  This advance appears as a natural consequence of the fact that the Q output of the bistable circuit 52 only changes at the clock pulse following a change of the output Q 'of the bistable circuit 59. The output Q' therefore produces a signal which actually "precedes" that of the Q output. The output signal on the line 34 has a front phase shift equal to half an interval of the first clock, with respect to the signals of the Q and Q outputs of the bistable circuit 52. Being given that the clock intervals applied to the two bistable circuits 59 and 52 are the same, the control signal

  delay on lines 34 alternates with the same

  valles that the Q and Q outputs of the bistable circuit 52 and otherwise resembles any other delta-less-sigma modulation signal. The clock signal applied to the bistable circuit 59 in fact becomes the decisive clock signal that governs the changes affecting the output of the modulator. It would be possible to use any other type of digital shift device, for example a multistage shift register in place of the bistable circuit 59, provided that the introduced delay is not long enough to destabilize the feedback loop. The digital offset device used could be controlled at a clock frequency different from that of the first bistable circuit 52, although this would change the characteristics of the delayed control signal. If, for example, a multi-stage shift register, controlled by the high frequency clock pulses, were inserted in place of the bistable circuit 59, it would delay the control signal by a selected number of short intervals. The output signal of such a shift register would be a delayed command signal that could alternate

  at the higher clock rate. We could also

  use a shift register with different stages controlled by clock pulses

  at different frequencies. In such a configuration

  The longer clock interval used to control any of the stages would determine the intervals at which the delayed control signal could alternate. Any device for delaying the control signal shall comprise at least one bistable circuit controlled by clock pulses at different intervals so that the modulated modulator output signal (the control signal

  delayed) can alternate at these separate intervals.

  The forward phase shift produced in the modulator can be chosen. This choice is obtained. This choice is obtained by adjusting the clock signals applied to the bistable circuits 52 and 59. Assuming that a first clock signal producing pulses at first clock intervals is applied to the bistable circuit 52 and that a second clock signal, producing pulses at. second clock intervals, is applied to the digital shift device (bistable circuit 59), and that the first and second clock intervals are equal, the phase offset between the clock signals determines

  the importance of the advance of the modula-

  tor. In the example described with reference to FIGS. 7A to 7G, the second clock signal is the inverse of the first clock signal and the total offset is equal to half of a clock interval. If the clock pulses applied by the second clock to the bistable circuit 59 preceded by three quarters of a clock interval the pulses applied to the bistable circuit 52, a phase shift would be obtained before three quarters of a clock interval. The duration of the advance time of the signal transmitted on the lines 34 is determined by the importance of the delay between a change of the signal of the output Q 'of the bistable circuit 59 and the output

Q of the bistable circuit 52.

  The importance of the forward phase shift that can be obtained with the modulator of FIG. 6 depends on the degree of delay that can be introduced into the loop.

  reaction of the delta-less-sigma modulator, without

  to destabilize it. However, it is known that a delay of a fraction of a clock pulse, as described in the example above, is functional and produces the forward phase shift in the modulated signal,

as described.

  FIG. 8 represents another embodiment of the measurement system according to the invention which performs an additional measurement of power output in VARS or Q as described in the preamble.

  of the present application, the values VARS and Q represent

  measures of power in which a rela-

  determined phase is introduced between the current and voltage signals. The value VARS is obtained by multiplying the current by a rear phase quadrature voltage signal; the Q value is obtained by multiplying the current by a back-phase voltage signal of 60. In the measurement system of this embodiment of the invention, the value VARS, Q or other desired power value, in relation to the phase, can be easily obtained by delaying a selected value of the modulator output signal. 30. This delay can be conveniently produced using a delay device such as

  that a shift register, in the manner described above,

  below. The Q output of the modulator 30 of the embodiment of FIG. 8 provides signals to both the trigger device 80 and the shift register 160. The latter delays the output signal of the modulator 30 by a selected interval. The magnitude of the delay depends on the desired power value (VARS or Q), in selected phase relation, as well as the frequency of the alternating current as measured (50 or 60 Hz). To simplify the circuit, only the

  signal of the Q output of the modulator 30 is applied to the

  shift register 160. The delayed output signal of the shift register is then applied to an inverter

  161, and the two signals, inverted and not inverted, become

  the delayed signal present on a line 162. The expressions "delayed signal" and "modified phase signal" are used interchangeably for each other, and

  it should be noted that the phase change introduces

  picking is done by introducing a delay

in the signal.

  Further processing of the delayed modulated signal is performed exactly as for the first modulated signal of the embodiment of FIG. 1. The delayed modulated signal is applied to a second modulated signal.

  triggering device.164 which includes two

  controllers 166 and 168 controlled by the delayed modulated signal.

  The inverse and non-inverted analog current signal IA2 is applied to the switches 166 and 168. The signal

  modified-phase modulated alternately closes the

  166 and 168 to multiply the current and voltage signals with each other and to provide a second product signal at 170. The second product signal is then applied to the input of a VARS / Q converter 172 which is exactly the same as the converter 90 shown in FIG. 3. The VARS / Q converter 172 delivers first and second output signals according to FIG.

  the polarity of the energy running along the line 10, exactly

  In the same way as the converter 90. The first and second output signals of the converter 172 can alternate between two levels, at the converter clock intervals, in a manner proportional to the second product signal and the power value. relationship with the chosen phase (VARS or Q. 50 or 60 Hz) of the energy passing through the line 10. The processing of the first and second output signals of the VARS / Q converter 172 is exactly the same as that of the signals of output of the converter 90 shown in Figure 1, including the use of a meter suitable for delivering selected power values. A selector (not shown) may be provided to select either the VARS value or the Q value as the second output signal of the measurement system. The selector adjusts the shift register to produce the necessary voltage delay for generating the selected phase relationship

  and he simultaneously selects an appropriate display.

  The improved digital phase selection technique, shown by way of example in FIG. 8, is not limited to power measurement applications. It can be used in all signal multiplication applications, where the phase relationship between input signals can be adjusted to measure product values

in relation to the chosen phase.

  FIG. 9 represents a multiplier similar to that used in the power measurement system of FIG. 8. The same elements are designated by the same reference numerals. The signals IA1 and IA2 must be multiplied by each other and they are assumed to have periodic waveforms, not necessarily sinusoidal, having a predetermined phase relationship with each other. As in the power measurement system of FIG. 8, the multiplication is carried out by the technique

  known as time division multiplication

  or an interval, in which one of the signals IA2 is modulated and then used to trigger or invert the polarity of the other signal IA1 in order to obtain a signal produced. The signal IA2 is applied to a

  trigger device, in both forms

  not reversed. A conventional inverter 72 applies the signal to a switch 82. The non-inverted signal is applied to a switch 65. The modulated signal

  intended to control the switches 65 and 66 is

  to the triggering device by a line 34.

  The modulator 30 of FIG. 9 is of an embodiment and of an operation equivalent to those

  corresponding modulator indicated in 30 in the

  1 and 2. To establish a selected phase relationship between the signals IA1 and IA2, a digital offset device 160 is used which introduces a selected delay into the output signal of the modulator 30. The digital offset device 160 may take numerous forms, a simple version being illustrated by the element 198 of Figure 11. The operation of a shift register can be conveniently illustrated by series stages consisting of bistable circuits 200 to 204 connected so that the output Q d a bistable circuit

  is connected to the input D of the adjacent bistable circuit.

  A clock signal, applied to each of a circuit

  bistable by a line 196, causes the simultaneous

  born of all the floors. A digital pulse present on a line 53 leading to the shift register 198, which pulse is a progression from a low level to a high level or from a high level to a low level, is delayed by an interval of input clock by each bistable circuit as it passes through it. For example, if the signal on line 53 goes from a low level to a high level, the Q output of the bistable circuit 200 goes from one level to the next.

  down to the high level during the next clock pulse.

  Due to the clean switching delays, when the Q output of the bistable circuit 200 changes from the low level to the high level and the signal is applied to the D input of the bistable circuit 201, its Q output must wait for the clock pulse next to go high. In this way, digital signals can be conveniently delayed from any desired number of discrete intervals simply by introducing a sufficient number of delay stages into the shift register. Usually, the shift registers have a plurality of output lines 206 on which the signal can be extracted. The position of the spindle determines the overall delay introduced, depending on

the clock frequency.

  The digital device 160 of the multiplier device shown in FIG. 9 is assumed to be a conventional shift register such as the register

  shift 198 of FIG. 11. The multiplier device

  request the introduction of a chosen time setting

  in one of the signals to be multiplied by means of a

  digital offset to introduce a temporisa-

  which is a chosen number of discrete intervals.

  The shift register 198 is a digital device

  suitable offset for producing such a delay.

  Referring now to FIGS. 10A-10H, it is assumed that the signals IA1 and IA2 must be multiplied by each other and that a rear phase shift of 90 is introduced into the signal IA2. Fig. 10A shows an example of a first input signal IA1 (VL) and Fig. 01G shows an example of a second signal

  input IA2 to be multiplied one by the other.

  FIG. 10B shows the clock signal produced by the clock 56 and FIG. 10C shows the output signal of the integrator 42 that results from the input signal IA1. FIG. 10D shows the output signal resulting from the comparator 50. The output signal of the modulator 30 is shown in FIG. 10E and is applied to the line 53 of FIGS. 9 and 11. The clock signal 56 of the modulator is transmitted to the shift register

  198 in line 196. In the example given, the intervals

  the clock, shown in Figure lOB, have twenty-

  four times the frequency of the signal IA2. A quadrature A2 e quadrature back therefore requires a delay of six clock intervals. Assuming that pin 206 'of the register

  198 is the sixth pin, the signal IA2, moduli

  1 and delayed by 90, is thus delayed by a total of six clock intervals at the output of the clock 56. The output signal of the pin 206 'of the shift register 198 is illustrated in Fig. 10F. The signal

  delayed modulated shown in Figure 10F is a reproduc-

  exact modulation of the modulated signal of the output Q of the modulator 30, shown in FIG. 10E, moved to the right

six clock intervals.

  The multiplication of the signals is performed by applying the delayed modulated signal shown in FIG. 10F to the signal triggering device via line 34. The latter carries both the inverted and non-inverted forms of the delayed modulated signal. by applying the signal to a conventional digital inverter 161. The signal IA1 is the one shown in FIG. 1OG, both in inverted form and non-inverted form. The multiplication is effected by means of the switches 82 and 86 which are open and closed alternately with respect to each other, switching the point 88 of FIG. 9 between the non-inverted and inverted forms of the signal IA'1. The resulting signal is shown in Figure 10H. The signal of FIG. 10H may then be transmitted by a suitable low-pass filter 90 to provide a mean or continuous value, as shown at line 132 of FIG. 10H. Line 132 represents a product signal proportional to the product value of IA1 and IA2, with a rear phase shift of 90 introduced into IA2. If, for example, the signal A1 is proportional to the current carried by the power line and the signal IA2 is proportional to the voltage of the line, the signal produced represented by line 132 of FIG. 10H would be proportional.

at VARS.

  A particular advantage of using a delta-minusigma modulator such as modulator 30, together with the multiplier described, is

  that the modulated signal can only alternate at intervals

  the predetermined clock. Digital delay techniques necessarily divide an input signal into discrete units or intervals. The length or

  duration of these intervals is a matter of choice.

  Digital type signals carry information at the pulse edges as the signal goes from a low level to a high level, or vice versa. A shift register consisting of a series of bistable circuits "seeks" these pulse flanks at each

  once it is controlled by a clock pulse.

  The higher the clock frequency, the greater the frequency at which the sampling of the flanks of the pulses of the input signal is made. Since the delay introduced in a signal at each stage of a shift register depends on the clock frequency, the shift registers driven by the clock pulses at a high frequency require more stages, to produce a higher clock. given delay, that shift registers controlled at a low clock frequency. It is obvious that the control of a shift register at a low clock frequency means that the edges of the input signal pulses are less frequently sampled, and this may be a disadvantage if the position of the flanks of the pulses is not known, as is the case with conventional pulse width modulation signals. The

  modulator 30 delivers a signal having pulse flanks

  which appear only at predetermined clock intervals. By synchronizing the clock signals applied to the modulator and the shift register 198, the latter "searches" the pulse flanks only at the requested times. This means that the number

  of shift register stages necessary to introduce

  To obtain a given delay in a modulated signal may be less than would be necessary if the position of the flanks of the pulses was not precisely known. In fact, in the example given above, the shift register can be controlled at the same frequency as the modulator 30, without any loss of information whatsoever. It is therefore possible to use an inexpensive shift register with relatively few stages to introduce

  a given delay in a delta modulated signal

  less-sigma, whereas a much larger shift register would be needed to produce a delay

  comparable in a signal with flanks of impulse

  located at random points. Even if a record

  relatively high frequency shift was used to delay a randomly modulated signal of substantially lower frequency, some

  loss of information would appear in the absence of synchro-

  precise identification of impulse flanks with impulse

  clock positions of the shift register. No loss of information of this type occurs in the embodiment of the invention described above, since the modulator and the shift register are synchronized with each other and the pulse flanks are therefore not displaced. The clock intervals by which the shift register is controlled need not necessarily be exactly the same as the first clock intervals of the modulator 30. However, it is preferable that the clock of the shift register is synchronized to the modulator clock. . To avoid any loss of information, the shift register clock must operate at a frequency not less than that of the modulator, but it can operate at higher frequencies to achieve almost any desired delay. A convenient way to increase the clock frequency of the shift register, while maintaining synchronization with the first clock intervals of the modulator, is to use a frequency divider for the modulator clock. Although in the example described above, the desired delay in the modulated signal corresponds to an integer number of first clock intervals, it may not always be so. To achieve greater flexibility in the choice of a delay, it may be desirable to use either a second shift register or additional stages of a single shift register, which are controlled by clock pulses at the same time. a higher frequency and thus introduce incremental delays in the modulated signal. The states of the shift registers of element 212 of FIG. 11 illustrate a technique for increasing the selectivity of the digital time setting of the present invention. In this example, the delayed output signal of any selected shift register stage 198 is applied to a second group of shift register stages shown in FIG.

  11 in the form of a second shift register 212.

  Several bistable circuits 216 constitute the shift register 212. The delayed signal leaving the shift register 198 is applied to the input 214 of the shift register 212. A clock signal, advantageously having a frequency greater than that of the first clock 56, is applied via a line 208 to the bistable circuits forming the shift register 212. The higher clock frequency can conveniently be obtained by means of an oscillator 220 operating at a frequency higher than that of the first clock 56. By using a suitable frequency divider 210, clock signals of different frequencies can be applied to the various stages of the register

  as well as the modulator 30, as desired.

  The term "first clock intervals" as used herein generally refers to the signals

  clock coming out of the first clock 56 and the expression

  "second clock interval" refers to the signals output from the second clock 220. In addition, the stages of the shift register illustrated in FIG.

  be considered as constituting either the first regis-

  The shift register 198 and the second shift register 212 are a single shift register having a plurality of stages which are controlled by clock pulses at various selected frequencies. By using separate oscillators or a single oscillator associated with a frequency divider, the presence of different clock signals increases the flexibility of the techniques.

  digital offset used in the present invention.

  The delay of a signal by means of a shift register having a number of stages, all controlled by clock pulses of the same frequency, makes it possible to delay a signal by any number of intervals discreet, these intervals being able to reach

  the maximum number of stages of the shift register.

  By using additional stages controlled by different clock signals,

  additional chosen delay can be obtained.

  A signal may be transmitted by a first shift register and delayed by a number of first intervals and then transmitted by a second group of stages

  shift register and delayed by an additional

  silence of second intervals. Thus, a delay equal to virtually all full and fractional increments

  desired first intervals can be obtained.

  Similar flexibility can be achieved in

  signal delays by digital means through the use of

  a second clock that operates at the same frequency as the first clock but is shifted in time by a desired value. For example, if a signal is transmitted through a first register

  shift controlled by first intervals of hor-

  when it is transmitted to an additional stage controlled by the inverse of the clock signals having the first intervals, an additional delay equal to half of a first clock interval is introduced. Depending on the offset between the clock signals applied to the first and second groups of stages of the shift register, it is possible to introduce substantially

any delay value.

  An example of the operation of the modulator and the digital timer device of Figures 9 and 11 is given in Figures 12A-12D. Assuming a first clock signal applied by the clock 56 as shown in Fig. 122 and a second clock signal produced by the second clock 220 and the like shown in Fig. 10A, the modulated signal applied to the clock The input of the shift register is delayed as described below. In this example, the second clock 220 has a frequency equal to exactly twice that of the first clock 56. If, for example, a delay equal to two and a half times the first clock intervals is desired.

  in the modulated signal, the shift register is

  arranged so that the output pin 206 "is connected to the input 214 of the second shift register In this way, an input modulated signal arriving via the line 53 is transmitted by the first two stages 200 and 201 of the register and then arrives at the first stage of the second shift register 212, after which the signal exits through the pin 218. The signal is delayed by two first full clock intervals, and a second additional clock interval by such Assuming that a modulated signal, as shown in Fig. 12C, is applied to the input of the circuit described above, the output signal at pin 218 is that shown in Fig. 12D. 12D is exactly the same as the modulated signal shown in FIG. 12C, but delayed by two and a half times

the first interva.les clock.

  The technique of digital shift of the multi-

  pliant according to the invention has the advantage, clean

  digital electronic circuits, to be relatively

  free from drift and error. In addition, the time adjustment is performed independently of the adjusted signal. In other words, it does not depend on the frequency of the adjusted signal over time. The system shown in FIG. 9 allows a phase adjustment during the multiplication of two analog signals, without the use of RC networks and the signal disturbances associated therewith. If the delta-minus-sigma modulation is used in the multiplication, the size of the shift registers used need not necessarily be too large, while a high level of accuracy is however obtained. To obtain a high precision with the power measurement system according to the invention,

  over a wide dynamic range, it is important to eliminate

  the shifting errors of the active elements of this invention. Amplitude offset errors sufficient to affect the accuracy of the measurement often appear in operational amplifiers at good

  market. The expression "voltage offset" is global-

  defined as the voltage difference between two inputs of an active circuit element, such as a

  operational amplifier, when the output is zero.

  It denotes a discrepancy between the entries of the

  plifier, and the measuring system according to the invention comprises an offset compensation device

who corrects this discrepancy.

  Figure 13 shows a device

  Fitted offset compensation as applied to a single amplifier. The fundamental theory of the offset compensation device is to use a capacitor or other storage element which is connected to an input of the amplifier and then charged to a compensation voltage. It should be noted that other equivalent devices for storing and applying voltage to an amplifier input could be used in place of a capacitor. Operational amplifiers often have more than two inputs and sometimes have one or more inputs designed specifically for offset compensation purposes. The invention also works well to compensate for the offset of amplifiers having additional inputs. Any entrance designated to receive a voltage of

  offset in order to correct a voltage

  kills the input to which the capacitor is connected.

  The device further comprises means for charging the capacitor to an offset voltage which substantially cancels the effect of the voltage shift of another input of the amplifier. For the sake of simplicity, only the amplifier 70 (FIG. 1) is shown in FIG. 13, although the

  offset compensation according to the invention can corri-

  sequentially multi amplifiers, such as

described below.

  The amplifier offset compensation device, as applied to the amplifier 70, includes an offset storage element, such as a capacitor C1, connected to a first selected input 181 of the amplifier. A cancellation circuit 128, connected by switches to both the offset storage element and the second selected input 183 of the amplifier 70, is also

  planned. The cancellation circuit 182 includes an amplification

  Loader 184 is connected to the second input of amplifier 70 via a switch A1. The cancellation circuit further comprises a temporary storage element, namely a capacitor

  186, and a series of switches B, D and E which connects

  Attempt capacitor 186 to charge amplifier 184, as described below. Additional switches G1 and H1 connect the charge amplifier 184 to a charging circuit which regulates the stored voltage.

on the capacitor C1.

  The signal IA2 of the line current is applied to the inverting input 183 of the amplifier 70, which is ideally a virtual ground. Any voltage shift in the amplifier 70 initially appears as a voltage at the inverting input 183. When the capacitor C1 is charged, the voltage applied to the inverting input 183 decreases to

  what a virtual land condition is reached. The difference between the compensation voltage V

  plotted at C1 and the actual voltage offset of the amplifier

  70 is called the Verr error

  The purpose of the offset compensation device according to the invention is to reduce the error voltage Vr err to a minimum. The offset compensation device comprises control means intended to assume

  the functions indicated in box 190. Essential-

  The controller operates the switches A1, B, D, E, G1, and H1 to produce a series of transfer and load periods sequentially. During an initial transfer period, the switches A1, B and D are closed and the switches E, G1 and Hil are open. Al switch being closed, the

  Verr voltage is applied to the direct input of the amplifier.

  charging indicator 184 which is mounted as a unity gain amplifier. The switch B, which is closed during the transfer periods, establishes a feedback connection between the output 192 of the charge amplifier 184 and the direct input 226. A first terminal 228 of the temporary storage capacitor 186 is also connected. at the inverting input 226. The switch D, when closed, connects a second terminal 230 of the capacitor 186 to ground. Thus, during the transfer period, the voltage Verr appears at the output 192 of the amplifier and is stored on the capacitor 186 for temporary storage, as well as the voltage offset of the charge amplifier 184 (VoffstAmp 184). following a charging period, the controller 190 opens the switches Ai, B and D and closes the switches E, G1 and H1. This serves to disconnect the second terminal 230 of the capacitor 186 from the ground and to connect it to the output 192 of

  the amplifier, in a second feedback loop.

  The result is that a -Verr voltage appears at the output 192 of the amplifier. Internal offset

  of the charge amplifier 184 (Voffst Amp 184) is

  offset by the equal and opposite value of the -Voffst Am 184 component that is applied at output 192 and

  from the capacitor 186. The closure of the

  G1 and the opening of the switch Ai during the charging period also cause the application of the voltage Vcomp, present across the capacitor Cl shift storage, to the direct input of

  the charge amplifier 184. The voltage -V rr being pre-

  feels at exit 192 of. the charge amplifier and the voltage Vmp being applied to its input (during the charging period), a current -Ier is established through the impedance 224 and the switch H1 which regulates the voltage Vcomp in the direction necessary to comp reduce the Verr voltage during the next err transfer period. Figure 14 illustrates the operation

  of the offset compensation device in conditions of

  start-up procedures. Assuming that the voltage Voffst-Amp 70 represents the voltage offset between the inputs of the amplifier 70 and that the load applied to the capacitor C1 (Vcomp) is initially zero, the voltage Verr, during the initial transfer period, is equal At Voffst Amp 70 During the next charging period, a voltage Verr appears at the output err 192 of the amplifier. A current -Ierr is then err applied to the capacitor 186, increasing the value of Vcomp. The voltage Vcomp applied to the capacitor C1 is intended to substantially reduce the offset error of the amplifier 70 until the next transfer period. The values of resistor 224 and capacitor C are chosen to produce an I-I current that does not excessively change the voltage applied to capacitor C1 during any single charge period. Capacitor C1 therefore does not charge at the full offset voltage during

  the very first transfer and charge cycles.

  When Vcomp approaches Voffst-Amp 70), the Verr voltage decreases more and more. Finally, Verr approaches a stable minimum value sufficient to compensate for the leakage currents and other transient signals present in the circuit. At this point, errors in

  offset are virtually eliminated.

  Subsequent transfer and charge periods can either immediately follow the previous transfer and charge periods, or be delayed by a delay. In the preferred embodiment, where other amplifiers are offset compensated by the same cancellation circuit 182, the transfer and charge states associated with any amplifiers are spaced apart by predetermined time intervals. With reference to FIG. 14, the next transfer period has a smaller voltage Verr, as indicated by err 222. As before, Ver is first stored on a capacitor 186 and then, during the period of

  next charge, it appears at output 192 of the amplifier

  load indicator a voltage -V err. During this charging period, the -Ierr current is added to the load of capacitor C1, which further reduces the Verr amplitude during the next transfer period. During the following cycles, the voltage Vcomp applied to the capacitor C1 approaches the actual voltage offset of the amplifier 70, reducing the

Voltage Lock virtually to zero.

  The offset compensation device described above with respect to the amplifier 70 can similarly compensate for the offset of

  several amplifying elements. Figure 15 shows

  This is the preferred embodiment of the offset compensation device used to compensate for the offset of five different amplifiers. The five amplifiers whose offset must be compensated by the measuring system device are as follows:

  the gain amplifier 70 of the current signal, the amplifier

  current signal inversion flag 74, the amplifier

  integrator 46 of the first modulator, the amplification

  converter 108 of the output converter integration

  of the active power, and the amplifier 180 of integra-

  output converter VARS / Q. Each of the amplifiers is analogous to the gain amplifier 70 described with reference to FIG. 13, in that all of these amplifiers have virtually ground-inverted inputs to which a signal is applied. Each of these amplifiers comprises respective elements of offset storage, namely capacitors C1 to C5. The direct inputs of the amplifiers are connected to the amplifier

* 184 charging circuit 182 canceling through

  respective pairs of switches A1 to A5, as shown in FIG. 15. Pairs of switches equivalent to G1 and H1 of FIG. 13, namely G1 to G5 and H1 to H5, connect the charge amplifier 184 to the capacitors of FIG. respective offset storage

amplifiers.

  A unique 182 cancellation circuit stores

  the error voltage and charge the storage capacitor

  offset of each amplifier using the sequence described below. For clarity, the control circuit of the various switches shown in Fig. 15 is removed. A conventional controller of any suitable type may be used to control the switches in accordance with the timing diagram illustrated in FIG. 16. The controller first closes the switches A 1, B and D during an initial transfer period for the amplifier 70, then opens the switches Ai, B and D and closes the switches E, G1 and H1 during a charging period. The controller then establishes additional successive periods

  transfer and charge for each of the other amplifi-

  which must be offset. After the charge period of the amplifier 70, the transfer period of the amplifier 74 begins, the controller closing the switches A2, D and B and then opening these switches and closing the switches E, G2 and H2 during the charging period

  next. In the case of the amplifier 46, the switches

  A3, B and D are closed during the transfer period and the switches E, G3 and H3 are closed during the charging period. For the amplifier 108, the switches A4, B and D are closed during the transfer period and the switches E, G4 and H4 are closed during the charging period. Finally, for the amplifier 180, the switches A5, B and D are closed during the transfer period and the switches E, G5 and H5 are closed during the period

charge.

  After a transfer and charging period has been completed for an amplifier, all switches associated with this amplifier, namely switches A, G and H, are left in the open position. The charge stored on the respective charge storage capacitors remains until the control sequence produces a new period.

  charge associated with this capacitor. Although some

  As no load reduction occurs, errors due to voltage compensation are significantly reduced for each of the amplifiers. The frequency with which the control opens and closes the switches associated with the offset compensation device

  is a question of choice, but it can be sensitive-

  less than the frequency of the associated clocks

to the measuring system.

  The offset compensation device described may be used to correct offset errors in any number of amplifier elements associated with a measurement system. A single cancellation circuit such as circuit 182 may be connected sequentially to N amplifying elements and their associated storage elements during

  a sequence of transfer and load periods.

  Such an offset compensation device is economically

  It is ideally suited to the use of CMOS integrated circuits where offset errors can be problematic. Although described in its application to the measuring system according to the invention, the offset compensation device can be applied to other types of power measuring circuits using operational amplifiers. Such a measurement circuit may comprise, for example, any suitable means for multiplying the analog signals representing current and voltage, as well as any suitable converter or filter circuit for producing an output signal from the product signal. Assuming that the measurement system uses up to N amplifier elements in its various components, the offset compensation device according to the invention can substantially eliminate the offset errors of the

as described below.

  The N amplifier elements each comprise several inputs. A first selected input of any of these amplifiers is the input for receiving a compensation voltage for

  the correction of the voltage offset. N elements of emma-

  Offset gas, such as capacitors, are also provided. One of the N shift storage elements is connected to the first selected input of each of the N amplifier elements. The offset storage elements receive compensation voltages that substantially reduce the offset error to another input of the amplifier element to which it is applied, the other input being referred to as the second input selected. Any difference between the compensation voltage applied to the offset storage element and the voltage offset of the amplifier element is an error voltage that occurs at the second selected input of the amplifier element. A cancellation circuit such as circuit 182 is also provided for the power measurement system. The cancellation circuit can be successively connected to each of the N amplifier elements and to the offset storage element which is

  associated. In the following description, the amplifying element

  which the cancellation circuit is connected to, including its associated storage element, is called the selected amplifier element. In the same way

  that in the system described above, the cancellation circuit

  The section is first connected to the second input of the selected amplifier element during an intermittent transfer period. The cancellation circuit is then connected to the offset storage element associated with the selected amplifier element during the intermittent charge period following the transfer period. A controller then connects the cancellation circuit sequentially to the remaining N amplifier elements to establish transfer and charge periods for each of these amplifier elements. The sequence is continuously repeated so that all the amplifier elements are offset compensated and the offset errors of the measurement system are substantially

eliminated.

  Thanks to the presence of the compensation device

  In the above-described shift arrangement, the measuring system according to the invention measures the power with a

  high degree of accuracy over a wide dynamic range.

  The need to use error-free or calibrated amplifiers of a relatively high cost is eliminated,

  which makes the measurement system relatively cheap.

  The system produces continuous parallel displays of power, both in watts and in VARS or Q. Since the output signal of the modulator 30 is precisely controlled at the first clock intervals, it is possible to manipulate the signal using digital logic. A shift register

  can be conveniently used to introduce the temporality

  necessary to produce an appropriate phase shift

  Required for VARS and Q measurements. By simply selecting the appropriate stage in the shift register, the delay applied to the modulated signal can be adjusted to produce the desired output signal (VARS or Q. 50 or 60 Hz). The invention thus avoids the devices

  analogous phase shifting for the production of

  the desired voltage delay. Since the output signal of the modulator can be applied

  to both a power converter and a conver-

  VARS / Q weaver, simultaneous readings can be performed using a single modulator. The system also produces digital output signals for each polarity of energy traveling along the line. Maximum information is therefore obtained with a degree

  high precision, in an efficient and economical way.

  FIG. 17 represents a part of another variant of the modulator which is substantially more

  simple that the embodiment of the modulator represents

  30 in Figure 2. In this form of realization,

  tion, a capacitor 44 is mounted between the node 36

  of summation and mass. Capacitor 34 serves as the

  modulation scratcher. The inversion entry of a comparator

  The driver 50 is also connected to the node 36 while the direct input is connected to ground. The comparator

  50 produces a control signal in response to variances

  voltage applied to the node 36 which is connected to a bistable circuit 52. The latter is used to control two switches which apply a signal

  at the node 36 as described below.

  Figures 18A to 18E illustrate several

  signals produced by the modulator of Figure 17.

  An input signal VL is shown in Fig. 18A. It is obvious that in power measurement applications on AC currents the voltage VL is sinusoidal. Initially, the switch 58 is supposed to be closed, and a reference current

  negative is applied to the summation node 36 by the

  of resistance 40. The values of V1-

  and resistor 40 are selected to produce an IF current which is large relative to the input signal IA1. The current Idiff therefore has a net worth

  negative, the current from the capacitor 44.

  Therefore, the integrated difference voltage signal

  initially decreases, as shown in Figure 18C.

  Clock 56 produces a signal as shown in FIG. 18B. The bistable circuit 52 is controlled by the leading edge of each progressively increasing clock pulse. At the clock pulse a, the difference integrated signal of FIG. 18C has not yet passed through the threshold of the comparator 50, so that the Q output remains low and the Q output high and the difference signal continues its decline by integration. Since the difference signal is applied to the Enversion input. of the comparator

  50, when passing through the threshold, the exit of the

  from low to high. The control signal shown in Fig. 18D represents the output signal of the comparator 50. Therefore, at the clock pulse b, the bistable circuit 52 changes state and the output Q goes from the low level to the high level. When the Q output goes high, the Q output goes low and the switch 60 is closed while the switch 58 opens. A positive reference signal is then applied to the summing node 36, causing the integrated Idiff signal to grow until the next clock pulse c. Between the clock pulses b and c, the integrated difference signal again passes through the threshold level of the comparator 50, causing the first control signal to go low. The Q output then goes low to the next clock pulse, again negating the reference signal applied to the summing node 36. As the voltage VL increases, the slope of the difference signal changes and its value decreases until the signal again passes through the threshold level. The Q output remains low until

  detecting a change in the first control signal

  from the clock pulse f. The Q output then goes high, again passing the reference signal from a negative value to a positive value. The circuit and method described above

  operate in the manner of a delta-converter

  less-sigma in which only the difference between

  Input and reference signals are integrated and measured.

  The circuit always maintains the integrated difference signal around the threshold level of the comparator 50. The Q output of the bistable circuit 52 is selected as the first output signal having a mean level or an average amplitude, over time, which

  is proportional to the amplitude of VL.

  FIG. 19 represents a modulator circuit analogous to that of FIG. 17, which comprises a

  variant of the offset compensation device.

  In this embodiment, the comparator 50, which is an operational amplifier, has a

  compensation device for eliminating

  any offset error resulting from a voltage shift existing between the inputs 306 and 308 of the amplifier. As previously described, a voltage offset is generally defined as the requested voltage between the inputs of an amplifier to obtain zero output. Ideally, an offset

  voltage is zero, but in most amplifiers

  used in practice, an offset of unknown value is usually present. With the present invention, a first storage element, such as a capacitor 302, is connected to one of the inputs of the amplifier, and an offset voltage

  substantially equal to the voltage offset of the ampli-

  It is stored on the storage element to compensate for the voltage shift. In the example shown in Fig. 19, the capacitor 302 is placed on the electrical path between the summing node 36 and the inverting input 306 of the amplifier. It should be noted that the capacitor 302, likewise

  that the capacitor 44 and the other storage elements

  used in the embodiments described hereinafter, represents a type of storage element that can be used, and that other types of circuit elements, such as registers with converters.

  digital / analogue and others, could be used

  for the various storage elements of the present invention. The offset compensation device also comprises a feedback loop 300 which is connected intermittently, on either side of the amplifier 50, between the inverting input 306 and the output of the amplifier by the amplifier. through a switch C. When the switch is closed, the voltage offset appears at a low impedance at the input 306. To store the voltage produced by the feedback loop on the capacitor 302, switches A and B are provided to disconnect one end of the capacitor from the summation node 36

  and to connect it to the common ground 305.

  The means for controlling the offset compensation device shown in Fig. 19 includes a clock 56 and Fig. 20 illustrates the control function. The bistable circuit 52 is controlled by the leading edge of each clock period, as indicated by arrows 312. Each pulse

  progressively increasing represents a pulse of hor-

  box. Just as the clock pulse starts to go from the low level to the high level, the switches B and C are in the off state and the switch A is in the state in, which means that the feedback loop bypassing amplifier 50 is disconnected and that

  the capacitor 302 is connected to the summing node 36.

  As soon as the clock pulse starts, switches B and C go to state en and switch A goes off, connecting the feedback loop around

  of the amplifier and connecting a terminal of the condensa-

  302 to ground. During this period, called the cancellation period, the voltage offset + Vfft offst the amplifier 50 appears at the input 306. Binding given that the capacitor 302 is connected between the input 306 and the ground, the voltage + Voffst is stored on the capacitor. During the second half of each clock period, called the measurement period, switches B and C are off again and switch A is in. With the direct input 308 grounded, the error at the inverting input 306 is the

  negative value of the voltage offset -Voffst. By con-

  the signal being compared with the threshold level by the comparator 50, when A is closed and B and C are open, the voltage at the summing node 36 is constituted by the integrated difference signal,

  plus voltage + Voffst plus voltage -Voffst. The deca-

  The voltage of the comparator 50 is therefore canceled and the error, which it would otherwise introduce into the measurement.

  threshold, is essentially eliminated.

  Another embodiment of a modula-

  using an offset compensation device

  is shown in Figure 21. In this form of embodiment,

  tion, the measuring device 298 comprises first

  and second amplifier elements 328 and 336, respectively

  which serve as comparators and which are alternately connected between the summation node 36 and the

  bistable circuit 52. A first amplifier 328 comprises

  carries a switchable 324 feedback loop connecting

  its output 330 to its input 326 inverting through

  of a D switch. A first storage element

  The capacitor 316 is mounted in the electrical path between the summing node 36 and the inverting input 320 via a switch E. A path is established between a terminal 318 of the capacitor 316 and the mass, via a switch F. The second element

  amplifier 336 also includes a switching loop

  Reactor 332 mounted between output 338 and the

  334 to inversion via a switch G, and a storage element such as a capacitor 320 is placed on the electrical path between the input

  334 inversion and the summation node 36, through

  a switch H. A path is established between

  a terminal 322 of the capacitor 320 and the mass by the in-

  intermediate of a switch J. The embodiment of FIG.

  is designed to form two parallel comparator circuits

  Offset Compensation Models for Measuring & Measuring

  the integrated difference signal at the summing node 36.

  When the switches E and Kv are closed, the first amplifier element 328 applies the first control signal to the bistable circuit 52 and when the switches H and L are closed, the second amplifier element 336 applies the first control signal to the bistable circuit 52. By closing the switches E, G, J and K and opening the switches D, F, H and L, the first amplifier element 328 is placed in measurement mode applying the control signal to the bistable circuit 52, and the second amplifier 336 in cancellation mode in which the voltage shift of the amplifier element 336 is stored on the capacitor 320. The storage of the voltage Voffst on the capacitors 316 and 320 is realized

  in exactly the same way as with the amplifying element

  50 and the capacitor 302 of the embodiment

  19. Inverting all the switches, that is by closing the switches D, F, H and L and opening the switches E, G, J and K, is

  amplifier 328 in cancellation mode and the amplification

  336 in measurement mode in which the integrated difference signal at the summation node 36 is applied.

  at the inverting input 334 via the capacitor

  320, compensating for the voltage shift of the amplifier

  336 and applying a first command signal

  error free at the input D of the bistable circuit 52.

  An advantage of the embodiment shown in Fig. 21 with respect to that of Fig. 19 is that an offset compensation amplifier

  is constantly available in its measurement mode.

  In addition, the switching between the measurement and cancellation modes of the embodiment of FIG.

  19 appears at the frequency of the clock 56. If the frequency

  the sampling rate, as determined by the clock frequency 56, is sufficiently high, the comparator amplifier elements are unable to stabilize after each cancellation period, and errors are introduced. The embodiment of Fig. 21, which uses conventional control logic to operate the switches D, E, F, G, H, J and L, represented by the element 340, can be controlled at a frequency different from that of the clock 56. A conventional frequency divider

  can be used to reduce the frequency of

order, for example.

  To ensure that a suitable time is

  intended for amplifiers in the form of

  FIG. 21 to stabilize after each cancellation period, the control logic 340, which serves as a control means for the operation of the switches D, E, F, G, H, J, K and L. , extends the measurement period of each amplifier element to allow time for stabilization. Figure 22 is a timing chart showing operations

  switches D, E, F, G, H, J, K and L under the

  The switches K and L, which connect the outputs of the first and second amplifier elements, respectively, to the bistable circuit 52, are controlled in phase shift with respect to one another. The switch K is closed half the time and open the other half of the time, and the switch L is open while the switch K is closed, and vice versa. In addition to controlling the switches that connect the amplifiers to the flip-flop 52, the control logic 340 also controls the switches that determine the cancellation periods.

  and measuring amplifiers 328 and 336. The switches

  D, E and F are used to connect a feedback loop.

  surrounding the amplifier 328 and to connect a terminal 318 of the capacitor 316 to the ground, in exactly the same manner as in the embodiment of FIG. 19. The switches G, H and J assume the same function for the amplifier 306. As can be seen in FIG. 22, the cancellation and measurement periods of each of the amplifying elements do not have the same duration. The cancellation period of the first amplifier 328, for example, begins when

  the switch K opens and ends before the

  controller K closes again. Similarly, the cancellation period of the second amplifier 336 starts when

  the switch L opens and ends before the

  driver L closes again. Consequently, the cancellation period

  Each amplifier is shorter than the measurement period, the difference corresponding to a predetermined interval. This is so to allow amplifiers time to stabilize before

  they are connected to the bistable circuit 52.

  It should be noted that, in addition to allowing additional time for amplifier stabilization prior to connecting the first or second amplifier to the bistable circuit, the control logic 340 operates, by its nature, more slowly than the As can be seen in FIG. 22, the clock signal NRL, which is not shown in FIG.

  scale, works at a substantially higher frequency

  greater than that of any of the switches of FIG. 21. The control logic 340 advantageously comprises a frequency divider provided for this purpose. The embodiment shown in the figure

  21 can therefore use a relative frequency clock-

  high, for example 10 kHz, to produce a sample of

  frequent readout and relatively high resolution, while the cancellation and offset compensation of the amplifier elements are performed at a low enough frequency to minimize errors due to the slow response of the amplifiers. In Figure 22, the cancellation periods are indicated

  in PA and measurement periods in PM.

  The method according to the invention implemented by the embodiment of FIG. 21 comprises an additional step in the measuring operation for establishing a switching between the first and second

  amplifier elements 328 and 336, respectively.

  The compensation step consists of taking a measurement with the first amplifier element and canceling the second amplifier element, then measuring with the second amplifier element and canceling the first amplifier element in a continuous cycle so that at least one of the offset compensating amplifiers is constantly connected to the summing node. In the preferred form of the method of the invention, the cancellation periods and the measurement periods are different and the prefixes are slower than the clock intervals. In addition, the cancellation periods are shorter than the measurement periods for each amplifier element,

  according to the diagra-xe of the times of Figure 22.

  The measurement period of one amplifier element begins before the end of the measurement period of the other amplifier element so that any errors due to the slowness of the comparator response of the first amplifier element, when it is initially switched

  from a one-way cancellation, be eliminated.

  The operation of the embodiment of Fig. 21 gives the results illustrated in Figs. 18A to 18E. Assuming that the voltage VL is as shown in Fig. 18A, the integrated difference signal appearing at the summing node 36 is as shown in Figure 18C. The first control signal of Figure 18D and I signal the output

  Q of Figure 18E are not affected by the function

  intermittently and the cyclical periods of cancellation

  The embodiment of FIG. 21 provides greater accuracy at higher clock rates,

  but it is also, from the point of view

  identical to the embodiment of FIG. 19. The modulator 30 used in the measuring system of FIG. 1 can also be used

  in other applications it is necessary to

  to create modulated signals that are representative of

the polarity of the input signal.

  Referring now to Fig. 23, a variant of the modulator that produces

  such output signals. The input signal IA1 is

  plicated to the summing node 36 via the resistor 38. One of the two reference signals, which preferably have the same amplitude and which are of opposite polarity, is also applied to the node.

  summation via the resistor 40.

  The reference voltages V1- and Vi + are applied

  summation node via two commu-

  58 and 60, respectively, which are controlled by the output signal of the modulator. The instantaneous differences between the IA1 input current and the current

  IF reaction at node 36 are applied to an integration

  which produces a rising or falling ramp voltage. The integrated signal is then compared to a threshold level by a comparator 50 which outputs a control signal indicating whether the integrator output signal is above or below the threshold level. The output signal of the comparator 50 is

  applied to a bistable circuit such as a flip-flop 52.

  The bistable circuit changes state only at predetermined clock intervals, as determined by the clock 56. When the integrated signal passes through the threshold level of the comparator 50, the

  bistable circuit outputs 52 change state to impulse

  next clock. The Q output of the bistable circuit 52, which carries the first modulated signal of the present invention, controls the switch 60 which connects the reference positive voltage Vl + to the summing node 36. The Q. output, which is always the opposite of the Q output, operates the switch 58, connecting the negative reference voltage V1- to the summing node 36. The switches 58 and 60 are always alternately actuated, which means that one or other of the reference signals is always applied

at the summing node 36.

  The Q output of the bistable circuit 52 is connected to the input D of a second bistable circuit 53 and these two circuits receive signals of the same clock 56. Given the delay of tripping, changes affecting the Q output of the bistable circuit 53 always follow those affecting the Q output of the bistable circuit 52, delayed by one clock pulse. An AND gate 350 is also intended to receive the signals of the Q outputs of the two bistable circuits.

  and 53, as well as a signal from clock 56.

  The AND gate is intended to deliver a first digital signal which is proportional to the amplitude of a

polarity of the input signal.

  Figures 24A-24J illustrate the function

  elements of the circuit described above. Assuming, by way of example, that the waveform of the voltage at node 32, applied to this variation of the modulator, is as illustrated in FIG. 24A, the signal is converted into a first modulated signal at the output Q of the bistable circuit 52, as described above. The Q output of the bistable circuit 52 is assumed to give the waveform shown in Fig. 24D. The output of flip-flop 56 is represented by the waveform of FIG. 24B. The output of the second bistable circuit 53 is referred to as the "delayed Q output" and is illustrated by the waveform of FIG. 24E. The delayed Q output is substantially equal to

  exit Q. but delayed, in time, by an interval

  the clock. The invention requires combining the delayed Q Q outputs and a clock signal with a

AND gate 350 (see Figure 23).

  Although this is not necessary in these idealized circuits in which component delays are non-existent, in the case of components used in practice, it is preferable to incorporate

  an inverter 57 between the clock 56 and the AND gate 350.

  Inverter 57 reverses the clock signal to provide an inverted clock signal indicated in FIG. 24C. The reason for applying an inverted clock signal to the AND gate is that propagation delays in the bistable circuits 52 and 53 tend to give their output signals a slight delay with respect to the clock output signal. 56 and thus briefly and simultaneously give the three signals "high" states at the wrong time. The absence of inversion of the clock signal causes the appearance of a foreign tip at the output of the AND gate 350, which represents a clock pulse. This is the reason why

  the inverter 57 is incorporated in the embodiment of

  Figure 23. The resulting waveform produced

  by the AND gate 350 is shown in Fig. 24F.

  The waveform of Figure 24F is essentially

  Usually a numerical representation of the value by which the time during which the Q output is high exceeds the time during which the Q output is low. In the example of FIG. 24F, the waveform contains only two pulses generated one after the other and appearing on the

  right side of the illustrated waveform. These two impulses

  are approximately coincident with the zone in which the input indicated in FIG. 24A is the most negative. Preferably, the frequency of the clock significantly exceeds the variations of the analog signal

  to obtain higher resolutions

  than those shown in Figures 24A-24J.

  However, the operating principle is exactly the same. Essentially, by combining a delayed modulated signal with the original modulated signal, using an AND gate, an output signal is obtained that goes high only when the Q output remains

  high for at least two successive clock pulses

  sive. The clock signal sends at the output of the gate AND a pulse train in which the pulses have intervals which are not inferior.

  at the intervals of the pulses of the clock signal.

  In the example just described, the AND gate delivers pulses only when all the signals it receives are high. If the Q output is low for two or more successive clock pulses, this has no effect on the output signal of the AND gate 350 because only the high level input signals are measured. Therefore, the output of the AND gate is a representation of

  the amplitude of a single polarity of the input signal.

  The output is actually a rectified signal on half a

  period, represented in numerical form.

  To produce a digital output signal proportional to the other polarity Y of the input waveform, the variant of the modulator according to the invention uses the signals of the outputs Q of the bistable outputs 52 and 53 as first and second inverse modulated signals. , respectively. Assuming the same input signals and clock signals as those shown in Figs. 24A-24J, the output signal Q has the waveform shown in Fig. 24G. The bistable circuit 53 produces a delayed Q signal as shown in FIG. 24H. Both signals are applied to a second AND gate 352 (Fig. 23) together with the inverted clock signal shown in Fig. 24C. The output signal of the second AND gate 352 has the waveform of Fig. 24I and is called the second digital signal. The second AND gate is for providing a second digital signal which contains pulses in proportion to the time interval during which a level of the first modulated signal reverses the other level. When the three inputs of the AND gate are high, pulses are produced at intervals which are not smaller than the intervals of the clock 120. In the example described, the waveform of FIG. 24I represents the component of positive polarity of the input signal. As can be seen, the pulse position corresponds approximately to the areas where the input signal shown in Fig. 24A is high. The waveform of Figure 24I constitutes

  a numerical representation of the amplitude of

  positive half-periods of the input signal.

  Returning to FIG. 23, the present invention may further be used to produce a digital signal proportional to the amplitude of the complete waveform of the input signal. This is achieved by applying the first digital signal output from the AND gate 350 and the second digital signal output from the AND gate 352 to an OR gate 351 which serves as a trigger element for combining the digital signals and to provide a signal numerical summation shown in Figure 24J. The waveform of Figure 24J is proportional to the amplitude of the complete input signal, including both polarities, which is referred to herein as "absolute amplitude." The outputs of the AND gates 350 and 352 are connected to the count inputs. and counting up / down counter 354, so that the numbers of positive and negative pulses can be compared on

any time interval chosen.

  It goes without saying that many modifications can be made to the measuring system described

  and shown without departing from the scope of the invention.

Claims (8)

  A system for producing digital signals proportional to selected parameters of an input signal which has been converted into a first modulated signal varying between two levels, in a manner proportional to the amplitude and to the polarity of the input signal, said system being characterized in that   comprises means (56) for generating pulses   clock positions at predetermined clock intervals.   a delay means (59) for receiving the first modulated signal and for outputting a second modulated signal substantially equal to the first modulated and delayed signal of a clock interval and means (52).   intended to deliver a first digital signal containing   output pulses are not less than said clock intervals when the first and second modulated signals are simultaneously at predetermined levels so that the   first digital signal carries amplification information   study and polarity regarding the input signal.   System according to claim 1, characterized in that the first modulated signal can alternate between first and second levels at said clock intervals, in a manner producing a mean level, over any sufficient interval, proportional to said input signal. said means for providing a first digital signal outputting pulses at intervals which are not less than the clock intervals when the first and second modulated signals are simultaneously at said first level, so that the first digital signal contains pulses in a prcportion which depends on the time interval during which the first level of said modulated signal exceeds the second level.   3. System according to claim 2, characterized in that it comprises inversion means for producing a first inverted modulated signal which is the inverse of the first modulated signal, and a second inverted modulated signal which is the inverse of second modulated signal, and means for delivering a second   digital signal containing impulses at inter-   valles which are not less than the clock intervals when the first and second inverted modulated signals are simultaneously at predetermined levels, so that said second digital signal contains pulses the proportion of which corresponds to the time interval during which a level of said inverted modulated signal exceeds the other level.   4. System according to claim 3, characterized in that said input signal is converted into a modulator (30 ') which comprises a first bistable circuit (52) having outputs Q and Q, the first modulated signal appearing at the output Q of the bistable circuit, the inverting means of using the Q output of the first bistable circuit to produce   said inverse modulated signal, the delay means comprising   a second bistable circuit (59) having outputs Q and Q and receiving said first modulated signal at its output Q which reproduces said first modulated signal with a delay of a clock interval, said inverting means comprising the use of said Q output of the second bistable circuit to produce said second inverse modulated signal.   5. System according to claim 3, characterized in that the time interval during which a level of said first modulated signal exceeds the other level for any sufficient duration is proportional to the amplitude of a polarity of the input signal, the system further comprising tripping means (350,352,351) for receiving said first and second digital signals and providing a summation digital signal which corresponds to the sum of the first and second digital signals and which is   proportional to the absolute amplitude of the input signal.   6. System according to claim 1, characterized in that the delay means comprise a bistable circuit (59) which receives at an input said first modulated signal, and which also receives the clock pulses, and which produces an output signal. constituting said second modulated signal and following and reproducing all variations of the first modulated signal, delayed by a clock interval.   A system for producing digital signals proportional to selected output parameters of an input signal, characterized in that   comprises means (56) for generating pulses   clock positions at predetermined clock intervals.   a modulator for converting the signal of   In a first modulated signal, this modulator comprises   a first bistable circuit (52) which delivers, at an output Q, said first modulated signal which can alternate with said clock pulses between first and second levels in a manner producing a mean level over any sufficient space, proportional to said an input signal, a second bistable circuit (53) which receives said first modulated signal and the clock pulses and which outputs a second modulated signal delayed by a clock interval, and means (350) for outputting a first digital signal containing output pulses, at intervals not lower than said predetermined intervals, when   said first and second modulated signals are simultaneously   to the first level, so that said first digital signal carries the pulses in proportion to the duration during which the first level of the modulated signal exceeds the second level, and also in proportion to   the amplitude of a first polarity of the input signal.   8. System according to claim 7, characterized in that said first and second bistable circuits each comprise an additional Q output, the Q output of the first bistable circuit producing a first inverted modulated signal which is the inverse of the first modulated signal, and said Q output of the second bistable circuit producing a second inverted modulated signal which is the inverse of the second modulated signal, means (352) being for outputting a second digital signal containing the output pulses to   intervals not inferior to those   predetermined valleys when the first and second inverted modulated signals are simultaneously with said first level, so that said second digital signal carries pulses in proportion to the time during which the   second level of the first modulated signal exceeds the first   first level, and also in proportion to the amplitude   the second polarity of the input signal.