CH672847A5 - - Google Patents

Description

DESCRIPTION

Technical field

The invention relates to a method for measuring the electrical power carried on a line, in which delta-minus-sigma modulation and an offset compensation device are used, a measuring device for carrying out the method, and a modulator and a multiplier arrangement for the measuring device.

State of the art

Measuring devices that accurately measure the electrical power flowing in a line are an essential part of an electrical supply system. The most common type of meter used by the utility today is a rotating disk meter that is accurate and reliable in its basic form, but provides the company with limited information regarding the use of power. In addition to total kilowatt-hour power consumption, utilities often need to measure other parameters to better determine the cost of supplying certain consumers. For example, it is considerably more complex to supply a consumer with high reactive power because a phase mismatch of current and voltage is induced here, which is referred to as the power factor. In order to determine the power factor, certain standardized power measurements have been developed in electricity supply companies. Two widely used measurements are reactive power (VARS for reactive volt amperes) and Q. In both cases, power measurements are proportional to the product of power current and voltage, with the voltage phase for reactive power or VARS the current around 90 ° lags, while with measure Q this lag is 60 °. Together with the total power consumption, reactive power and Q allow the company to measure the power factor for which an additional charge is usually required. Another factor of interest to utilities is the polarity or direction of the power flow, since in some use cases both power is consumed and power is fed back into the grid. In the electricity industry there is a constant need for measuring systems with which it is possible to measure such parameters as reactive power, Q and polarity in addition to the total power consumption.

Various electronic measuring systems have been designed or proposed to replace the rotating disk measuring device. Examples of known electronic measuring systems are those shown in the following patents: US 3 875 508, US 3 955 138 and US 4 182 983. All of these systems use modulators which provide a pulse-width modulated signal in proportion to either current or voltage, and then one Use time division or mark space multiplication, gating the polarity of the other signal or vice versa, to obtain a product signal. The product signal pulses obtained vary in amplitude with respect to one analog value (current or voltage) and vary in width with reference to the other analog value. A low pass filter extracts the DC component of the product signal, which is proportional to the power consumption. It would be beneficial to have a highly accurate system that is electronic and that is capable of continuously delivering power measurements in terms of both kilowatt hours and reactive power (VARS) or Q at the lowest possible cost. It would also be advantageous if such a measuring system could measure the net power flow separately in each direction. The measuring system should also be essentially free of errors due to voltage offset in the active circuit elements. The system should therefore better have an offset compensation device which economically compensates for errors in multiple amplifier elements.

Presentation of the invention

Accordingly, a method for measuring the electrical power carried on a line according to claim 1, a measuring device for performing the method according to claim 13 and a modulator and a multiplier arrangement for the measuring device according to claims 35 and 46 were created. The device has means with which current and voltage signals are monitored on the line. A first signal converter delivers a first analog signal proportional to the current or voltage signal, and a second signal converter delivers a second analog signal proportional to the other, current or voltage signal. A modulator modulates one of the analog signals to produce a first modulated signal that is changeable between two levels at predetermined first clock intervals such that the first modulated signal has a medium level proportional to the selected one of the analog signals over any sufficient interval. First multiplication means are provided to gate the other of the analog signals in accordance with changes in the level of the first modulated signal so that the analog signals are multiplied together to produce a product signal that is proportional to the power carried on the line. A converter then converts the product signal to a first output signal which, in the preferred embodiment, is changeable between two levels at a predetermined converter clock interval in a manner proportional to the product signal and the power carried on the line.

The preferred measuring device according to the invention has a converter which measures the power at each polarity on the line separately and has digital means for changing the phase relationship between the analog signals in order to generate a product signal proportional to a present phase relationship power value, for example Reactive power or Q. The system also has an offset compensation device that corrects the voltage offset in the various operational amplifiers of a measuring system in order to eliminate offset errors and to ensure high accuracy. The offset compensation device described corrects a voltage offset between the inputs of N amplifier elements. The offset compensation device has N offset memory elements, each of which is connected to an input of the amplifier elements in order to obtain a compensation voltage which considerably reduces the offset error at the other input of the amplifier element. Any difference between the compensation voltage and the voltage offset of this amplifier element is referred to as offset error voltage, which at the other amplifier input er5

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seems. The system has a balancing circuit that can be sequentially connected to each of the N amplifier elements and the offset memory element associated therewith, such that the amplifier elements sequentially become the selected amplifier element that is compensated for in terms of offset. The balancing circuit is first connected to the other input of the selected amplifier element, during an intermittent transfer period in order to determine the offset error voltage. Then the matching circuit is coupled to the offset memory element which is coupled to the one input of the selected amplifier element during an intermittent charge period following the transfer period. The offset compensation device has means with which the transfer and charging period is created sequentially for each of the N amplifier elements, in such a way that offset errors in the measuring system are essentially eliminated.

Brief description of the drawings

Fig. 1 is a schematic block diagram of a measuring device for measuring the power on a line according to the invention.

FIG. 2 shows a schematic circuit diagram of the first modulator part of the measuring device shown in FIG. 1.

3 shows a schematic circuit diagram of the first output converter part of the measuring device shown in FIG. 1.

4 shows a series of graphic representations, designated as FIGS. 4a to 4g, which show certain selected internal and output signals which are generated during operation of the measuring device according to FIGS. 1 to 3.

5 shows a series of graphic representations, designated by FIGS. 5a to 5i, which show various internal and output signals which are generated by the converter according to FIG. 3, specifically during the measurement of signals of different polarities.

6 shows a schematic circuit diagram of a modulator of another embodiment for use in the power measurement device in question, which provides for a phase advance in the modulated output signal.

FIG. 7 is a series of graphical representations, labeled 7a to 7g, showing certain selected internal and output signals generated by the modulator of FIG. 6.

Fig. 8 is a schematic block diagram of a measuring device according to the invention, which has devices for generating measurements of reactive power and Q.

9 is a schematic circuit diagram of a signal multiplier which can be used in the measuring device according to FIG. 8 and which has digital circuits for phase adjustment in order to enable the generation of reactive power and Q measurements.

FIG. 10 is a series of graphical representations, labeled 10a through 10h, showing certain selected internal and output signals generated by the multiplier of FIG. 9.

FIG. 11 is a schematic circuit diagram showing further details of the digital phase adjustment circuit according to FIG. 9.

FIG. 12 is a series of graphical representations, labeled 12a through 12d, showing a selected phase adjustment of a modulated signal generated by the multiplier of FIG. 9.

13 is a schematic diagram of an embodiment of a voltage offset compensation device for use in the invention.

FIG. 14 is a graphical representation of the change in the offset error voltage that is generated with the compensation device according to FIG. 13.

15 is a schematic circuit diagram of a voltage offset

Compensation device of the type shown in Fig. 13 for an entire power measurement device.

FIG. 16 is a timing diagram illustrating the operation of the offset compensator of FIG. 15.

17 shows a schematic circuit diagram of a second embodiment of a modulator for use in the power measuring device according to FIG. 1.

Fig. 18 is a series of graphical representations, designated by Figs. 18a to 18e, showing various signals generated by the modulator of Fig. 17.

FIG. 19 shows the modulator according to FIG. 17 with a voltage offset compensation device according to another embodiment.

FIG. 20 is a timing diagram showing the control signals for operating the voltage offset compensation device according to FIG. 19.

21 shows an alternative embodiment of a modulator for use with the measuring device according to FIG. 1, which contains a voltage offset compensation circuit.

FIG. 22 is a timing chart showing the control signals for operating the offset compensator of FIG. 21.

Figure 23 shows an alternative embodiment of a modulator and associated dual polarity output circuit.

Figure 24 is a series of graphs, labeled Figures 24a through 24j, showing various signals generated by the modulator of Figure 23 and the associated output circuitry.

Best way to carry out the invention

The word "offset" is named "offset" in the following description. The term “zeroing circuit” is to be understood as an adjustment circuit. "Offset error voltage" is named "Deviation voltage".

1, the measuring device according to the present invention is shown schematically as a means for measuring the electrical power, which is led on a power line 10 from a source 12 to a consumer 14. The current on line 10 is generally designated II and the voltage Vl. The system has a signal monitoring and conditioning device, for example transformers 16 and 18, to monitor VL and II, respectively. The transformer 16, which is referred to as the first signal means, supplies a first analog signal Iai proportional to VL on line 20. The transformer 18, which is referred to as the second signal means, supplies a second analog signal Ia2 proportional to II on line 22. A shunt resistor 24 lies above that Secondary winding of transformer 18, whereby most of the current flows on line 22. The shunt resistor 24 provides a low impedance current path and can be selected to control the overall range of the current signal Iai on line 22.

The measuring device and the method according to the invention operate in such a way that the two analog signals Iai and Ia2 on lines 20 and 22 are multiplied together and then the multiplied product signal is converted into a suitable digital form. Generally speaking, this is accomplished by modulating one of the signals and then keying or switching the other of the signals to obtain a composite or product signal that has an average value proportional to the power. It will be apparent to those skilled in the art that either current or voltage can be modulated and the resulting modulated signal can be used to gate the other of the two analog signals to obtain the product signal. Accordingly, the designation of the first or second analog signal as a voltage or current signal could be reversed without the fundamental operation of the measuring circuit according to FIG. 1 ge5

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would change. Similarly, the names for the first and second signal monitors could be reversed.

The measuring device forms a multiplier for multiplying the signals Iai and Ia2, so that together they form a product signal that is proportional to the power transported on the line. In order to obtain the necessary multiplication, the voltage signal Iai is first fed to a first modulator circuit 30. The modulator 30 forms a modulator device with which the analog voltage signal Iai is converted into a first modulated signal, which can change between two levels at predetermined clock intervals. According to the principles of delta-minus-sigma modulation, the first modulated signal output has a medium level over any sufficient interval that is proportional to the first analog signal that is supplied to modulator input 32.

2, the analog (voltage) signal Iai is fed to a summing node 36 through an impedance 38. The modulator 30 has a modulator feedback device in order to generate a feedback signal If, which is likewise fed to the summing node 36. If is controlled by the modulator output, which is called the first modulated signal and appears on line 34. One or the other of two reference sources VI + and VI- are alternately connected to the summing node 36 by an impedance 40 in response to levels of the first modulated signal. The feedback signal If switches between the positive and negative reference sources in a manner that balances the first analog signal Iai over time. Current differences between If and the first analog signal result in a difference signal Idiff from the summation node 36. The instantaneous difference between input and feedback signal, namely Idiff, is integrated and measured with a modulator measuring circuit 42. The measuring circuit 42 has an active integrator with a capacitor 44 as a feedback element of an inverting operational amplifier 46. The signal at amplifier output 48 rises or falls linearly, depending on the polarity of Idiff. The integrated signal at 48 is compared to a modulator threshold level with a comparator 50 that goes high when the signal is above the modulator threshold level and low when the signal is below the modulator threshold.

The output of the comparator 50 is fed to the D input of a bistable modulator circuit 52. The Q output of the bistable circuit 52 is the first modulated signal. The bistable circuit 52 changes only at predetermined first clock intervals, which are determined with an external clock. A suitable clock for this purpose is formed by a conventional oscillator 54 and a frequency divider circuit 56, which are shown in Figures 1 and 2. For the sake of simplicity, the time interval between the pulses supplied by the frequency divider 56 is referred to as the first clock. The bistable circuit 52 has a Q output as well as Q, where (J is the inverse of Q. Both the Q and Q outputs are used to control the feedback signal If by actuating two switches 58 and 60, respectively Since Q and Q are inverse to each other, as mentioned, only the Q output signal will be referred to here as the first modulated signal, but it should be clear that both outputs Q and Q, which are referred to as "first modulated signal" contain designated information, and line 34 designates the lines that carry both the Q and Q signals.

Since the first modulated signal is emitted via bistable circuit 52, the first modulated signal on line 34 can change between two levels at the predetermined first clock intervals. Even if the level does not need to change every clock interval, the modulator circuit ensures that if the level of the first modulated signal actually changes, this change only takes place at the predetermined first clock intervals and not at other times. Changes between the high and low levels of the first modulated signal cause switches 58 and 60 to switch simultaneously, and corresponding inversions in the polarity of the feedback signal If to summing node 36. When the integrated difference signal rises above or falls below the level threshold of comparator 50 , changes in the level of the comparator output are caused. At each clock interval, bistable circuit 52 determines whether the output of comparator 50 has changed, and if so, it provides a corresponding change in outputs Q and Q. The size of the analog input signal provides a directly proportional change in the period of time during which the first modulated signal is at a given level. Accordingly, the first modulated signal has a medium level or a medium amplitude, which is either at one of its two levels or between them, and over a sufficiently long interval this medium amplitude is proportional to the analog input signal.

As an example of the operation of modulator 30 when the input signal at input 32 is zero, the Q output of bistable switch 52 is high for exactly the same time as it is low, so that a medium level is generated that is exactly in is midway between the high and low levels of Q. If the input signal at input 32 has a positive value, the positive current in summing node 36 must be compensated for by a larger negative current which is supplied from negative reference VI via switch 58 to the summing node. Accordingly, Q is proportionally low longer than high and switch 58 is closed for a longer time and switch 60 is open than vice versa. If the input signal is negative, the positive coupling reference must be provided for a larger portion of the time for If to equalize the input signal, and Q is more high than low. It is a feature of the modulator according to the invention that Q can remain high or low for as long as If needs to compensate for the input signal at the summing node.

In order to generate a current signal for multiplication with the modulated voltage signal, the system has means with which inverted and non-inverted representations of the line current II are generated. 1, the analog current signal Iaî is first fed to an amplifier 70, after which the signal is fed to a signal inverter circuit 72. The illustrated inverter circuit has an operational amplifier 74 and gain adjustment resistors 76 and 78. The amplified signal Ia2 is applied to the inverting input of amplifier 74, which is configured to produce a gain of -1. The inverted signal is then fed to one of two switches, which together form a first push button device 80. The inverted signal goes to switch 82 and a second line 84 supplies the non-inverted amplified signal Ia2 to switch 86. It will be appreciated that a suitable center tap transformer may be used in place of the second transformer 18 and in this case the signals for the circuits 82 and 86 could be provided directly from the transformer.

The Q and Q outputs of the bistable modulator circuit 52 are used to operate the switches 82 and 86 to gate the second analog signal Ia2 based on the first modulated signal. Since Q is inverse to Q, switches 82 and 86 are switched in an alternating manner such that the output of key 80, at 88, is an analog signal that is switched in a modulated manner between positive and negative polarity. Such a gate operation

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is commonly referred to as time division or amplitude-mark gap modulation. Switches 82 and 86 multiply the two analog signals representing the current and voltage of the power carried on line 10. The resulting signal, referred to as the product signal, appears at the first gate output 88 and is proportional to the power carried on the power line 10.

As shown in FIG. 1, the product signal output of the first key device is fed to a first converter circuit 90. The converter circuit converts the product signal into a first output signal on line 92, which can be changed proportionally between the two levels at predetermined converter clock intervals in the product signal. Converter 90 operates essentially as a low pass filter that extracts the DC component or the average of the product signal. The resulting first output signal is proportional to the power carried on line 10.

3, converter 90 is essentially a delta-minus-sigma modulator of a type similar to modulator 30, and is designed to provide separate modulated output signals proportional to each polarity of the input signal. In order to simplify the description, the converter 90 and its operation should first be described with reference to a first polarity of the operation. The components within block 94 include all elements that are used in operating a polarity. In the following example, it is assumed that the product signal to be converted is predominantly positive, and it is assumed that this corresponds to a power flow on line 10 from source 12 to load 14. As in the modulator 30, the input signal to the converter 90, designated Ip (product signal), is initially fed through an impedance 95 to a summing node 96. A feedback device delivers a second signal I2 to the summing node from one of several reference sources. For positive polarity operation, the reference sources alternate between a negative reference source 98 (VR—), which is fed by a switch 100, and an earth connection 102, which is fed by a switch 104. Since only positive values of the product signal are considered, it is sufficient to switch I2 between earth and a negative value in order to balance the product signal at summing node 96 over time.

As has been described for the modulator 30, each difference between the product signal Ip and I2 represents a difference signal that is fed to a measuring circuit 106. The measuring circuit integrates the difference signal and compares the difference signal with a first level threshold. The preferred embodiment of a measuring circuit according to FIG. 3 has an active integrator 107, which consists of an amplifier element 108 and a capacitor 110 as a feedback element. The voltage at amplifier output 112 rises or falls depending on the polarity of the difference signal at summing node 96. The integrated difference signal at 112 is fed to a first comparator 114, the threshold of which is set to a first selected level threshold. If the integrated difference signal is 112 above the first level threshold, the output of comparator 114 is high. If the integrated difference signal is below the first level threshold, the output of the comparator 114 is low.

The comparator output, referred to as the first control signal, is fed to the D input of a bistable circuit 118 via line 116. The Q output of the bistable circuit 118 can only change at predetermined converter clock intervals, which are preferably longer than the first clock intervals for the modulator 30. The converter clock intervals can be generated by adding a second frequency divider 120 to the first clock generator 56. The time intervals between the pulses generated by the frequency divider 120 are called converter clock intervals and the frequency divider is called the converter clock. The Q output of bistable circuit 118 is the first output signal that controls switches 100 and 104 to determine the operation of the feedback system that provides second signal I2 to summing node 96. Switch 104 is actuated by a gate 122 which emits a high signal to close the switch only when both inputs 124 and 126 are low. Gate 122 as shown is a conventional negative AND gate. During periods with positive product signals, input 126 remains low, as will be described later. Accordingly, switch 100 is closed, so that VR - is connected to summing node 96 whenever Q is high and when Q is low, switch 100 is open and switch 104 is closed.

The operation and the method of the measuring device according to the invention will now be described in connection with FIGS. 1 to 4. For the sake of simplicity, it is assumed that the power on line 10 flows predominantly in the positive direction. The voltage on line 10 is shown in FIG. 4a as a sinusoidal AC voltage curve. The current Il is shown in FIG. 4f as an increasing value, represented by curve 128. The first step is that the transformers 16 and 18 monitor the current and voltage signals and deliver analog signals Iai and Iaî that are proportional to the line voltage and current. One of the analog signals, voltage signal Iai in the preferred embodiment, is then fed to the first modulator 30. 4c shows the integrated difference signal which is generated in modulator 30 with the delta-minus-sigma modulation technique described above. The integrated difference signal is fed to the measuring circuit 42. 4b illustrates the first clock intervals that are generated with the first clock 56. The inclination of the integrated difference signal in FIG. 4c only changes at the predetermined clock intervals that are determined by the first clock signal. Since the bistable circuit 52 clocks on the leading edge of each upward moving pulse, the predetermined first clock intervals are shown starting at the points labeled a, b, c, d, etc. in Fig. 4b. The integrated difference signal is then fed to the comparator 50. Line 130 in Fig. 4c represents the modulator level threshold in comparator 50. Note that the integrated difference signal at the beginning of each clock interval after crossing threshold 130 reverses the slope. The output of the comparator 50 is shown in Fig. 4d. Whenever the integrated difference signal is below threshold 130, the comparator output is low, and when the integrated difference signal is above threshold 130, the comparator output is high. The comparator output is then fed to the D input of bistable circuit 52, which provides Q, or the first modulated output signal, as shown in Fig. 4e. The Q output is the result of the modulation of the voltage signal and can change between two levels at the predetermined first clock intervals.

Since the bistable circuit can only change at the predetermined clock intervals according to FIG. 4b, the changes in Q slightly lag behind the changes in the comparator output FIG. 4d. Depending on the level of accuracy required in the signal multiplication system, it may be desirable to compensate for the slight delay in the modulated signal introduced by bistable circuit 52. Such correction can be accomplished by inserting an RC circuit on line 20 to introduce a small phase lead in signal Iai when it enters modulator input 32. Another technique would be to introduce a slight delay in the analog current signal U2. A third alternative, where a delta minus

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sigma modulator with digital phase advance circuit will be described later. The phase adjustment introduced, which is only a fraction of a first clock interval, should be the average of the delay induced by the lag of Q relative to the comparator output.

4f illustrates the same and opposite analog signals proportional to the line current IL. Curve 128 represents a growing current signal and curve 129 is the inverse signal generated by inverter 72. The next step is to gate the analog current signal using gate device 80. The output of gate device 80 is the product signal, curve 131, shown in Fig. 4g. Curve 131 is generated by switching between signals 128 and 129, corresponding to the first modulated signal shown in Fig. 4e. The average level or the equal component of curve 131 is represented by curve 132 in FIG. 4g.

In the example given, it is assumed that power flows predominantly in one direction into the consumer 14. Accordingly, the product signal Ip shown in FIG. 4g has predominantly positive polarity, as indicated by line 132. For purposes of describing the operation of converter 90 below, it will be assumed that the product signal has a predominant and average value that is positive. Although the designer can choose the actual polarity of the product signal, the product signal will predominantly have a first polarity if the power on line 10 has the first polarity with unidirectional power flow and will predominantly have a second polarity if the power on line 10 has the second or opposite polarity, with the power flowing in the other direction.

The next step is to convert the product signal Ip into a first output signal, which can change at predetermined intervals between two levels, in proportion to Ip. For this purpose, reference is made to Figures 3, 4 and 5. The product signal Ip according to FIG. 4g is fed to the converter 90. Both Ip and the second signal I2 are fed to summing node 96, where the instantaneous difference is integrated into an integrator 106. The time constant of integrator 106 is selected to be long compared to the switching frequency of first modulator 30. The converter 90 can therefore act as a low-pass filter and only respond to the DC component or the mean value of the product signal Ip. For this reason, Ip is shown in FIG. 5a as a step-free analog curve, although this value actually varies in the manner shown in FIG. 4g. 5a shows only the mean of Ip. The time scale in FIG. 5a is considerably compressed in comparison with the time scale in FIG. 4g. For purposes of illustration, it is assumed that the interval 134 in FIG. 5a is equivalent to the entire length of the curve 132 in FIG. 4g. 5a shows the converter clock intervals generated with clock 120.

If only a positive power flow is considered, which is shown in FIG. 5a between to and ti, integrator 1Q6 delivers an integrated difference signal (IDS) according to FIG. 5c at the output. The integrated difference signal rises and falls around the first level threshold TL1 of the comparator 114. The integrated difference signal (IDS) is fed to the comparator 114, where it is compared with the first level threshold TL1. The comparator 114 outputs a control signal 133 on line 116, as shown in Fig. 5d. The next generated signal is the first output signal, shown in FIG. 5e, which is output by the bistable circuit 118. The control signal 133 changes its level depending on the level of the integrated difference signal relative to the threshold TL1. When IDS is above TL1, signal 133 is high and when IDS is below

TL1, signal 133 is low. The next step is to output the first output signal according to FIG. 5e through the first bistable circuit 118. The first output has a medium level proportional to a first polarity of power on line 10 for any sufficient interval. It can only change at the predetermined converter clock intervals, which are shown as w, x, y and z in FIG. 5b.

Operation of the comparator 90 with one polarity includes switching the feedback signal I2 between the first reference source 98 and a second reference source 102, depending on the level of the first output signal (Fig. 5e). Since the second reference source 102 is an earth connection, the previously described part of the converter 90 cannot take into account negative power flow on the line 10. If the power flow (Ip) becomes negative, as is the case between times ti and t2 in FIG. 5a, additional circuitry in converter 90 is used. 3, the converter 90 has a second comparator 140, which receives the output from the integrator 107. Comparator 140 has a second level threshold TL2, which differs from the first level threshold of comparator 114. The level thresholds should be sufficiently far apart to take into account the greatest expected variations in the integrated differential signal output from integrator 107, without the level thresholds of both comparators being crossed at the same time. The integrated difference signal is fed to the non-inverting input of comparator 114 and the inverting input of comparator 140, so that the outputs have opposite polarities. The output of comparator 140 goes high when the integrated difference signal is below the second level threshold in comparator 140 and goes low when the integrated difference signal is above the second level threshold in comparator 140.

The output of the comparator 140 is fed to the D input of a second bistable circuit 142. The second bistable circuit 142 outputs a second output signal from the Q output. The second output signal is at one of two levels, depending on the level of the integrated difference signal relative to the second level threshold at each of the converter clock intervals. The second output signal is applied to the output 126 of a negative AND gate 122 and a switch 146 to connect a third reference source VR + to the summing node 96. The feedback signal I2 is thus dominated by the level of the second output signal, which has an average level proportional to the power of the second polarity, which is carried on line 10.

The operation of converter 90 with the second polarity will be described with reference to FIGS. 3 and 5. After time ti, the direction of power flow reverses and product signal Ip begins to draw charge from summing node 96. According to FIG. 5c, the integrated difference signal drops just shortly before ti, and this means that the negative reference source VR is connected to the summing node via switch 100. At the clock pulse that follows the crossing of the first level threshold TL1, the switch 100 opens and the switch 104 closes, so that the summing node is connected to earth. Since the product signal Ip is negative after the time ti, the integrated difference signal continues to integrate downwards until the second level threshold TL2 of the comparator 140 is reached, and at this time output 135 goes high (cf. FIG. 5g). At the next comparator clock interval after converter 140 goes high, the Q output of bistable circuit 142 (the second output signal) goes high, as shown in Figure 5h. When the second output signal goes high, a switch 148 is closed which is connected to the third reference source 146 (VR +). The third reference source supplies a positive current I2 to summing node 96 to compensate for the negative product signal Ip and IDS through TL2 zu5

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drive back. When TL2 is crossed, signal 135 goes low again so that the second output signal goes low at the next clock interval. During second polarity operation, the first output signal (FIG. 5e) remains low and whenever the second output signal (FIG. 5h) is low, both inputs of gate 122 are low and its output goes high. When the output of gate 122 goes high, switch 104 is closed and the ground connection, source 102, is connected to summing node 96. When switch 104 is closed, IDS is allowed to cross in the other direction via TL2. In the meantime between times ti and t2, when the power flow is negative, the integrated difference signal is kept near the second level threshold TL2.

The converter 90 shown in FIG. 3 is equipped with three different reference sources, the second of which is a connection to the common earth for the measuring circuit. Because of the configuration of the circuit elements, the ground connection is always used when the integrated difference signal is in the area between the two thresholds TL1 and TL2. It is not necessary for the second reference source to be a ground connection. Separate positive and negative reference sources can be used for each company polarity if desired. In such a case, the first and second reference sources would be used to provide the second signal I2 to the summing node 96 if the product signal Ip was of a first polarity, and separate third and fourth reference sources could then be used to provide the second signal h to the summing node 96 when the product signal Ip has the other polarity. In practice, the selection of the values for the reference sources is dictated by the need to keep the integrated difference signal in the vicinity of the level threshold of the comparator currently in use. The designer can freely select the sizes and polarities of the reference sources.

The use of reference sources in converter 90, which includes at least one ground or ground connection, improves the overall accuracy of the modulated signal output. Although there may be variations in the positive and negative voltage reference sources), the ground connection remains fixed. If the positive and / or negative reference source is above or below the correct value, there is a deviation in that a level is slightly longer or shorter than it should be because during the time that the voltage reference source is providing the feedback signal a little too much or too little electricity is supplied. The closer the input signal is to ground (zero), the smaller the error. Identical and opposite reference sources, such as are used in the feedback system of modulator 30, have a greater potential for error if there is a mismatch between reference sources VI + and VI-. Since the feedback system of modulator 30 always switches between VI + and VI—, an error resulting from a reference voltage mismatch tends to keep the modulated output signal at one level or another for an incorrect period of time, regardless of the size of the input signal. In the case of modulator 30, this is not a problem because it modulates the line voltage signal, which generally changes only by a small amount. Accuracy therefore only needs to be maintained over a small range. Converter 90, however, requires greater accuracy because of the wide variations in the product signal representing line performance. For this reason, the separation of converter operations between positive and negative polarities of power has clear advantages. Since only one polarity is measured by each comparator, reference sources can use a ground connection to create the feedback signal, so that the converter accuracy is improved overall. The information provided about the flow of power at any polarity is also desirable because it provides additional data about the nature of the consumer and his performance requirements.

The two output signals, which are output on lines 92 and 144 by converter 90 (cf. FIG. 1), can change between two values at the converter clock intervals. In order to obtain a suitable digitized output in which the pulse density is proportional to the power flow, a system is provided to convert the output signals into pulse trains. According to FIGS. 1 and 5, the two output signals are delivered to two AND gates 150 and 152. A second input for the AND gates comes from converter clock 120. FIG. 5f shows the pulse train which is supplied by power of first polarity from AND gate 150. The pulse train has a pulse density proportional to the magnitude of the power flow in one direction on line 10. Similarly, Fig. 5i shows a pulse train for second polarity power from the AND gate 152 for power flow in the opposite direction. Various means are available to do this to process both digital output signals according to FIGS. 5f and 5i. For example, it would be expedient to deliver the digital signals to a counting device in order to count the pulses for the positive or the negative polarity. The meter could then display or display the total power consumption. A counter 154 illustrates such a display concept. If a strobe signal is additionally supplied to the counter 154, power measurements in corresponding units, for example kilowatts, can easily be obtained. Separate readings for power flow in each direction can also be obtained.

As mentioned above, a slight delay is introduced into the modulated output signal, since the bistable circuit 52 (FIG. 2) can only be switched over at predetermined clock intervals. FIG. 6 shows a novel delta-minus-sigma modulator 30 'with a digital phase advance in order to compensate for the phase lag. Identical elements in the modulators according to FIGS. 2 and 6 are identified by the same reference symbols. It should be noted that this digital phase advance circuit can also be used in cases other than in power measurement systems. If desired, a phase lead circuit can also be made available which is more than sufficient to compensate for the phase lag caused by the bistable circuit 52 at the output according to FIG. 2.

The modified modulator 30 'of FIG. 6, like the modulator of FIG. 2, has a bistable circuit 52 which controls a source of feedback current If via switches 58 and 60. A summation node 36 receives the input signal Iai via input resistor 38. Current differences between the feedback and the input signal are represented by Idiff, and this difference signal is measured with measuring circuit 42. The output control signal from comparator 50 is high when the inverted difference signal is above the comparator threshold and low when the integrated difference signal is below this threshold.

The modulator 30 'differs from the modulator 30 according to FIG. 2 in that it contains a digital shift between the measuring circuit 42 and the bistable circuit 52. The digital shift introduces a time delay into the control signal emitted by the comparator 50. In Fig. 6, the digital shifter is a bistable circuit 59 which receives the control signal which is output by the comparator at its D input. For the purposes of the following example, bistable circuit 59 is clocked at the same rate as bistable circuit 52, but out of phase by half a clock interval.

The operation of the modulator of FIG. 6 to achieve a

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Phase advance in the modulated output signal is described in connection with FIG. 7. The input signal Iai of the modulator 30 'is shown in Fig. 7a. The output of the first clock 56 is shown in Fig. 7b. The first clock 56 also provides a signal to the bistable circuit 59 via an inverter 57, and the second clock signal is shown in Fig. 7c. If IAi at clock pulse a is positive and the Q output of bistable circuit 52, shown in FIG. 7g, is initially high, If in summing node 36 is positive. This results in a positive idiff, which is fed to the inverting input of the integration amplifier 46, so that it is ensured that the integrated difference signal initially falls at point 47, at 21 in FIG. 7d. Line 22 in Figure 7d represents the threshold of comparator 50. When the integrated difference signal crosses threshold 22, the control signal shown in Figure 7e transitions from high to low. If it is assumed that the bistable circuit 59 clocks with upward pulses a ', b', c ', d', e 'etc., the output of the bistable circuit 59 goes from high to low at the clock pulse a'. The output of the bistable circuit 59 (Q ') is referred to here as the delayed control signal, which is then supplied to the D input of the bistable circuit 59. Fig. 7f shows the delayed control signal and Fig. 7g shows the Q output of the bistable circuit 52. If Q 'changes from high to low, the Q output of the bistable circuit 52 goes from high to low on its next clock pulse b . The change in Q opens switch 60 and closes switch 58, causing If to become negative. The integrated difference signal will then rise and cross the comparator threshold 22 and cause the control signal to go high again. At the clock pulse d 'of the second clock, the Q' output of the bistable circuit 59 goes up again. This again causes the Q output of the first bistable circuit 52 to go high at the following clock pulse e.

The process described continues, with the Q output of bistable circuit 52 providing the signals to control the feedback loop of the modulator. Assuming that the time delay introduced by the digital shifter represented by bistable circuit 59 is not large enough to create instability in the feedback loop, modulator 30 'provides a modulated signal that is equivalent but not identical to that from modulator 30 is delivered. Equivalence here means

that the Q output of bistable circuit 52 is a modulated signal that changes at predetermined first clock intervals in a manner that is proportional to the signal input of the modulator. The Q 'output of bistable circuit 59 leads the Q output of first bistable circuit 52 by an amount that depends on the differences in the clock signals applied to the two bistable circuits. This advance occurs as a natural consequence of the fact that the Q output of the bistable circuit 52 changes only at the next clock pulse subsequent to a change in the Q 'output of the bistable circuit 59. The Q 'output is therefore a real "leading" signal for the Q output.

The output signal on line 34 then has a phase lead equal to one half of the first clock interval compared to the Q and Q outputs of bistable circuit 52. Since the clock intervals supplied to bistable circuit 59 and bistable circuit 52 are the same, may the delayed control signal provided on lines 34 changes only at the same intervals as the Q and Q outputs of bistable circuit 52 and is otherwise similar to any other delta-minus sigma-modulated signal. The clock signal supplied to the bistable circuit 59 effectively becomes the determining clock signal that controls changes in the output of the modulator. It would be possible to have another type of one

Use digital shifter, such as a multi-stage shift register, in place of bistable circuit 59 if the delay introduced is not so long as to destabilize the feedback loop. The digital shifter used can also be clocked at a different rate than the first bistable circuit 52, although that would change the characteristic of the delayed control signal. For example, if a multi-stage shift register clocked at a high rate were used in place of bistable circuit 59, it would delay the control signal by a selected number of short intervals. The output of such a shift register would be a delayed control signal that could change at the higher clock rate. A shift register could also be used that has different levels that are clocked at different rates. In such a configuration, the longest clock interval that would be used to clock any of the stages would determine the intervals at which the final delayed control signal would be changeable. Any control signal delay system should include at least one bistable circuit that is clocked at discrete intervals so that the modulated output of the modulator (the delayed control signal) becomes changeable at those discrete intervals.

The phase advance caused in the modulator 30 'can be selected. This choice is made by adjusting the clock signals that are supplied to the bistable circuits 52 and 59. Assuming that a first clock signal that provides pulses at first clock intervals is supplied to bistable circuit 52 and a second clock signal that supplies pulses at second clock intervals is supplied to digital shifter (bistable circuit 59), and both clock intervals are the same the phase offset between the clock signals determines the size of the lead in the modulator output. In the example discussed in connection with FIG. 7, the second clock was the inverse of the first clock and the total offset was equal to half a clock interval. If the clock pulses supplied from the second clock to bistable circuit 59 were three quarters of a clock interval before the pulses supplied to bistable circuit 52, a phase advance of three quarters of a clock interval would be generated. It is the amount of delay between a change in the Q 'output of bistable circuit 59 and the Q output of bistable circuit 52 that determines the amount of lead time in the signal delivered on lines 34.

The amount of phase lead that can be achieved by the modulator of Figure 6 depends on the degree of delay that can be introduced into the feedback loop of the delta-minus-sigma modulator without causing destabilization. However, it is known that a delay of a fraction of a clock pulse works in the manner described in the example above and provides the phase lead in the modulated signal as described.

8 shows a measuring system according to a further embodiment of the invention, which delivers an additional output power measurement either as reactive power or Q. As has been described in the background section above, the reactive power or Q power mass represents a specified phase relationship between the current and voltage signals. The reactive power is obtained by multiplying the current by a voltage signal that lags by 90 °; Q is obtained by multiplying the current by a voltage signal that lags by 60 °. In the measurement system according to this embodiment of the invention, the reactive power, Q or any other power value with a desired phase relationship can easily be obtained by delaying the output of the modulator 30 by a selected amount. The Delays5

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tion can be conveniently caused by using time delay devices, such as a shift register, as described below.

The Q output of the modulator 30 in the embodiment according to FIG. 8 is supplied to both a gate device 80 and a shift register 160. The shift register 160 delays the output of the modulator 30 by a selected delay interval. The amount of delay depends on the selected phase relationship of the desired power value (reactive power or Q) and on the frequency of the measured AC voltage curve (50 or 60 Hz). In order to simplify the circuit, only the Q output of the modulator 30 is fed to the shift register 160. The time-delayed output of the shift register is then fed to an inverter 161, and both the inverted and the non-inverted signal become the time-delayed signal on line 162. Here and below, the expression "time-delayed signal" becomes equivalent to a "phase-modified signal »And the whole is to be understood in the sense that the phase modification introduced is implemented by means of a time delay introduced into the signal.

The further processing of the time-delayed modulated signal is exactly the same as that of the first modulated signal of the embodiment according to FIG. 1. The time-delayed modulated signal is fed to a second gate device 164, which contains two switches 166 and 168, with the time-delayed one modulated signal can be controlled. The inverted and non-inverted analog current signal Ia2 is supplied to switches 166 and 168. The phase modified modulated signal alternately closes switches 166 and 168 to multiply the current and voltage signals together and provide a second product signal at 170. The second product signal is then fed to the input of a VARS (reactive power) / Q converter 172, which is exactly the same as converter 90 shown in FIG. 3. VARS / Q converter 172 provides two output signals, depending on the polarity of the power on line 10, in exactly the same way as converter 90. The outputs of converter 172 are two output signals that are between two levels at the converter clock intervals can change in a manner that is proportional to the second product signal and the selected phase relationship of the power value [reactive power (VARS) or Q, 50 or 60 Hz] of the power on line 10. Subsequent processing of the two output signals from the VARS / Q converter 172 is exactly the same as for the outputs from converter 90 according to FIG. 1, including the use of counting devices which are suitable for outputting selected power values.

A selector (not shown) can be provided to select either reactive power or Q as the second output of the measuring system. The selector adjusts the shift register 160 to cause the voltage lag required to create the selected phase relationship and to select an appropriate delay at the same time.

The novel digital phase selection technique illustrated as an example in Fig. 8 is not limited to power meter applications. The technique can be used in any application of signal multiplication where the phase relationship between input signals can be adjusted to measure selected phase relationship product values.

FIG. 9 shows a multiplier similar to the multiplier used in the power measurement system of FIG. 8. The same elements are provided with the same reference symbols. Iai and Ia2 are the signals to be multiplied and are assumed to be periodic voltage profiles, not necessarily sinusoidal, which have a predetermined phase relationship to one another. As in the case of the power measurement system according to FIG. 8, the multiplication by the time division or

Marking gap multiplication technique is performed in which one of the signals Ia2 is modulated and used to gate the other signal Iai or reverse its polarity to obtain a product signal. The signal Ia2 is fed to a gate device in both inverted and non-inverted form. A conventional inverter 72 supplies the signal to switch 82. The non-inverted signal is fed to switch 65. The modulated signal for controlling switches 65 and 66 is fed via line 34 to the gate device.

The modulator 30 according to FIG. 9 is equivalent in construction and operation to the corresponding modulator 30 according to FIGS. 1 and 2. In order to obtain a selected phase relationship between signal Iai and Iaî, a digital shifter 160 is used, which has a selected delay in the output of the modulator 30 introduces. The digital shifter 160 can take various forms, a simple version is illustrated in element 198 in FIG. 11. The operation of a shift register can simply be illustrated by connecting a series of stages consisting of bistable circuits 200 through 204 in such a way that the Q output of a bistable circuit is fed to the D input of the adjacent bistable circuit. A clock signal provided to each of the bistable circuits via line 196 ensures that all stages are clocked simultaneously. A digital pulse on line 53 into shift register 198, which goes either from low to high or from high to low, is delayed by an input clock interval by each bistable circuit through which it passes. For example, if the signal on line 53 goes low to high, the Q output of bistable circuit 200 goes low to high on the next clock pulse. When the Q output of bistable circuit 200 goes low to high and this signal is applied to the D input of bistable circuit 201, the Q output must wait for the next clock pulse to go high because of the inherent switching delays. In this way, digital signals can be conveniently delayed by any random number of discrete intervals simply by providing enough delay stages in the shift register. Shift registers are usually equipped with a plurality of output lines 206, on which the signal can be extracted. The position of the pin determines the total delay introduced as a function of the clock frequency.

The digital time delay device 160 of the multiplier system according to FIG. 9 is assumed to be a conventional shift register, for example shift register 198 in FIG. 11. The multiplier system requires that the introduction of a selected time setting into one of the multiplied signals using a digital shifter introduces a delay that a selected one Number of discrete intervals. Shift register 198 is a suitable digital shifter to generate such a delay. Referring now to Fig. 10, let us assume that signals Iai and Ia2 are to be multiplied together and that a 90 ° phase lag is introduced in signal Ia2. Fig. 10a shows an example of a first input signal Iai (VI) and Fig. 10g shows an example of a second input signal Ia2, which are to be multiplied together. FIG. 10b shows the clock signal provided by clock 56 and FIG. 10c shows the output signal of integrator 42, which results from the input signal Iai. FIG. 10d shows the resulting output of the comparator 50. The output of the modulator 30 is shown in FIG. 10e and is carried on line 53 of FIGS. 9 and 11. The clock signal from modulator clock 56 is fed to shift register 198 of line 196. In the given example, the clock intervals shown in FIG. 10b are twenty-four times the frequency of the signal Ia2. A phase lag of 90 ° therefore requires a delay of six clock intervals. Under the assumption

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that pin 206 'of shift register 198 is the sixth pin,

the signal Ia2 after modulation and delay by 90 ° will be delayed by a total of six clock intervals which are emitted by the clock 56. The output signal at pin 206 'of shift register 198 is shown in Figure 10f. The delayed modulated signal shown in FIG. 10f is an exact representation of the modulated Q output of modulator 30 shown in FIG. 10e shifted right by six clock intervals.

The signal multiplication is realized in that the delayed modulated signal according to FIG. 10f is given to the signal gate device via line 34. Line 34 contains both inverted and non-inverted versions of the delayed modulated signal by feeding the signal to a conventional digital inverter 161. Signal Iai is that shown in Fig. 10g, both in inverted and non-inverted form. The multiplication is carried out by means of the switches 82 and 86, which are opened and closed alternately with respect to one another, point 88 in FIG. 9 being switched between the non-inverted and the inverted version of the signal Iai. The resulting signal is shown in Figure 10h. The signal in FIG. 10h can then be passed through a suitable low pass filter 90 to provide an average or DC value, as shown in curve 132 in FIG. 10h. Curve 132 represents a product signal proportional to the product value of Iai and Ia2, a phase lag of 90 ° being introduced in Ia2. For example, if signal Iai is proportional to the current on a power line and signal Ia2 is proportional to line voltage, the product signal represented by curve 132 in Fig. 10h would be proportional to the reactive power.

A particular advantage of using a delta-minus-sig-ma modulator such as modulator 30 in connection with the multiplier in question is that the modulated signal can only be changed at the predetermined clock intervals. Digital time delay techniques necessarily divide an incoming signal into discrete units or intervals. The length or duration of these intervals is chosen by the designer. Digital signals transmit information on the pulse edges when the signal goes from low to high or from high to low. A shift register from a series of bistable circuits "checks" for such pulse edges every time it is clocked. The higher the clock frequency, the more frequently the incoming signal is polled on a pulse edge. Because the delay introduced into a signal at each stage of a shift register depends on the clock frequency, shift registers that are clocked at high frequency require more stages to achieve a certain delay than shift registers that are clocked at low frequency. Clocking a shift register with a low frequency naturally means that the incoming signal is scanned less often on pulse edges, and this can be disadvantageous if the position of the pulse edges is unknown, as is the case with conventional signals that are modulated pulse-width. The modulator 30 emits a signal with pulse edges that only occur at predetermined clock intervals. When the clock signals applied to the modulator and shift register 198 are synchronized,

The shift register only "checks" for pulse edges at the required times. This means that fewer shift register stages are required to introduce a certain delay into a modulated signal than would be the case if the position of the pulse edges were not precisely known. In fact, in the example described above, the shift register can be clocked at the same rate as the modulator 30 without losing any information. It is therefore possible to use an inexpensive shift register which has relatively few stages to cause a certain delay in a delta-minus-sigma-modulated signal, whereas a much larger shift register would be needed to cause a comparable delay in a signal, which can have pulse edges at arbitrarily distributed locations. Even if a relatively high frequency shift register were used to delay a signal stochastically modulated at a considerably lower frequency, there would still be some loss of information if a pulse edge were not precisely synchronized with the shift register clock. In the embodiment of the present invention described above, no such loss of information occurs because the modulator and the shift register are synchronized with each other and the pulse edges are therefore not offset.

The clock intervals at which the shift register is clocked need not be exactly the same as the first clock intervals of the modulator 30. However, it is preferable that the shift register clock is synchronized with the modulator clock. To avoid loss of information, the shift register clock should operate at a frequency that is not lower than that of the modulator, but can operate at higher rates to obtain practically any time delay. A convenient way to increase the frequency of the shift register clock while maintaining synchronization with the first clock intervals of the modulator is to use a frequency divider for the modulator clock. While in the example described above the desired time delay in the modulated signal corresponded to an integer number of first clock intervals, this need not always be the case. To provide additional flexibility in the selection of a time delay, it may be desirable to use either a second shift register or additional stages within a single shift register which are clocked at a higher frequency and which therefore introduce incremental delays into the modulated signal. The shift register states in element 212 according to FIG. 11 illustrate a technique for achieving a further option in the digital time setting according to the invention. In this example, the delayed signal output from any selected stage of shift register 198 is given to a second group of shift register stages, which are shown in FIG. 11 as a second shift register 212. A number of bistable circuits 216 form the shift register 212. The delayed signal from the shift register 198 is fed to the input 214 of the shift register 102. A clock signal on line 208, which preferably has a higher frequency than the first clock 56, is supplied to the bistable circuits which form the shift register 212. The higher clock frequency can be conveniently obtained by means of an oscillator 220 which operates at a higher frequency than the first clock 56. By using a suitable frequency divider 212, clock signals of different frequencies can be applied to the different shift register stages as well as to the modulator 30 if desired.

Here, the term "first clock intervals" generally refers to the clock signals that come from the first clock 56, and second clock intervals are intended to be those that are output by the second clock generator 220. In addition, the shift register stages illustrated in FIG. 11 can either be viewed as a first shift register 198 and second shift register 212, or these can be viewed as a single shift register with a plurality of stages clocked at different selected frequencies. Both with the use of separate oscillators and with the use of a single oscillator with a frequency divider, the presence of different clock signals increases the flexibility of the digital shifting techniques used in the invention

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will. Delaying a signal with a shift register with a number of stages, all clocked at the same rate, allows the signal to be delayed by any number of discrete intervals up to the maximum number of stages in the shift register. By providing additional stages that are clocked with a different clock signal, additional selected delay intervals can be created. A signal can be sent through a first shift register and delayed by a certain number of first intervals, and then sent through a second set of shift register stages and delayed by an additional number of second intervals. A delay of practically all desired integer and fractional increments of the first intervals can thus be provided. A similar flexibility of signal delays with digital means can be obtained by using a second clock which operates at the same frequency as the first clock but is offset in time by a selected amount. Thus, for example, if a signal is passed through a first shift register that is clocked at first intervals and then fed to a second stage that is fed with the inverse of the clock signal for the first interval, there will be an additional delay of one half of a first clock interval introduced. Depending on the offset between the clock signals applied to the first and second groups of shift register stages, virtually any amount of delay can be introduced.

An example of the operation of the modulator and the digital time delay device according to FIGS. 9 and 11 is shown in FIG. 12. If it is assumed that a first clock signal coming from the clock 56 shown in FIG. 12b and a second clock signal provided by the second clock 220 shown in FIG. 10a, one is put into the shift register input modulated signal delayed in the manner described below. In this example, the second clock 220 is exactly twice the frequency of the first clock 56. For example, if a delay in the modulated signal of two and a half first clock intervals is desired, the shift register is configured to have output pin 206 ″ with the input 214 of the second shift register is connected. In this manner, a modulated signal input via line 53 passes through two shift register stages 200 and 201 and into the first stage of the second shift register 212, and then the signal is output to pin 218. With such an arrangement, the signal is delayed by two full first clock intervals and an additional second clock interval. Assuming that a modulated signal as it appears in FIG. 12c is applied to the configuration described above, the signal at pin 218 results in the signal shown in FIG. 12d. The delayed modulated signal shown in Figure 12d is exactly the same as the modulated signal shown in Figure 12c delayed by two and a half first clock intervals.

The digital displacement technology of the multiplier in question has the inherent advantage for digital electronics that it is relatively drift-free and error-free. Furthermore, the time setting is carried out in a manner that is independent of the set signal. In other words, it does not depend on the frequency of the signal that is timed. The system shown in Fig. 9 allows a phase adjustment in the multiplication of two analog signals without the use of RC networks and the associated signal interference. If delta-minus-sigma modulation is used in the multiplication, the size of the shift registers used need not be unacceptably large, and a high degree of accuracy is nevertheless achieved.

In order to achieve a high degree of accuracy of the power measurement system according to the invention over a wide dynamic range, it is important that the celebration of the offset be eliminated from the active circuit elements. Misalignments, the size of which is sufficient to adversely affect the measuring accuracy, are usually found in cheap operational amplifiers. The term "voltage offset" is generally defined as the voltage difference between two inputs to an active circuit element, for example an operational amplifier, when the output is zero. There is a mismatch between the amplifier inputs and the measuring system according to the invention contains an offset compensation device which corrects such a mismatch.

Fig. 13 shows a novel offset compensation arrangement applied to a single amplifier. The basic theory of the offset compensation arrangement involves the use of a capacitor or other memory element which is connected to an input of the amplifier and then charged to a compensation voltage. Obviously, other equivalent arrangements instead of a capacitor can be used to store a voltage and to supply it to an amplifier input. Operational amplifiers often have more than two inputs and sometimes have one or more inputs that are specifically designed for offset compensation purposes. The invention works just as well in compensating for offset in amplifiers with additional inputs. Whichever input is intended to receive a compensation voltage with which a voltage offset is corrected, it will be this input to which the capacitor is connected. The arrangement also has devices with which the capacitor is charged to an equivalent voltage, which essentially cancels out the effect of the voltage offset at another amplifier input. For the sake of simplicity, only one amplifier 70 (FIG. 1) is shown in FIG. 13, although the offset compensation device according to the invention can also be used to correct a multiplicity of amplifiers in succession, as will be explained in more detail.

The amplifier offset compensation device, as it is applied to the amplifier 70, has an offset storage element, for example a capacitor Ci, which is connected to a first selected input 181 of the amplifier. A zeroing circuit 182, which is connected via switches to both the offset storage element and the second selected input 183 of amplifier 70, is also provided. The zeroing circuit 192 has a charge amplifier 184 which is connected to the second input of the amplifier 70 via a switch AI. The zeroing circuit further includes a temporary memory element, a capacitor 186, and a series of switches B, D and E that connect the capacitor 186 to a charge amplifier 184, as will be described. Additional switches Gi and Hi switch the charge amplifier 194 into a charging circuit that adjusts the voltage stored on capacitor Ci.

Line current signal Ia2 is provided to the inverting input of amplifier 70, which is ideally a virtual earth. Each voltage offset in amplifier 70 initially appears as a voltage at inverting input 183. When capacitor Q is charged, the voltage at inverting input 183 decreases until the virtual earth condition is reached. The difference between the compensation voltage VCOmp at Ci and the actual voltage offset of the amplifier 70 is referred to as the deviation voltage V deviation. It is V deviation. that appears at entrance 183. The purpose of the offset compensation device according to the invention is to reduce V deviation to a minimum.

The offset compensation device has control means for performing the functions listed in box 190. The control means essentially actuate the switching

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ter Al, B, D, E, Gl and Hl in order to generate a series of transfer and charging periods in succession. During an initial transfer period, switches Al, B and D are closed and switches E, Gl and Hl are open. When switch AI is closed, VA deviation is applied to the non-inverting input of charge amplifier 184, which is configured as a gain one amplifier. The switch B, which is closed during the transfer periods, provides a feedback connection between the output 192 of the charge amplifier 184 and the non-inverting input 226. A first connection 228 of the temporary storage capacitor 186 is also connected to the inverting input 226. In the closed state, the switch D connects a second connection 230 of the capacitor 186 to ground. During the transfer period, therefore, V deviation appears at amplifier output 192 and is stored in temporary storage capacitor 186, together with the voltage offset of charge amplifier 184 (V offset offset 184).

During a subsequent charging period, the control means 190 open the switches Al, B and D and close the switches E, Gl and Hl. This serves to isolate the second connection 230 of the capacitor 186 from ground and to the amplifier output 192 in a second feedback loop connect to. The result is that a voltage -V deviation appears at amplifier output 192. The internal offset of the charge amplifier 184 (V-offset-m.) Is determined by the same and opposite value of the component -V-offset. 184 extinguished, which is provided by the capacitor 186 to the output 192. Closing the switch Gl and opening the switch AI during the charging period also supplies the voltage VCOmp on the offset storage capacitor Cl to the non-inverting input of the charging amplifier 184. With -V deviation at the charging amplifier output 192 and VCOmp at its input (during the charging period) through impedance 224 and switch Hl a current -l deviation is established which adjusts VCOmp in the direction necessary to reduce V-deviation during the next transfer period.

14 shows the operation of the offset compensation device in the start-up mode. Suppose the voltage V-offset. 70 represents the voltage offset between the inputs of amplifier 70 and the charge on capacitor Ci (VComp) is initially zero, then V-deviation during the initial transfer period is V-offset. 70. During the following charging period, a voltage -V deviation appears at amplifier output 192. A current -l deviation is then supplied to capacitor 186 so that the value of Vcomp is increased. The voltage Vcomp on capacitor Ci serves to significantly reduce the offset error of amplifier 70 until the next transfer period. The values of resistor 224 and capacitor C1 are chosen to produce a current deviation that does not change the voltage on capacitor Ci too much during a single charge period. Capacitor Ci is therefore not charged to full offset voltage during some initial transfer and charge cycles. As VCOmp approaches (V offset offset 70), V deviation becomes progressively smaller. Finally, V-deviation approaches a stable minimum value that is sufficient to correct leakage currents and other temporary signals that are present in the circuit. At this point, misalignments are practically eliminated.

Subsequent transfer and charge periods can either follow immediately after previous transfer and charge periods, or separated by a time delay. In the preferred embodiment, where additional amplifiers are offset compensated using the same zeroing circuit 182, the transfer and load periods associated with any amplifier are separated by predetermined time intervals. 14 shows the next transfer period one

V deviation that is smaller as shown at 222. As above, VA deviation is first stored on capacitor 186 and then, during the subsequent charge period, appears at charge amplifier output 192 as "VA deviation". During this charge period, the current "-1 deviation" is added to the charge on capacitor Ci, so that the magnitude of VA deviation during the following Transfer period is further reduced. During subsequent cycles, VCOmp on capacitor Ci approaches the actual voltage offset of amplifier 70, so that V deviation is reduced to approximately zero.

The offset compensation system described above with respect to amplifier 70 can similarly compensate for the offset in a variety of amplifier elements. Figure 15 shows the preferred embodiment of the offset compensation system used to obtain offset compensation for five different amplifiers. The five amplifiers whose offset is to be compensated for by the compensation device of the measuring system are the following: current signal amplifier 70, current signal inverting amplifier 74, integration amplifier 46 of the first modulator, integration amplifier 108 for the power (watt) output amplifier and integration amplifier 180 for the apparent power (VARS) / Q output converter. Each of the amplifiers is similar to amplifier 70 discussed in connection with FIG. 13 in that they all have inverting virtual ground inputs to which a signal is applied. Each of these amplifiers is provided with corresponding offset memory elements, capacitors Ci to C5. The non-inverting inputs of the amplifiers are connected to the charge amplifier 184 of the zeroing circuit 182 via corresponding switches A1 to A5, as shown in FIG. 15. Switch pairs equivalent to Gl and Hl in FIG. 13, namely Gl to G5 and Hl to H5, connect the charge amplifier 184 to the corresponding offset storage capacitor of each amplifier.

A single zeroing circuit 182 stores the offset voltage and charge of the offset storage capacitor of each amplifier using the sequence described below. For the sake of simplicity, the control circuit for operating the various switches shown in Fig. 15 is omitted. A conventional controller of any suitable type can be used to control the switches according to the timing diagram illustrated in FIG. 16. The controller first closes switches Al, B and D during an initial transfer period for amplifier 70, then opens switches Al, D and B and closes switches E, Gl and Hl during a charging period. The controller then provides for further subsequent transfer and charging periods for each of the other amplifiers whose offset is to be compensated for. After the amplifier 70 charge period, the amplifier 74 transfer period begins, with the controller closing switches A2, D and B and then opening these switches and closing switches E, G2 and H2 during the following charging period. For amplifier 46, switches A3, B and D are closed during the transfer period and switches E, G3 and H3 are closed during the charging period. For amplifier 108, switches A4, B and D are closed during the transfer period and switches E, G4 and H4 are closed during the charging period. Finally, for amplifier 180, switches A5, B and D are closed during the transfer period and switches E, G5 and H5 are closed during the charging period.

After a transfer and charge period for an amplifier has ended, all switches associated with this switch, namely switches A, G and H, remain open. The charge stored on the offset storage capacitor in question remains until the control sequence provides for a new charging period associated with that capacitor. If a certain

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Loss of charge occurs, so deviations due to voltage offset for each of the amplifiers are significantly reduced. The operating frequency of the controller to open and close the switches associated with the offset compensation device can be determined in the design, it can be significantly slower than the clocks associated with the measurement system.

The disclosed offset compensation system can be used to correct deviations due to offset in any number of amplifier elements associated with a measurement system. A single zeroing circuit similar to circuit 182 can be sequentially connected to up to N amplifier elements and the associated memory elements during a sequence of transfer and load periods. Such an offset compensation system is economical and is ideally suited for use with CMOS integrated circuits, where offset deviations can cause problems. While the offset compensation system has been described in connection with a measurement system according to the invention, it can equally well be used with other types of power measurement circuits in which operational amplifiers are used. Such a measuring circuit can be, for example, any suitable arrangement with which analog signals representing current and voltage are multiplied, as well as any suitable converter or filter circuit with which an output signal is obtained from the product signal. If it is assumed that the measuring system uses up to N amplifier elements in its various components, the offset compensation system according to the invention can practically eliminate deviations due to offset in the manner described below.

The N amplifier elements each have a number of inputs. A first selected input in each such amplifier is the input for receiving a compensation voltage for correcting the voltage offset. N offset storage elements, for example capacitors, are also provided. One of the N offset memory elements is connected to the first selected input of each of the N amplifier elements. The offset storage elements receive compensation voltages which considerably reduce the offset deviation at another input of the amplifier element to which they are connected, this other input being referred to as the second selected input. Each difference between the compensation voltage on the offset storage element and the voltage offset of the amplifier element is a deviation voltage that appears at the second selected input of the amplifier element. A zeroing circuit, such as circuit 182, is also provided for the power measurement system. The zeroing circuit can be sequentially connected to each of the N amplifier elements and the offset memory element associated therewith. In the following description, the amplifier element to which the zeroing circuit is connected, including the associated memory element, is referred to as the selected amplifier element. In the same way as in the system described above, the zeroing circuit is first connected to the second input of the selected amplifier element during an intermittent transfer period. The zeroing circuit is then connected to the offset storage element associated with the selected amplifier element during the intermittent charge period following the transfer period. A control system then sequentially connects the zeroing circuit to the remaining one of the N amplifier elements to obtain transfer and load periods for each of the amplifier elements. The sequence is repeated continuously so that all amplifier elements are compensated for the offset and the offset deviations in the measuring system are essentially eliminated.

By using the described offset compensation device, the measuring system according to the present invention measures power with a high degree of accuracy over a wide dynamic range. The need for relatively complex calibrated or error-free amplifiers has been eliminated, so that the measuring system becomes relatively cheap. The system provides continuous, parallel displays of power both in real power and reactive power or Q. Since the modulator output from the modulator 30 is clocked precisely at the first clock intervals, it is possible to manipulate the signal with digital logic. A shift register can conveniently be used to introduce the time delay necessary to obtain a suitable phase shift for the measurement of reactive power and Q. By simply selecting the appropriate stages in the shift register, the delay of the modulated signal can be set so that the desired output is delivered (reactive power or Q, 50 or 60 Hz) / the invention thus eliminates the need for coordinated analog phase shifters to the desired voltage lag receive. Since the output of the modulator is connected to both a power and a reactive power. Q converters can be delivered, simultaneous readings can be obtained with just a single modulator. The system also provides digital outputs for each polarity of the power flow on the line. Maximum information is therefore created with a high degree of accuracy in an efficient and economical manner.

FIG. 17 shows part of an alternative embodiment of a modulator, which is constructed somewhat more simply than the modulator 30 shown in FIG. 2. In this embodiment, a capacitor 44 is connected between the summation node 36 and ground. The capacitor 44 serves as a modulator integrator. The inverting input of a comparator 50 is also connected to node 36, while the non-inverting input is connected to ground. The comparator 50 forms a control signal based on voltage changes at the node 36, which is coupled to a bistable circuit 52. Circuit 52 is used to control a pair of switches that provide a feedback signal to node 36, as will be explained.

FIG. 18 illustrates various of the signals generated with the modulator of FIG. 17. The input signal VI is represented in Fig. 18a. Of course, when measuring AC power, Vl is sinusoidal. It is assumed that switch 58 is initially closed and a negative reference current is applied to summing node 36 via resistor 40. The values of VI— and resistor 40 are chosen so that a current If is generated which is large relative to the input signal Iai.

Idiff therefore has a negative net value, with current being drawn from capacitor 44. Accordingly, the integrated differential voltage signal initially falls as shown in Fig. 18c.

The clock 56 emits a signal according to FIG. 18b. The bistable circuit 52 clocks on the leading edge of each upward pulse. At clock pulse a, the integrated differential signal according to FIG. 18c has not yet crossed the threshold of the comparator 50, and thus Q remains low and Q high, and the differential signal continues to integrate downwards. Since the difference signal is fed to the inverting input of comparator 50, the comparator output switches from low to high when the signal crosses the threshold. The control signal shown in FIG. 18d represents the output of the comparator 50. Accordingly, the bistable circuit 52 changes the state to the clock pulse b and Q goes from low to high. When Q goes high, Q goes low and switch 60 is closed5

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sen and switch 58 open. A positive reference signal is then fed to the summing node 36 so that the integrated Idiff grows until the next clock pulse at c. Between the clock pulses b and c, the integrated difference signal again crosses the level threshold of the comparator 50, so that the first control signal goes low. Q then goes low at the next clock pulse, so that the reference signal applied to the summing node 36 goes negative again. As Vl increases, the slope of the difference signal changes and its value falls until the level threshold is crossed again. Q remains low until a change in the first control signal for the clock pulse f is detected. Q then goes high, so that the reference signal is switched from negative to positive again.

The circuit described above and the corresponding method works as a delta-minus-sigma converter, whereby only the difference between the input and the reference signals is integrated and measured. The circuit always holds the integrated difference signal around the level threshold of the comparator 50. The Q output of the bistable circuit 52 is selected as the first output signal which has a medium level or an amplitude over time, which is proportional to the magnitude of VI.

FIG. 19 shows a modulator circuit like FIG. 17 which contains an alternative offset compensation system. In this embodiment, the comparator 50, which is an operational amplifier element, is equipped with compensation devices which practically eliminate any offset deviation that results from a voltage offset that may exist between the amplifier inputs 306 and 308. As described above, a voltage offset is generally defined as the voltage required between the inputs of an amplifier to produce zero output. Ideally, the voltage offset is zero, but an offset of unknown value is usually present in most operational amplifiers that are actually available. According to the invention, a first memory element, for example a capacitor 302, is connected to one of the amplifier inputs, and an offset voltage substantially equal to the voltage offset of the amplifier is stored in the memory element in order to compensate for the voltage offset. In the example shown in FIG. 19, capacitor 302 is arranged in the electrical path between summing node 36 and inverting amplifier input 306. It should be noted that capacitor 302, like capacitor 44 and the other memory elements used in the embodiments described later, represent one type of memory element that can be used and that other types of circuit elements, such as registers with D / A converters and the like could be used for the various memory elements of the invention.

The offset compensation system also has a feedback loop 300 that is intermittently connected around amplifier 50, between inverting input 306 and the amplifier output, via switch C. When switch C is closed, the voltage offset appears at a low impedance am Input 306. To store the voltage produced by the feedback loop on capacitor 302, switches A and B are provided to disconnect one end of the capacitor from summing node 36 and connect it to ground 305.

The means for controlling the offset compensation system shown in Fig. 19 is clock 56, and Fig. 20 illustrates the control function. The bistable circuit 52 clocks on the leading edge of each clock cycle, as indicated by arrows 312. Each pulse going up represents a clock pulse. Just when the clock signal begins to go low to high, switches B and C are off and switch A is on, which means that the feedback loop around amplifier 50 is open and capacitor 302 is connected to summing node 36. As soon as the clock pulse begins, switches B and C turn on and switch A turns off, closing the feedback loop around the amplifier and connecting one terminal of capacitor 302 to ground. During this period, referred to as the zeroing period, the voltage offset 4 V offset of amplifier 50 appears at input 306. Because capacitor 302 is connected between input 306 and ground, the voltage + V offset is stored on the capacitor. During the last half of each clock cycle, called the measurement period, switches B and C turn off and switch A turns on. If the non-inverting input 308 is connected to ground, the deviation at the inverting input 306 is the negative value of the voltage offset -V offset. Accordingly, the signal that is compared to the level threshold by comparator 50 when A is closed and B and C are open is the voltage at summing node 36, the integrated difference signal plus + V offset plus - V offset. The voltage offset of the comparator 50 is thus canceled and the deviation that it would otherwise produce in the threshold measurement is practically eliminated.

Another embodiment of a modulator using an offset compensation system is shown in FIG. 21. In this embodiment, the measuring device 298 has two amplifier belts 328 and 336, which serve as comparators and which are alternatively connected between summation node 36 and bistable circuit 52. The first amplifier 328 is provided with a switchable feedback loop 324 which connects the output 330 to the inverting input 326 via switch D. A first storage element in the form of a capacitor 316 is connected in the electrical path between summing node 36 and inverting input 320 via switch E. A path via switch F is provided between a connection 318 of the capacitor 316 and ground. The second amplifier element 336 also has a switchable feedback loop 332, which is connected between output 338 and inverting input 334 via switch G, and a storage element, such as capacitor 320,

lies in the electrical path between the inverting input 334 and the summation node 36, specifically via switch H. A path between a connection 322 of the capacitor 320 and ground is provided by switch J.

The embodiment of FIG. 21 is designed so that two parallel offset compensated comparator circuits are formed to measure the integrated difference signal at summing node 36. When switches E and K are closed, first amplifier element 328 provides the first control signal to bistable circuit 52, and when switches H and L are closed, second amplifier element 336 supplies the first control signal to bistable circuit 52.

By closing switches E, G, J and K and opening switches D, F, H and L, the first amplifier element 328 is in a measurement mode, the control signal being supplied to the bistable circuit 52 and the second amplifier element 336 being located in a zeroing mode in which the voltage offset of amplifier element 336 is stored on capacitor 320. The storage of V-offset on the capacitors 316 and 320 is realized in exactly the same way as with the amplifier element 50 and capacitor 302 in the embodiment according to FIG. 19. By reversing all switches, that is to say closing the switches D, F, H and L and opening switches E, G, J and K, amplifier 328 comes into the zeroing mode and amplifier 336 into measuring mode, the integrated difference signal at summing node 36 being supplied to inverting input 334 via capacitor 320, with the voltage offset of amplifier 336 is compensated for and an error-free first control signal

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gnal is supplied to the D input of the bistable circuit 52.

An advantage of the embodiment shown in FIG. 21 over that shown in FIG. 19 is that an offset-compensated amplifier is always available in measurement mode. Furthermore, the switching between the measuring and zero mode takes place in the embodiment according to FIG. 19 with the clock frequency of the clock 56. If the interrogation frequency, as determined by the frequency of the clock 56, is sufficiently high, the amplifier elements are as Comparators are not able to stabilize after each zeroing period and errors are introduced. The embodiment of FIG. 21, in which conventional control logic is used to operate switches D, E, F, G, H, J and L, represented by element 340, may be operated at a frequency different from that of clock 56 differs. For example, a conventional frequency divider can be used to reduce the frequency of the control operations.

To ensure that in the embodiment of FIG. 21 there is adequate time for the amplifiers to stabilize after each zeroing period, the control logic 340, which acts as a control device for operating the switches D, E, F, G, H , J, K and L is used to provide the measurement period for each amplifier element in order to provide time for stabilization. Fig. 22 shows the timing diagram for the operation of switches D, E, F, G, H, J, K and L by the control logic 340. The switches K and L, which the outputs of the first and second amplifier element with the connect bistable circuit 52 are operated out of phase with each other. Switch K is half the time on and half the time off, and switch L is off when the switch K is on, and vice versa. In addition to controlling the switches that connect the amplifiers to the bistable circuit 52, the control logic 340 also controls the switches that determine the zeroing and measurement periods of the amplifiers 328 and 336. Switches D, E and F serve to close a feedback loop around amplifier 328 and to connect one terminal 318 of capacitor 316 to ground, in exactly the same way as in the embodiment of FIG. 19. Switches G, H and J perform the same function for the amplifier 336. As can be seen from FIG. 22, the amplifier zero and measurement periods of each amplifier element are not of the same duration. For example, the zeroing period for first amplifier 328 begins when switch K turns off and ends before switch K turns on again. Similarly, the zeroing period begins for the second amplifier 336,

when switch L turns off and ends before switch L turns on again. Accordingly, the zeroing period for each amplifier is shorter than the measurement period, namely by a predetermined interval. This is done to give the amplifiers time to stabilize before they are connected to the bistable circuit.

It should be noted that, in addition to allowing the control logic to allow extra time for amplifier stabilization before connecting the first or second amplifier to the bistable circuit, the control logic is inherently slower than clock 56. As can be seen from FIG. 22, the clock signal, which is not drawn to scale, operates at a considerably higher frequency than any of the switches in FIG. 21. The control logic 340 preferably has a frequency divider for this purpose. The embodiment shown in Fig. 21 can thus use a relatively high frequency clock, for example 10 kHz, to obtain frequent polling and relatively high resolution, while zero and offset compensation of the amplifier elements are done at a frequency low enough to pass through errors to minimize slow response of the amplifiers.

The method according to the invention, which is carried out in the embodiment according to FIG. 21, has an additional step within the measuring step for switching between the two amplifier elements 328 and 336. The compensation step consists in measuring with the first amplifier element and the second amplifier element is zeroed, and then measured with the second amplifier element and the first amplifier element is zeroed, in a continuous cycle, such that at least one of the offset-compensated amplifier elements is connected to the summation node at all times. In the preferred embodiment of the method, the zeroing period and the measuring period are different, and preferably slower than the clock intervals. Furthermore, the zeroing periods are shorter than the measurement periods for each amplifier element, according to the timing diagram in Fig. 22. The measurement period of one amplifier element begins before the end of the measurement period of the other amplifier element, such that any errors due to slow comparator response of the first of the amplifier elements when switched for the first time from zeroing to measuring.

Operation of the embodiment of FIG. 21 provides the results illustrated in FIG. 18. Assuming VI runs as shown in FIG. 18a, the integrated difference signal that appears at the summation node 36 has the form shown in FIG. 18c. Both the first control signal according to FIG. 18d and the Q output according to FIG. 18e are not affected by the intermittent operation and the cyclical zero and measurement periods of the amplifiers 328 and 336. The embodiment according to FIG. 21 ensures higher accuracy at higher clock frequencies, but is otherwise functionally identical to the embodiment according to FIG. 19.

The modulator 30 used in the measurement system of Fig. 1 can be used in other applications where it is necessary to obtain modulated output signals which indicate the polarity of the input signal. FIG. 23 shows an alternative embodiment of a modulator that supplies such output signals. The input signal Iai is fed to a summing node 36 via a resistor 38. One of the two reference signals, which preferably have the same size and opposite polarity, is also applied to the summation node via resistor 40. The reference voltages VI— and VI + are connected to the summation node via two switches 58 and 60, respectively, which are controlled by the modulator output. Current differences between input current Iai and feedback current If at node 36 are fed to an integrator that provides a rising or falling sawtooth voltage. The integrated signal is then compared to a comparator 50 with a level threshold that provides a control signal that indicates whether the output of the integrator is above or below the level threshold. The output of the comparator 50 is fed to a bistable circuit, for example a flip-flop 52.

The bistable circuit changes its state only at predetermined clock intervals, as determined by clock 56. When the integrated signal crosses the level threshold of the comparator 50, the output of the bistable circuit 52 reverses its state on the next clock pulse. The Q output of bistable circuit 52, which is the first modulated signal of the invention, controls switch 60, which connects positive reference voltage VI + to summing node 36. The Q output, which is always the inverse of the Q output, actuates switch 58 so that negative reference voltage VI— is connected to summing node 36. The switches 58 and 60 are always actuated alternately, which means that one or the other of the reference signals is always supplied to the summing node 36.

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The Q output of the bistable circuit 52 is connected to the D input of a second bistable circuit 53 and both receive clock signals from the same clock 56. Because of gate delays, changes in the Q output of the bistable circuit 53 always follow changes in the Q output of the bistable circuit 52 with a delay of one clock pulse. An AND gate 350 is also provided to receive the Q outputs from both bistable circuits 52 and 53 and a clock signal from clock 56. The AND gate serves as a means for outputting a first digital signal which is proportional to the magnitude of a polarity of the Input signal.

24 illustrates the operation of the circuit elements described above. For illustration, it should be assumed that the voltage curve on node 32, which is supplied to this modulator according to the alternative embodiment, has the form shown in FIG. 24 a, the signal is first converted into a first modulated signal at the Q output of the bistable circuit 52 converted in the manner described above. Furthermore, it is assumed that the Q output of the bistable circuit 52 has the course shown in FIG. 24d. The output of clock 56 is shown by the voltage curve in FIG. 24b. The output of the second bistable circuit 53 is referred to as “delayed Q” and is illustrated by the voltage curve in FIG. 24e. Delayed Q is essentially equal to Q, but is delayed in time by one clock interval. The invention requires that Q, delayed Q and a clock signal be combined in an AND gate 350 (see FIG. 23).

For actually executable components, it is preferable to arrange an inverter 57 between clock 56 and AND gate 350, even if this is not necessary for idealized circuits in which component delays are not present. The inverter 57 inverts the clock signal to obtain an inverted clock signal as shown in FIG. 24c. The reason for providing an inverted clock signal to the AND gate is that propagation delays in bistable circuits 52 and 53 tend to cause their outputs to lag slightly behind the output of clock 56, so that short, simultaneous "high conditions" appear in all three signals at the wrong time. If the clock is not inverted, there is therefore an extra peak output from AND gate 350 which would represent an error pulse. For this reason, the inverter 57 is provided in FIG. 23. The resulting output voltage curve from AND gate 350 is shown in Fig. 24f.

The voltage waveform in FIG. 24f is essentially a digital representation of the amount by which the time in which Q is high exceeds the time in which Q is low. In the example according to FIG. 24, the voltage curve 24f contains only two pulses which are generated in succession and which appear on the right side of the illustration. Roughly speaking, these two pulses coincide with the area in which the input Fig. 24a is the most negative. Preferably, the frequency of the clock significantly exceeds the variations of the analog input signal in order to obtain higher resolutions than shown in FIG. 24. However, the working principle is exactly the same. In principle, the combination delivers a delayed

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modulated signal with the original modulated signal at an AND gate, an output signal that goes high only when Q remains high for at least two consecutive clock pulses. The clock signal ensures that the AND gate output is a pulse train, with pulses at intervals of not less than the clock intervals of the clock signal. In the example just described, the AND gate only emits pulses when all the signals applied are high. If Q is low for two or more consecutive clock pulses, it has no effect on the output of AND gate 350 since only high inputs are measured. The output of the AND gate is therefore a representation of the size of only one polarity of the input signal. The output is therefore effectively a simply rectified signal, represented digitally.

In order to obtain a digital output proportional to the other polarity of the input voltage curve, the modulator according to the alternative embodiment uses the Q outputs of the bistable circuits 52 and 53 as first and second inverted modulated signals. Assuming the same input signal and clocks as in Fig. 24, Q has a shape as shown in Fig. 24g. The bistable circuit 53 supplies a delayed Q signal as shown in Fig. 24h. Both signals are fed to a second AND gate 352 (Fig. 23) along with the inverted clock signal shown in Fig. 24c. The output of the second AND gate 352 is shown in the voltage profile in FIG. 24i and is referred to as the second digital signal. The second AND gate serves as a means for delivering a second digital signal containing pulses proportional to the amount of time that one level of the first inverted modulated signal exceeds the other level. If all three inputs of the AND gate are high, pulses are produced at intervals of not less than the clock intervals of clock 120. In the present example, the voltage curve 24i represents the component of positive polarity of the input signal. Obviously, the locations of the pulses roughly correspond to the areas where the input signal Fig. 24a is high. 24i forms a digital representation of the size of the positive half-wave components of the input signal.

FIG. 23 also shows that the invention can be used further to produce a digital signal proportional to the size of the full voltage curve of the input signal. This is accomplished by providing the first digital signal output of AND gate 350 and the second digital signal output of AND gate 352 to an OR gate 351, which serves as a gate device with which the digital signals are combined to produce a digital sum output signal as shown in Fig. 24j. 24j is proportional to the size of the full input signal including both polarities, which is referred to here as the “absolute size”. The outputs of AND gates 350 and 352 are connected to up and down inputs of an up / down counter 354 so that the number of positive and negative pulses over any selected time interval can be compared.

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Claims (49)

672 847 2nd PATENT CLAIMS 1. A method for measuring the electrical power carried on a line (10), characterized by: Monitoring current and voltage signals on the line and producing a first analog signal (Iai) proportional to one of the current and voltage signals and producing a second analog signal (Ia2) proportional to the other of the current and voltage signals, modulating the first analog signal to a first to produce a modulated signal which can be changed between two values at predetermined cycle times, the first modulated signal having a temporal mean value which is proportional to the first analog signal (Iai), and multiplying the first modulated signal by the second analog signal (Ia2), to produce a product signal (88, Ip) that is proportional to the power carried on the line. 2. The method according to claim 1, characterized in that the modulation step includes generating a modulator feedback signal (If) which changes its value in response to changes in the first modulated signal and which over time compensates for the first analog signal (IAi) that instantaneous differences measured between the modulator feedback signal (If) and the first analog signal (Iai) and that a control signal, which is characterized by these differences, is supplied to a bistable circuit (52) which outputs the first modulated signal. 3. The method according to claim 2, characterized in that the modulation step includes supplying the first analog signal (Iai) and the modulator feedback signal (If) to a summation node (36), and that the measuring step comprises the steps of integrating a signal (Idiff) at the summation node which is the difference between the first analog signal (Iai) and the modulator feedback signal (If), then comparing the integrated value generated by the integration step with a predetermined modulator level threshold. 4. The method according to claim 1, characterized in that the product signal (Ip) is converted to a first output signal (92), which indicates the power present on the line, wherein the conversion step is the generation of the first output signal (92) by a first bistable circuit (118), the output of which changes between two levels at predetermined converter clock times (120), that the product signal is supplied to a summing node (96), that a converter feedback signal (I2) from several reference sources in response to the level of the first output signal ( 92) is supplied to the summation node (96), the converter feedback signal (I2) compensating the product signal (Ip) over time and any instantaneous difference between the product signal (Ip) and the converter feedback signal (I2) being a converter difference signal that the converter difference signal to Form an integrated converter difference signal (112) integrated and the int integrated converter difference signal (112) is compared with a first level threshold (114) and that the first bistable circuit (118) is caused to use the first output signal (92) as one of two levels, depending on the level of the integrated converter difference signal (112) relative to the first level threshold (114) at each of the converter clock times. 5. The method according to claim 4, characterized in that the product signal (Ip) predominantly has a first polarity if the power on the line has a first polarity, in which the power flows predominantly in a first direction, that the conversion step comprises the steps of Forming the converter feedback signal (I2) from a first reference source (98) having a polarity opposite to the first polarity includes using the first reference source (98) to produce the converter feedback signal (I2) whenever the first output signal (92) does Level to drive the integrated converter difference signal (112) towards above the first level threshold, that a second reference source (102) is used to produce the converter feedback signal (I2) when the first output signal (92) has the other of the two levels, wherein the integrated converter difference signal (112) is caused to cause the first P to cross the control threshold in the other direction such that the integrated converter difference signal (112) is held in the vicinity of the first level threshold (114) while the power is on the line of the first polarity. 6. The method according to claim 5, characterized in that the product signal (Ip) predominantly has a second polarity opposite to the first if the power on the line has a second polarity in which the power flows predominantly in a second direction opposite to the first, that the conversion step further includes the steps of comparing the integrated converter difference signal (112) with a second level threshold (140) that is different from the first level threshold (114), that a second output signal (144) by a second bistable circuit (142 ) which, depending on the level of the integrated converter difference signal (112) relative to the second level threshold (140), has one of two levels for each of the converter clock pulses that is provided, the converter feedback signal. (I2) with a third reference source (148), if the power on the line has the second polarity, that the third reference source (148) always has an opposite polarity to the second polarity when the second output signal (144) is the one Level at which the integrated converter difference signal (112) is caused to cross the second level threshold (140) in a direction that the converter feedback signal (I2) is formed by a fourth reference source when the second output signal (144) the other of the two Level, causing the integrated converter difference signal (112) to cross the second level threshold in the other direction such that the integrated converter difference signal (112) while the line power is of the second polarity, in the vicinity of the second level threshold (140) is held. 7. The method according to claim 6, characterized in that the second reference source (102) is used as the fourth reference source. 8. The method according to claim 1, characterized in that a third output signal is formed, the size of which is the same and whose polarity is opposite to the second analog signal (Ia2) and that in the multiplication step the second and third analog signals are keyed as a function of the first modulated signal. 9. The method according to claim 1, characterized in that a number of N amplifier elements (46, 70, 74, 108, 180) are used, each of which has a plurality of inputs to carry out at least one of the steps of the method, that in the method additionally it is provided to compensate the N-amplifier elements with respect to offset, in order to eliminate deviations by voltage offset between selected inputs of each of the N-amplifier elements, that each of the amplifier elements with a first selected input (18IT in each case to an offset memory element (Ci, C2, C3, C4, C5) on which a compensation voltage (VCOmp) is stored to substantially correct any offset errors at a second selected input (183) of the amplifier element that any difference between the compensation voltage on the offset storage element and the Voltage offset of the amplifier element is an offset error voltage (VAbwe is) that the 5 10th 15 20th 25th 30th 35 40 45 50 55 60 65 3rd 672 847 Offset compensation steps connect a sequential coupling of a matching circuit (182) to each of the N amplifier elements and the associated offset memory element in order to compensate each selected amplifier element in the sequence in the offset, whereby first the matching circuit (182) during an intermittent Transfer period is coupled to the second input of the selected amplifier element in order to determine the offset error voltage that during an intermittent charging period following the transfer period, the matching circuit (182) to the offset memory element, which is connected to the first input of the selected amplifier element is coupled to adjust the charge on the offset storage element during the charging period such that the offset error voltage is reduced during the next transfer period of the selected amplifier element, and that the steps of the transfer and charging period for each of the N amplifier elements take place sequentially in a continuous cycle. 10. The method according to claim 9, characterized in that the adjustment circuit (182) has a charge amplifier (184) and a temporary memory element (186) with first and second connections and that the offset compensation includes the following steps: connecting an input of the charge amplifier (184) to the second input of the selected amplifier element, connecting the first connection of the temporary storage element (186) to a feedback path between an input (226) and the output (192) of the charge amplifier (184), connecting the second connection of the temporary A common ground memory element during the transfer period such that the offset error voltage is transferred to the temporary memory element (186) using the charge amplifier (184) and the second terminal is decoupled from the common ground and the second terminal is connected to the output the charge amplifier (184) during the following Charging period, so that a voltage which is proportional to the offset error voltage appears at the output (192) of the charge amplifier (184) during the charging period. 11. The method according to claim 10, characterized in that the offset compensation further includes the coupling of the output (192) of the charge amplifier (184) by an impedance to the offset memory element (Ci, C2, C3, C4, C5) during each charging period, such that a current proportional to the offset error voltage is supplied to the offset memory element (Ci, C2, C3, C4, C5), thereby adjusting the voltage on the offset memory element so that the offset error voltage of the selected amplifier element is reduced during the next transfer period. 12. The method according to claim 9, characterized in that the offset compensation of the N amplifier elements (40, 70, 74, 108, 180), each having a plurality of inputs, substantially eliminates the deviations due to voltage offset between selected N inputs of each of the amplifier elements by connecting each of the amplifier elements with a first input (181) to a memory element (Cr, C2, C3, C4, C5) on which a compensation voltage is stored by the method steps, in order to essentially eliminate any offset errors at a second input ( 183) of the amplifier element, each difference between the compensation voltage on the memory element and the voltage offset of the amplifier element being an offset error voltage appearing at the second input (183), that by sequentially coupling the adjustment circuit (182) to each of the N amplifier elements and on select the associated storage element each th amplifier element is sequentially compensated for offset, including the following steps: coupling the trim circuit (182) to the second input of the selected amplifier element during an intermittent transfer period to determine the offset error voltage, coupling the trim circuit during an intermittent charge period, which follows the transfer period to the memory element connected to the first input of the selected amplifier element to adjust the charge on the memory element during the charging period so that the offset error voltage is reduced during the next transfer period of the selected amplifier element. 13. Measuring device for performing the method according to claim 1, characterized by: Means for monitoring current and voltage signals on the line (10), including first signal means (16) for generating a first analog signal (Iai) proportional to one of the current and voltage signals and second signal means (18) for generating a second analog signal OU2) -tionl the other of the current and voltage signals; a modulator (30) for converting the first analog signal (Iai) into a first modulated signal which can be changed between two levels at predetermined first cycle times; wherein the first modulated signal has a mean time value which is proportional to the first analog signal (Iai); and a multiplier arrangement (82, 86) responsive to the first modulated signal and the second analog signal to produce a product signal (88) which is of a magnitude proportional to the power carried on the line. 14. Measuring device according to claim 13, characterized in that the modulator (30) comprises a bistable circuit (52) which can be changed by the cycle times and which emits the first modulated signal that further modulator feedback means (58, 60, 40) are present, to generate a modulator feedback signal (If) which changes its value depending on the first modulated signal and which compensates the first analog signal (Iai) over time and means (44, 46, 50) for measuring instantaneous differences between the modulator feedback signal (If) and the first analog signal (Iai) and for generating a control signal characterizing this difference, the control signal controlling the bistable circuit (52). 15. Measuring device according to claim 14, characterized in that the modulator (30) has a modulator ummaations node (36), in which the first analog signal (Iai) and the modulator feedback signal (If) are combined to generate a modulator difference signal (Idiff) that the modulator measuring means include an integrator (44, 46) for integrating the modulator difference signal and a comparator (50) for comparing the integrated modulator difference signal with a predetermined modulator level threshold. 16. Measuring device according to claim 13, characterized in that conversion means (90) for converting the product signal (88) into a first output signal (92), which indicates the power transported on the line, are present, the conversion means (90) being the first Output signal (92) by a first bistable circuit (118), the output of which can be changed between two levels at predetermined converter cycle times (120), that the converter means (90) means (95) for feeding the product signal (Ip) to a summation node (96 ) and converter feedback means (100, 104, 146) for supplying a converter feedback signal (I2) to the summing node (96), the latter compensating the product signal over time, the converter feedback signal (I2) being dependent on the level of the first output signal (92) , and each instantaneous difference between the product signal (Ip) and the converter feedback signal (I2) a converter difference signal, which is at S ummationsnoten (96) appears, is that converter measuring means (108, 5 10th 15 20th 25th 30th 35 40 45 50 55 60 65 672 847 4th 110, 114, 140) for integrating the converter difference signal and for comparing the integrated converter difference signal with a first converter threshold value level, wherein a first output (116) of the converter measuring means is connected to the first bistable circuit (118) and that the first output signal (92 ), depending on the level of the integrated converter difference signal relative to the first converter level threshold, is set to one of two levels at each converter clock time (120) so that the level of the first output signal averaged over time is proportional to the product signal (Ip) and that transported on the line Performance is. 17. Measuring device according to claim 13, characterized in that the first analog signal (Iai) is proportional to the voltage signal and the second analog signal (Ia2) is proportional to the current signal. 18. Measuring device according to claim 16, characterized in that the product signal (lp) predominantly has a first polarity if power on the line has a first polarity, in which the power flow is predominantly in a first direction, that the converter feedback means (100, 104 , 146) have a first reference source (98) which is used when the power on the line has this first polarity, the first reference source (98) having a polarity opposite to this first polarity and having a signal size sufficient to achieve the Compensate product signal (Ip) and wherein furthermore the first reference source (98) is used intermittently to generate the converter feedback signal (fc) when the first output signal (92) has the level that the integrated converter difference signal (112) in the direction above the first Converter threshold level drives and that a second reference source (102) is available to generate of the converter feedback signal (I2) is used when the first output signal (92) is at the other of the two levels, causing the integrated converter difference signal (112) to cross the first converter level threshold in the other direction to the integrated converter difference signal (112 ) while keeping the power on the line from the first polarity close to the first converter level threshold. 19. Measuring device according to claim 18, characterized in that first digital probe means (150) for receiving the first output signal (92) and for generating a first pulse train with a pulse rate proportional to the first output signal (92) are present. 20. Measuring device according to claim 18, characterized in that the product signal (Ip) predominantly has a second polarity opposite to the first if the power on the line has a second polarity in which the power flow predominantly in a second direction opposite to the first direction is that the converter means (90) have a second bistable circuit (142) and means (140) for comparing the integrated converter difference signal (112) with a second converter threshold level different from the first, that the output of the comparison means (140) with the second bistable Circuit (142) is connected, which depends on the level of the integrated converter difference signal (112) relative to the second converter threshold level produces a second output signal (144) at one of two levels that the converter feedback means (100, 104, 146) has a third reference source (148) which is used when the power of the line is of the second polarity wherein the third reference source (148) has a polarity opposite to the second polarity and furthermore the third reference source (148) is used intermittently to generate the converter feedback signal (I2) when the second output signal (144) has the level which the integrated converter difference signal (112) drives above the second converter threshold level and that a fourth reference source (102) is present which is used to generate the converter feedback signal (I2) when the second output signal is at the other of the two levels the integrated converter difference signal (112) being caused to cause the second Cross converter level threshold in the other direction to hold the integrated converter difference signal (112) near the second converter level threshold while the power is on the line of the second polarity. 21. Measuring device according to claim 20, characterized in that the second (102) and fourth reference source are identical. 22. Measuring device according to claim 21, characterized in that the second (102) and fourth reference source are both connected to a common ground for the measuring device and that the first output signal (92) proportional to the temporal power flow on the line with the first polarity and that second output signal (144) is proportional to the temporal power flow on the line with the second polarity. 23. Measuring device according to claim 20, characterized in that second digital probe means (152) for receiving the second output signal (144) and for delivering a second pulse train with a pulse rate proportional to the second output signal (144) are present. 24. Measuring device according to claim 19 and 23, characterized in that a counter (154) for recording the first and second pulse trains and for counting the pulses contained therein for determining the power flow on the line is present. 25. Measuring device according to claim 13, characterized in that the monitoring means comprise third signal means (74) for generating a third analog signal, which has the same size but a polarity opposite to the second signal (Ia2), and that the multiplier comprises scanning means (82, 86) for alternately switching the second analog signal and the third analog signal depending on the first modulated signal in order to generate the product signal (88, Ip). 26. Measuring device according to claim 13, characterized in that phase shifting means (160) are provided for setting the phase relationship between the first modulated signal and the second analog signal, so that the product signal is a power value of the power carried on the line (10) with a selected one Phase relationship is proportional. 27. Measuring device according to claim 26, characterized in that the phase shifting means (160) comprises a time delay means either for delaying the first modulated signal or the second analog signal by a selected time interval. 28. Measuring device according to claim 13, characterized in that a shift register (160) is provided, to which the first modulated signal is supplied and which emits a first modulated signal delayed by a selected interval and that a multiplier (164) is present. 29. Measuring device according to claims 25 and 28, characterized in that the multiplier (164) comprises a first multiplier (166) which responds to the delayed first modulated signal and to the second analog signal, the product signal being a second product signal, which identifies the selected phase relationship of the power value, and that there is a second multiplier (168) responsive to the first modulated signal and the third analog signal to produce a third product signal indicative of the reactive power carried on the line. 30. Measuring device according to claim 16, characterized in that at least in one monitoring means, modulation means and converter means a number of N amplifiers. 5 10th 15 20th 25th 30th 35 40 45 50 55 60 65 5 672 847 ker elements (46, 70, 74, 108, 180) are included, all of which have multiple inputs, that offset compensation means are present in order to essentially eliminate deviations by voltage offset between selected inputs of each of the N amplifier elements, that the offset compensation means N offset storage elements (Ci, C2, C3, C4, C5), each of which is coupled to a first input (181) of each of the amplifier elements to obtain a compensation voltage (Vcomp) which is essentially the offset error at a second input (183) of each of the amplifier elements, whereby any difference between the compensation voltage and the voltage offset of the corresponding amplifier element is an offset error voltage (V deviation) present at the second input, in that a matching circuit (182) is provided which is sequential with each of the N amplifier elements and the offset memory element (Ci , C2, C3, C4, Cj) can be coupled such that each of the N amplifier elements to compensate for the offset is sequentially the selected amplifier element, the trimming circuit being first connected to the second input (183) of the selected amplifier element during an intermittent transfer period to store the error voltage, and the trimming circuit is then connected to the first input (181) of the selected amplifier element in order to transfer the charge following the transfer period to the assigned offset offset storage element (Ci) during an intermittent charging period and that the offset compensation means comprise means (190) with which the Transfer and loading period for each of the N amplifier elements for substantially eliminating the offset errors can be generated sequentially. 31. Measuring device according to claim 30, characterized in that the adjustment circuit (182) comprises a charging amplifier (184) and a temporary storage element (186) which is connected to the charging amplifier and means (Gì, G2, G3, G4, G5), to transfer the offset error voltage during the transfer period from the second input (183) of the selected amplifier element (46, 70, 74, 108, 180) through the charge amplifier (184) to the temporary memory element (186). 32. Measuring device according to claim 31, characterized in that the offset compensation means contain coupling means (B, D, E) with which the temporary storage element (186) during the charging period for transferring the offset error voltage between a first input (226) of the charging amplifier (184) and a common ground and can be coupled between the first input (226) and an output (192) of the charge amplifier (184) during the transfer period, the output (192) of the charge amplifier (184) during the charging period being one of the deviation voltage of the selected amplifier element ( 70) has proportional voltage. 33. Measuring device according to claim 32, characterized in that the offset compensation means contain further coupling means (224, Hi) to the output (192) of the charge amplifier (184) during the charging period with the offset memory element (Ci) that with the selected amplifier element ( 70) is coupled such that a current which is proportional to the offset error voltage of the selected amplifier element flows to the first offset memory element (Ci), in order in this way to adjust the voltage on the offset memory element in a direction which tes the offset error voltage of the selected amplifier element (70) reduced during the next transfer period. 34. Measuring device according to claim 33, characterized in that the temporary storage element (186) has first (228) and second (230) connections, that the first connection of the temporary storage element (186) with an input (226) of the charging amplifier (184) and the second terminal is connected to the common ground via the coupling means (D) during each transfer period, in order to transmit a voltage, which characterizes the offset error voltage, to the temporary storage element (186) and that further coupling means (D, Hi) are mentioned Coupling means (Ai, Gì) are present to separate the second connection (230) from the common ground and to connect it to the output (192) of the charge amplifier (184) during each subsequent charging period, so that at the output (192) of the charge amplifier (184) there is a voltage proportional to the offset error voltage of the selected amplifier element. 35.Modulator for a measuring device according to claim 13, for converting the first analog signal (Iai) into a first modulated signal which can be changed between two levels at predetermined cycle times, the first modulated signal having an average time value which is proportional to the first analog signal ( Iai), characterized in that means (38) for supplying the first analog signal (Iai) and feedback means (58, 60) for supplying a feedback signal (If) which consists of at least two different reference signals (Vj_, Vi +) with predetermined sizes is selected, at a summation node (36) at which the difference between the first analog signal (Iai) and the feedback signal (If) is a difference signal, there are measuring means (44, 50) for integrating the difference signal and for determining, When the integrated differential signal reaches a level threshold, the measuring means include an amplifier element (50) and offset compensation ion means (56, 302, A, B, C) to substantially eliminate any offset error resulting from a voltage offset that exists between the amplifier inputs (306, 308) of the amplifier element (50) that the offset compensation means is a first Memory element (302), which is connected to the one amplifier input (306), and other means (56, A, B, C) for transferring the offset voltage to the first memory element (302) for compensating for the voltage offset, comprise a clock (56 ) for generating clock pulses at predetermined clock intervals and a bistable circuit (52) which is responsive to the measuring means and the clock pulses, the latter generating the first modulated signal (34) which can be changed between first and second levels with each clock pulse, depending on the fact that the integrated difference signal has exceeded a level threshold during a clock interval and that the feedback means (58, 60) on the bistabi respond to the circuit (52) such that one reference signal is provided to the summing node (36) when the first modulated signal is at the first level and the other reference signal is provided to the summing node when the first modulated signal is at the second level The mean value of the reference signals over time compensates for the first analog signal at the summation node. 36. Modulator according to claim 35, characterized in that the reference signals (Vi_, Vi +) have essentially the same size and an opposite polarity. 37. Modulator according to claim 35, characterized in that the measuring means (44, 50) have a second memory element (44) which is connected between the summation node (36) and a common ground and that the second memory element is part of a passive integrator for Integrating the difference signal forms, the voltage at the summation node being the integrated difference signal. 38. Modulator according to claim 35, characterized in that the amplifier element (50) is a comparator for determining when the inverting input (306) on the latter has reached a level threshold, that the inverting input (306) of the amplifier element with the summation node ( 36) is electrically connectable and the output (310) is connected to the bistable circuit (52), the amplifier element (50) emitting a first control signal, which is high when in FIG 10th 15 20th 25th 30th 35 40 45 50 55 60 65 672 847 6 tegrated difference signal is above the level threshold and is low when the integrated difference signal is below the level threshold. 39. Modulator according to claim 38, characterized in that the first memory element (302) lies in the electrical path between the summation node (36) and the inverting input (306) of the amplifier element (50), and the non-inverting input (308) with the Common ground is connected that the offset compensation means (56, 302, A, B, C) include a feedback loop around the amplifier element (50) between the inverting input (306) of the amplifier element (50) and its output (310), which during a intermittent matching period is switched in such a way that a voltage offset with low impedance appears at the inverting input (306), a connection of the first memory element (302) being separated from the summation node (36) and to the common one simultaneously with the offset compensation means (A, B) Ground is switched to store the voltage offset on the first storage element (302) during the matching period n and that the matching periods alternate with measuring periods in which the feedback loop around the amplifier element is disconnected and the one connection of the first memory element (302) is again connected to the summing node (36) in order to adjust the voltage offset of the amplifier element (50) by voltage on the Compensate memory element during the measurement period. 40. A modulator according to claim 39, characterized in that control means (340) are provided for synchronizing the adjustment and measurement periods with the clock pulses, the adjustment periods occurring during part of each clock interval and the measurement periods occurring when the first modulated signal bistable circuit (52) changes in response to the measuring means. 41. Modulator according to claim 35, characterized in that the measuring means (298, Fig. 21) include first (328) and second amplifier elements (336), which for determining when a signal at an input of the corresponding amplifier element reaches a level threshold, as Comparators are connected, one input (326, 334) of each amplifier element being located in an electrical path to the summing node (36), that offset compensation means (56, 316, 320, D, E, F, G, H, J) are present, which each have a first memory element (316, 320) on which the offset voltage is stored and which is connected to the input of each of the amplifier elements and connected to the electrical path in such a way that the outputs (330, 338) of the first ( 328) and the second amplifier element (336) are alternatively connected to the bistable circuit (52) during first and second measurement periods, the amplifier element connected to the bistable circuit (52) ei n emits the first control signal which is high when the integrated difference signal is above the level threshold and which is low when the integrated difference signal is below the level threshold and which determines the offset compensation means (D, E, F, G, H, J) are to charge the first memory element (316) connected to the first amplifier element (328) to the offset voltage during a first amplifier trimming period, while the second amplifier element (336) is connected to the bistable circuit (52) in order to do this with the charging the second amplifier element (336) connected first storage element (320) to the offset voltage during a second amplifier adjustment period, while the first amplifier element (328) is connected to the bistable circuit (52), the adjustment periods of the first amplifier element (328) between the first measurement periods and the adjustment periods of the second amplifier element (336) between the second measurement periods. 42. Modulator according to claim 41, characterized in that the one input (326, 334) of each amplifier element (328, 336) connected to the electrical path to the summation node (36) is the inverting input, that one with the offset compensation means (56, 316, 320, B, E, F, G , H, J) there is a switchable feedback loop around each of the amplifier elements, which is selectively switchable during each respective adjustment period between the inverting input (326, 334) of the respective amplifier dementes (328, 336) and its output (320, 338), so that a voltage offset with low impedance appears at the respective inverting input, and that the offset compensation means (D, E, F, G, H, J) for transferring the voltage offset of the corresponding amplifier element (328, 336) to the connected first memory element (316, 320 ) are determined during the comparison period. 43. Modulator according to claim 41, characterized in that the offset compensation means (56, 316, 320, D, E, F, G, H, J) ensure that the adjustment period of each of the amplifier elements (328, 336) is shorter than that Measurement period, in order to minimize errors due to a slow comparator reaction, the adjustment period of the first amplifier element (328) is ended by a predetermined interval before the start of its measurement period and the adjustment period of the second amplifier element (336) also ends by a predetermined interval before the start of its measurement period . 44. Modulator according to claim 35, characterized in that one connection of the amplifier element is connected to the summation node and the other connection is connected to the first storage element on which the offset voltage is stored. 45. Modulator according to claim 44, characterized in that the amplifier element is a first amplifier element (46, Fig. 2) of the measuring means (42), that a second memory element (44) in a negative feedback loop between the inverting input and the output of the first amplifier element (46) and the inverting input is also connected to the summing node (36), so that the integrated difference signal appears over the second storage element (44) and that a comparator element (50) for determining when the integrated difference signal is on the second storage element a level threshold is reached, between the output of the first amplifier element and the bistable circuit (52) is connected. 46. A multiplier arrangement for a measuring device according to claim 13, which is responsive to the first modulated signal and the second analog signal for producing a product signal (88) which has a size proportional to the power transported on the line, characterized in that phase shifting means (160 ) for adjusting the phase relationship between the first (Iai) and the second analog signal ÖU2), the phase shifting means (160) have delay means (198, 212) for delaying an applied signal by a selected number of clock pulses (196) by to cause a particular phase relationship between the first (Iai) and the second analog signal (Iaî) and that a multiplier (164) to generate a second product signal (170) indicative of a particular phase relationship of the power value on the line (10) , is available. 47. Multiplier arrangement according to claim 46, characterized in that a modulated signal (53) is applied to the phase shifting means (160). 48. Multiplier arrangement according to claim 47, characterized in that the delay means (198, 212) contain a first shift register (198) which is clocked with the predetermined clock pulses (196) by the modulated signal (53) by a selected number of clock intervals to delay. 49. Multiplier arrangement according to claim 47, characterized ge5 10th 15 20th 25th 30th 35 40 45 50 55 60 65 7 672 847 indicates that the delay means (198, 212) have a plurality of shift registers which are clocked with predetermined clock pulses, a first shift register (198) being clocked with first clock pulses (196) to the modulated signal (53) by a selected number of first Delay clock intervals and a second shift register (212) is clocked with second clock pulses (208) and wherein the second clock intervals are shorter than the first, so that a delay of the modulated signal (53) can be generated, which is the sum of a selected number of corresponds to the first and second clock intervals.