NL8420205A - POWER MEASUREMENT SYSTEM AND METHOD. - Google Patents

Description

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Description.

Power measurement system and method.

Technical area.

The invention generally relates to circuits for supplying one or more signals proportional to power or to another selected measuring parameter, and more particularly to an improved power measuring circuit and method which utilizes delta-minus sigma. applies modulation and shifted compensation scheme.

Background technique.

Meters that accurately measure electrical power across a conduit are an essential part of an electrical utility system. The most common type of meter used in today's electrical utility industry is the rotary disc meter which in its basic form is accurate and reliable but provides only limited information to the utility about power utilization. In addition to total power consumption in kilowatt hours, utilities often need to measure other parameters to properly determine the costs of feeding certain loads. For example, some highly reactive loads are more expensive to feed because they induce a current / voltage with a phase difference known as the power factor. To determine the power factor, utilities have designed certain standard power measurements. Two widely used measurements are VARS (for reactive 25 volt amperes) and Q. Both are power measurements proportional to the product of the line current and voltage with the voltage phase lagging behind the current at 90 ° for VARS, and at 60 ° for Q. Together with a total power consumption, the readings from VARS and Q allow the utility to measure the power-30 factor for which a fine is usually charged. Another parameter of importance to utilities is the polarity or direction of the energy flow since 8420205 - 2 - some applications both consume power and feed power back into the distribution system. There is a continuing need in the electrical utility industry to measure systems capable of measuring such parameters as VARS, Q and polarity in addition to total energy consumption.

Various electronic measurement systems have been proposed to replace the rotary disc meter. Several examples of the prior art of electronic measurement systems include those known from the following patents: US. 3,875,508; U.S. 3,955,138 and US 4,182,983.

These systems all employ modulators which supply a pulse width modulated signal proportional to either the current or voltage and then use time division or license space multiplication which gate or invert the polarity of the other signal to obtain a product signal.

The product signal pulses vary in amplitude with respect to one analog value (current or voltage), and vary in width with respect to the other analog value. A low-pass filter extracts the DC component of the product signal that is proportional to power consumption.

It would be advantageous to have a very accurate measurement system that is electronic and capable of delivering power readings continuously in both kilowatt hours and VARS or Q

at the lowest possible cost. It would also be advantageous if such a measurement system could separately measure the net power flow in each direction. The measurement system must also be practically free from errors due to voltage shifts in the active circuit elements. The system should therefore advantageously include a shift compensation system that can economically compensate for errors in multiple amplifier elements.

Disclosure of the invention.

Thus, a measurement system and method 8420205-3 is provided for measuring electrical power transported over a conduit. The system includes means for controlling the current and voltage signals on the line. A first signal transducer provides a first analog signal proportional to one of the current voltage signals and a second signal transducer provides a second analog signal proportional to the other current voltage signals. A modulator modulates one of the analog signals to provide a first modulated signal that can be changed between two levels at predetermined first clock intervals such that the first modulated signal has an average level over each sufficient interval proportional to the selected analog signal. First multipliers are arranged to gate the other of the analog signals due to changes in the level of the first modulated signal, multiplying the analog signals together to provide a product signal proportional to the power transported across the line .

A converter then converts the product signal into a first output signal which is to change in the preferred embodiment between two levels at predetermined converter clock intervals in a manner proportional to the product signal and to the power carried across the line.

The preferred measurement system of the invention includes a converter which separately measures power 25 at each polarity on the line and includes digital means for changing the phase relationship between the analog signals to provide a product signal proportional to a selected phase relationship of a power value such as VARS or Q.

The system also includes a shift compensation system that corrects for 30 voltage shifts in the various operational amplifiers of a measurement system to eliminate shift errors and provide high accuracy. The offset compensation system described will correct a voltage offset between the input of N amplifier elements. The offset compensation system includes N offset 8420205-4 memory elements which are respectively connected to one input of each of the amplifier elements to receive a compensation voltage which practically reduces the offset error at the other input of the amplifier element. Any difference between the compensation voltage and the voltage shift of the amplifier element is called an error voltage which occurs at the other amplifier input. The system includes a zeroing circuit which can be connected in sequence to each of the N amplifier elements 10 and the shift memory elements connected thereto so that each of the amplifier elements becomes the selected amplifier element of which the offset is offset in sequence. The zeroing circuit is first connected to the other input of the selected amplifier element during an intermittent transmission period to determine the error voltage. Then, the zeroing circuit is connected to the shifted memory element connected to one input of the selected amplifier element during an intermittent charging period following the transfer period. The offset compensation system 20 includes means for sequentially providing the transfer and charge period for each of the N amplifier elements so that offset errors in the measurement system are practically eliminated.

Brief description of the drawings.

Figure 1 is a schematic block diagram of a measuring system for measuring power over a pipe according to the invention.

Figure 2 is a schematic circuit diagram of the first modulator portion of the measurement system shown in Figure 1.

Figure 3 is a schematic circuit diagram of the first output transducer portion of the measurement system shown in Figure 1.

Figure 4 is a series of graphics illustrating Figures 4a through 4g and showing certain selected internal and external signals provided during the operation of the measurement system of Figures 1 to 3.

Figure 5 is a series of graphic illustrations showing Figures 5a through 5i and showing various internal and external signals supplied by the converter of Figure 3 during the measurement of signals of different polarities.

Figure 6 is a schematic circuit diagram of an alternative embodiment modulator for use in the power meter system of the application which provides phase advance in the modulated output signal.

Figure 7 is a series of graphics illustrating Figures 7a through 7g and indicating certain selected internal and external signals provided by the Figure 6 modulator.

Figure 8 is a schematic block diagram of the measurement system of the invention that includes a device for providing measurements of VARS and Q.

Figure 9 is a schematic diagram of a signal multiplier that can be used in the measuring system of Figure 8 and which includes a digital circuit for phase adjustment to enable the production of VARS and Q measurements.

Figure 10 is a series of graphical illustrations shown in Figures 10a through 10h showing certain selected internal and external signals supplied in the Figure 9 multiplier.

Figure 11 is a schematic diagram showing further details of a digital phase adjustment circuit of Figure 9.

Figure 12 is a series of graphic illustrations shown in Figures 12a through 12d showing a selected phase setting of a modulated signal supplied by the multiplier of Figure 9.

Figure 13 is a schematic diagram of 8420205-6 - a voltage shift compensation system for use in the invention.

Figure 14 is a graphical illustration of the change in the error voltage supplied by the compensation system of Figure 13.

Figure 15 is a schematic diagram of a voltage shift compensation system of the kind shown in Figure 13 for a whole power measurement system.

Figure 16 is a timing diagram showing the operation of the shift compensation system of Figure 15.

Figure 17 is a schematic diagram of a modulator with a second embodiment for use in the power measurement system of Figure 1.

Figure 18 is a series of graphical illustrations shown in Figures 18a through 18e showing various signals supplied by the modulator of Figure 17.

Figure 19 shows the modulator of Figure 17 20 with an alternative embodiment of a voltage shift compensation system.

Figure 20 is a timing chart showing the control signals for operating the voltage offset compensation system of Figure 19.

Figure 21 is an alternative embodiment of the modulator for use with the measurement system of Figure 1 that includes the voltage shift compensation circuit.

Figure 22 is a timing diagram showing the control signals for operating the offset compensation system of Figure 21.

Figure 23 shows an alternative embodiment modulator and associated dual polarity output circuit.

Figure 24 is a series of graphical illustrations shown in Figures 24a through 24j showing various signals supplied by the modulator of Figure 23 and associated circuitry.

Best mode for carrying out the invention.

With reference now to Figure 1, the measuring system according to the invention is schematically indicated as a means for measuring the electrical power transported over a power line 10 from a source 12 to a load 14. The current on the line 10 is in the generally indicated as L, and the voltage as V_. The system

L L

10 includes a signal control and conditioning means such as transformers 16 and 18 for controlling V_ and IT, residual

L L

pectively. Transformer 16 designated as the first signal means supplies a first analog signal I proportional to V across line 20. Transformer 18 indicated as L15 as second signal means supplies a second analog signal proportional I across line 22 A shunt resistor 24 is connected across the secondary winding of transformer 18 through which most of the current flows on line 22. The shunt resistor 24 outputs a low impedance current 20 and may be selected to control the total range of the current signal I on line 22.

The measuring system and method according to the invention operate to multiply together the first and second analog signal Ij, then over the lines 20 and 22, respectively, and then convert the multiplied product signal into a suitable digital form.

Broadly speaking, this is achieved by modulating one of the signals and then gating or switching the other of the signals to give a composite or product signal of an average value proportional to power. Those skilled in the art will understand that either the current on the voltage could be modulated and the resulting modulated signal used to gate the other of the two analog signals to provide the product signal. Thus, the designation of the first and second analog signals as the voltage and 8420205-8 current signals, respectively, could be reversed without changing a fundamental operation of the measuring circuit shown in Figure 1. Similarly, the designations for the first and second signal monitors can be reversed in the same manner.

The measurement system provides a multiplier for multiplying the signals I and together to provide a product signal proportional to the power transported over the line. To provide the necessary multiplication, the voltage signal I j is first applied to a first modulator circuit 30. The modulator 30 forms a modulator means for converting the analog voltage signal I j into a first modulated signal that is changeable between two levels 15 at predetermined clock intervals. In accordance with the principles of the delta minus sigma modulation, the first modulated signal output has an average level over each sufficient interval proportional to the first analog signal applied to the modulator input 32.

Referring now to Figure 2, the more analog (voltage) signal is supplied to a sum & node 36 via an impedance 38. The modulator 30 includes a modulator feedback means for supplying the feedback signal I, which is also supplied to the summation node 36.

F

25 I_ is controlled by the modulator output, called the first modulated signal, which occurs on line 34. One of the other of a pair of reference sources V1 + and V1 - is alternately connected to the summing node 36 via an impedance 40 due to the level of the first modulated signal.

The feedback signal schakeltρ switches between the positive and negative reference sources in a manner that balances the first analog signal I over time. Instantaneous differences between I and the first analog signal result in a difference signal I ^ from the summing node 36. The instantaneous difference between the input and feedback signals, namely 8420205-9 & lff, is measured by a modulator measurement circuit 42. The measuring circuit 42 includes an active integrator with a capacitor 44 as the feedback element of an inverting operational amplifier 46. The signal at the amplifier output 48 runs up and down depending on the polarity of The integrated signal at 48 is compared against a modulator threshold level through a comparator 50 which goes high when the signal is above the modulator threshold level and low when the signal is below the modulator-10 threshold level.

The output of comparator 50 is applied to the D input of a bistable modulator circuit 52.

The Q output of the bistable circuit 52 is the first modulated signal. The bistable circuit 52 changes only at 15 predetermined first clock intervals determined by an external clock. A suitable clock for this purpose is provided by a conventional oscillator 54 and frequency divider circuit 56 shown in FIGS. 1 and 2. For simplicity, the time interval between the pulses supplied by the frequency divider 56 will be considered the first clock. The bistable circuit 52 has a Q output as well as Q, where Q is the inverse of Q. Both the Q and Q outputs are used to control the feedback signal I by operating a pair of switches 58 and 60, respectively. Since it is understood that 0 and Q are the inverse of each other, only the Q output is mentioned herein as the first modulated signal. However, it is to be understood that both the Q and Q outputs contain the information represented by the term "first modulated signal" and that the line 34 indicates the lines 30 carrying both the Q and Q signals.

Since the first modulated signal is output through the bistable circuit 52, the first modulated signal over line 34 is changeable between two levels at predetermined first clock intervals. Although the level cannot change at every clock interval, the modulator chain ensures that when the first modulated signal changes level, such a change occurs only at the predetermined first clock intervals and at no other time. Changes between the high and low levels of the first modulated signal simultaneously provide switching of switches 58 and 60 and corresponding reversals in the polarity of the feedback signal I to the summing node 36. Since the integrated difference signal runs either up or down the threshold level of the comparator 50, changes in the level of the comparator output are provided. At each clock interval, the bistable circuit 52 determines whether the output of comparator 50 has changed and if so it provides a corresponding change in the Q and Q outputs. The magnitude of the analog input signal causes a directly proportional change in the amount of time that the first modulated signal is at a given level. Consequently, the first modulated signal has an average level or amplitude that is either at or between its two levels, and over each sufficient interval, such average amplitude is proportional to the analog input signal.

As an example of the operation of the modulator 30, when the input signal at the input 32 is zero, the Q output of the bistable circuit 52 will be exactly the same amount of time high as low with an average level being delivered exactly midway between the high and low levels of Q.

When the input signal at the input 32 has a positive value, the positive current in the summing node 36 must be balanced by a larger negative current supplied to the summing node by the negative reference V1-, through the switch 58. Consequently, Q will be proportionately longer for a low then high and the switch 58 will be closed and the switch 60 will be open for a greater amount of time than vice versa. When the input signal is negative 8420205-11, it is necessary that the positive feedback reference be applied in time so that I balances the input signal and Q will be more high than low. It is a feature of the modulator of the invention that Q can remain high or low for how long it takes I to balance the input signal in the summing node.

To provide a current signal for multiplication with the modulated voltage signal, the system includes means for providing inverted and non-inverted representations of the line current I. With reference to Figure 1, the current analog signal 1 ^ is first applied to an amplification amplifier 70, after which the signal is supplied to a signal reversing circuit 72. The indicated reversing circuit includes an operational amplifier 74 and 15 gain adjustment resistors 76 and 78. The amplified signal 1 ^ 2 is supplied to the inverting input of the amplifier 74 which is constructed to provide a gain of -1. The reverse signal is then supplied to one of two switches which together form first gate means 80. The inverted signal passes to switch 82, and a second lead 84 carries the non-inverse amplified signal to switch 86. It will be appreciated that a suitable mid-branch transformer could be used instead of a second transformer 18 in which in case the signals to the switches 82 and 86 could be supplied directly from the transformer.

The Q and Q outputs of the bistable modulator circuit 52 are used to cause the switches 82 and 86 to operate to gate the second analog signal 30 in response to the first modulated signal. Since Q is the inverse of Q, switches 82 and 86 are alternatively switched so that the output of gate means 80, at 88, is an analog signal switched in a modulated manner between positive and negative polarities. Such a gating operation is generally referred to as 8420205-12 - time division or amplitude sign space modulation. The switches 82 and 86 perform the multiplication of the two analog signals representing the current and the voltage of the power carried across the line 10. The resulting signal 5 called a product signal occurs at the first gate output 88 and is proportional to the power transported over the power line 10.

As shown in Figure 1, the product signal output from the first gate member is supplied to a first converter circuit 90. The converter chain converts the product signal into a first output signal on line 92 which is changeable between the two levels at predetermined converter clock intervals at a proportional to the product signal. The converter 90 essentially functions as a low-pass filter that extracts the DC component or the mean value of the product signal. The resulting first output signal is proportional to the power carried across line 10.

Referring now to Figure 3, the converter 90 is essential to a delta minus sigma modulator of a kind similar to modulator 30 designed to provide separately modulated output signals proportional to any polarity of the input signal. To simplify the description, the converter 90 and its operation will be initially described with respect to a first polarity of operation. The components in the housing 94 contain all elements used in single polarity operation. In the following example, it will be assumed that the product to be converted / signal is predominantly positive, and it will be assumed that this corresponds to a power flow on line 10 from source 12 to load 14. As in the modulator 30, the input signal to converter 90 is indicated by I (product signal) initially

P

applied to a summing node 96 via an impedance 95. A feedback means supplies second signals to the summing 8420205-13 node from one of a number of reference sources. For a positive polarity effect, the reference sources will alternate between a negative reference source 98 (VR-) supplied through a switch 100 and a ground connection 102 supplied through a switch 104. Since only positive values of the product signal are considered, i will switch between ground and a negative value is sufficient to balance the product signal in the summing node 96, over time.

As already described for the modulator 10, any difference between the product signal I and I 'is a P2 difference signal supplied to a measuring circuit 106. The measuring circuit integrates the difference signal and compares the difference signal with a first threshold level. The preferred embodiment measuring circuit shown in Figure 3 includes an active integrator 107 consisting of an amplifier element 108 and a capacitor 110 as a feedback element. The voltage at amplifier output 112 goes up or down depending on a polarity of the difference signal in sum node 96. The integrated difference signal at 112 is supplied to a first comparator 114 which has a threshold setting at a selected first threshold level. When the integrated difference signal at 112 is above the first threshold level, the output of comparator 114 is high. When the integrated difference signal is below the first threshold level, the output of comparator 114 is low.

The comparator output referred to as a first control signal is supplied to the D input of a bistable circuit 118 through line 116. The Q output of bistable circuit 118 is only changeable at 30 predetermined converter clock intervals which are preferably longer than the first clock intervals for the modulator 30. The converter clock intervals can be provided by adding a second frequency divider 120 to the first clock 156. The time intervals between the pulses supplied by the frequency divider 120 will be referred to as converter clock intervals 8420205-14. frequency divider will be called the converter clock. The Q output of the bistable circuit 118 in the first output signal that controls switches 100 and 104 to determine the operation of the feedback system supplying a second signal I ^ to the summing node 96. The switch 104 is operated by a gate 122 which gives a high signal output to close the switch only when both inputs 124 and 126 are low. Gate 122, as shown, is a conventional negative AND gate. During 10 periods of positive product signals, input 126 will remain low as described below. Consequently, when Q is high, the switch 100 is closed, connecting VR to the summing node 96, and when the Q is low, the switch 100 is open and the switch 104 is closed.

The operation and method of the measuring system according to the invention will now be described with reference to Figures 1-4. For simplicity, it will be assumed that power over line 10 is predominantly positive. The voltage of line 10 is shown in Figure 4a as a sinusoidal alternating current waveform.

The current I is shown in Figure 4f as an increasing value represented by the curve 128. The first step is for the transformers 16 and 18 to control the current and voltage signals and to supply analog signals proportional to the line voltage and current respectively.

One of the analog signals, voltage signal I ^ in the preferred embodiment, is then supplied first to the first modulator 30. Figure 4c shows the integrated difference signal supplied in the modulator 30 by the delta-30 minus sigma modulation technique described above. The integrated difference signal is supplied to the measuring circuit 42. Figure 4b indicates the first clock intervals supplied by the first clock 56. As can be seen, the slope of the integrated difference signal in Figure 4c changes only at predetermined clock intervals determined by the first clock signal. Since the bistable 8420205-15 circuit 52 clocks the leading edge of each upwardly moving pulse, the predetermined first clock intervals are shown starting at the points identified as a, b, cf d etc. in Figure 4b. The integrated differential signal is then fed to comparator 50. Line 30 in Figure 4c represents the modulator threshold level in comparator 50. Note that the integrated difference signal reverses the slope at the beginning of each clock interval after threshold 130 has passed. The output of comparator 50 is shown in Figure 4d. When the integrated difference signal is below the threshold 130, the comparator output is low and warn the integrated difference signal is above the threshold 130, the comparator output is high. The comparator output is then applied to the D input of the bistable circuit 52 which supplies the Q or the first modulated signal output shown in Figure 4e. The Q output is the result of modulating the voltage signal and is changeable between two levels at the predetermined first clock intervals.

Because the bistable chain is changeable only at the predetermined clock intervals shown in Figure 4b, the changes in Q lag somewhat behind the changes in the comparator output shown in Figure 4d. Depending on the level of accuracy required at the signal multiplication system, it may be desirable to compensate for the slight lag in the modulated signal introduced by the bistable circuit 52. Such correction can be achieved by plugging an RC net in lead 20 to introduce a small phase advance 30 into the signal I as it enters the modulator input 32. Another technique would be to induce a slight lag in the current analog signal I ^. The dual alternative using a delta-minus sigma modulator with digital phase advance chain will be described next. The phase setting introduced and which will be only part of a first clock interval must be the average of the delay induced by the lag of Q with respect to the comparator output.

Figure 4f shows equal and opposite 5 analog signals proportional to the line current I. The lei

X 128 is a representation of an increasing current signal and the line 129 is the reverse signal supplied by the inverter 72. The next step is to gate the current analog signal using the gate 80.

The output of the gate member 80 is the product signal, the curve 131 shown in Figure 4g. Curve 131 is generated by switching between signals 128 and 129 in response to the first modulated signal shown in Figure 4e. The average level or the DC component of the curve 131 is represented by the line 132 of Figure 4g.

In the example given, it is assumed that power predominantly flows in a direction in the load 14. Accordingly, the product signal 131 shown in Figure 4g is predominant with a positive polarity represented by the lead 132. It will be assumed to describe the operation of the converter 90 hereinafter that the product signal has a predominant and average value which is positive. Although the actual polarity of the product signal is a matter of design choice, the product signal 25 will predominantly have a first polarity when power on lead 10 has a first polarity with a power current and device and will be predominant from a second polarity when power on the line 10. lead 10 has a second and opposite polarity with the power flowing in the other direction.

The next step is to convert the product signal I into a first output signal that is changeable between two levels at predetermined intervals in a manner proportional to I. Reference will be made

P

35 after Figures 3, 4 and 5. The product signal 1, as shown in 8420205 - 17 - Figure 4g is supplied to the converter 90. Both I and the second signal I are supplied to the summing node 96 where the instantaneous difference is introduced into the integrator 106. The time constant of the integrator 106 is chosen to be long compared to the switching frequency of the first modulator 30. The converter 30 can therefore act as a low-pass filter that only addresses the DC component or average value of the product signal

needle I. To this end, I is depicted in Figure 5a as a smooth P P

10 analogous curve, although it will actually vary in the manner shown in Figure 4g. Figure 5a shows only the mean value of 1 ^. The time scale of Figure 5a is significantly compressed compared to the scale of Figure 4g. For illustrative purposes, it will be assumed that the interval 134 of Figure 5a is equivalent to the entire length of the curve 132 shown in Figure 4g. Figure 5b shows the converter clock intervals supplied by the clock 120.

Considering only the positive power current, indicated between tA and t in Figure 5a, the integrator 106 will output an integrated difference signal (IDS) as shown in Figure 5c. The integrated difference signal runs up and sews around the first threshold level TL1 of the comparator 114. The integrated difference signal (IDS) is supplied to the comparator 114 from which the first threshold level TL1 is compared. Comparator 114 outputs control signal 133 on lead 116 as shown in Figure 5d. The next signal to be generated is the first output signal shown in Figure 5e which is output through the bistable circuit 118.

The control signal 113 changes levels depending on the level of the integrated difference signal with respect to the threshold TL1. When IDS is above TL1, signal 133 is high and when IDS is below TL1 then 133 is low. The next step is to output the first output signal shown in Figure 5e through the first bistable circuit 8420205 loop. The first output has an average level proportional to a first polarity of power on line 10 over a sufficient interval. It is changeable only at the predetermined converter clock intervals indicated as w, x, 5 y and z in Figure 5b.

The single polarity operation of the converter 90 involves switching the feedback signal between first reference source 98 and a second reference source 102 depending on the level of the first output signal 10 (Figure 5e). Since the second reference source 102 is a ground connection, the part of the converter 90 described so far will not be suitable for a negative power flow on line 10. When the power current (1 ^) is negative as between at times t and in figure 5a an additional circuit is used in the converter 90. With reference to Figure 3, the converter 90 includes a second comparator 140 which receives the output from the integrator 107. The comparator 140 has a second threshold level TL2 which is different from the first threshold level of the comparator 114.

The threshold levels must be set far enough apart to accommodate the most widely anticipated variations in the integrated difference signal output of the integrator 107 without exceeding the threshold levels of both comparators simultaneously. The integrated difference signal is supplied to a non-inverting input of comparator 114 and to the reversing input of comparator 140 so that their outputs will have opposite polarity. The output of comparator 140 goes high when the integrated difference signal is below the second threshold level in comparator 140 and goes low when the integrated difference signal is above the second threshold level in comparator 140.

The output of comparator 140 is applied to the D input of the second bistable circuit 142.

The second bistable circuit 142 outputs an output of a second output 8420205-19 from its Q output. The second output signal has one of two levels depending on the level of the integrated difference signal with respect to the second threshold level at each of the converter clock intervals.

The second output signal is applied to the input 126 of the negative AND gate 122 and to a switch 146 for connecting a third reference source VR + to a summing node 96. The feedback signal is thus controlled by the level of the second output signal which has an average 10 level proportional to the second polarity energy carried over the power line 10.

The second polarity operation of the converter 90 will be described with reference to Figures 3 and 5.

After the time t ^, the direction of the power flow reverses and the product signal I begins to draw a load from the summing node 96. With reference to Figure 5c, just prior to the time t ^, the integrated difference signal drops, which means that the negative reference source VR- is connected to the summing node via switch 100. At the clock pulse that follows 20 exceeding the first threshold level TL1, the

switch 100 opens and switch 104 will close, grounding the summation node. Since the product signal I

P

negative after t ^, the integrated difference signal will continue to integrate downward until it reaches the second threshold level TL2 of comparator 140 when its output 135 goes high (see FIG. 5g). At the next comparator clock interval after converter 140 goes high, the Q output of bistable circuit 142 (the second output signal goes high as shown in Figure 5a). When the second output signal goes high, a switch 148 connected to the third reference source 146 (VR +) is closed. The third reference source supplies a positive current to summing node 96 to counterbalance the negative

drives product signal I and IDS over TL2. When TL2 P

35, the signal 135 goes low again, causing 8420205-20 to cause the second output signal to go low at the next clock interval. During the second polarity operation, the first output signal (Figure 5e) remains low and when the second output signal (Figure 5h) is low, both inputs to gate 122 are low and its output goes high. When the output of the gate 122 goes high, the switch 104 is closed and the ground connection reference source 102 is connected to the summing node 96. When the switch 104 is closed, IDS is again allowed to step TL2 over-10 in the other direction. During the interum between times t1 and t2 / when the power current is negative, the integrated difference signal is maintained in the vicinity of the second threshold level TL2.

The converter 90 shown in Figure 3 is provided with three different reference sources, the second of which is a connection to the common ground for the measuring circuit. Due to the construction of the circuit elements, the ground connection is used when the integrated difference signal is in the range between the first and second thresholds TL1 and TL2. It is not essential that the second reference source is a ground connection. Separate positive and negative reference sources could be used for any polarity of operation if desired. In such a case, the first and second reference sources 25 should be used to supply the second signal to the summing node 96 when the product signal I is a first

P

has polarity and separate third and fourth reference sources could be used to supply the second signal I2 to the summing node 96 when the product signal 30 is of the other polarity. In practice, the selection of the values for the reference sources is governed by the need to maintain the integrated change signal in the vicinity of the threshold level of the comparator used. Moreover, the sizes and polarities of the reference 35 curves are entirely a matter of design choice.

8420205 - 21 -

Using the reference sources in converter 90 containing at least one ground connection improves the overall accuracy of the output of the modulated signals. While variations can occur in the positive and negative voltage reference sources, the ground connection remains fixed. When one or both of the positive and negative reference sources is above or below its correct value, a one level error will be slightly longer or shorter than it must be because during the time the voltage reference source provides the feedback signal it is slightly too much or too little power. The closer the input signal is to ground (zero), the smaller the error will be. Equal and opposite reference sources, such as those used in the feedback system of the modulator 30, have a greater potential for error when there is a mismatch between the reference voltages V1 + and V1 - since the feedback system of the modulator 30 always switches between V1 + and VI- , any error resulting from a reference voltage error adjustment will tend to cause the modulated output to be at one level or the other with an incorrect amount of time without regard to the magnitude of the input signal. This does not pose a problem in the case of the modulator 30 because it modulates the line voltage signal which generally varies with only a small amount. Accuracy therefore only needs to be maintained over a small area. However, the converter 90 requires greater accuracy because a wide variation in the product signal represents lead power. As a result, the separation of the converter operations between a positive and negative polarity of the power has certain advantages.

Since only one polarity is measured by each comparator, the reference sources can use a ground connection to provide the feedback signal to improve overall converter accuracy. The information provided on the power flow of each polarity is also desirable 8420205-22 as it provides additional information about the nature of the load and its power requirements.

The first and second outputs have an output on lines 92 and 144 of converter 90 (see Figure 1) and are changeable between two levels at the converter clock intervals. To provide a suitable digitized output in which the pulse density is proportional to the power flow, a system for converting the output signals into pulse arrays is provided. In Figures 1 and 5, the first and second output signals are supplied to the first and second AND gates 150 and 152, respectively. A second input to the AND gates is supplied from the converter clock 120. Figure 5f shows the pulse train supplied for the power of a first polarity from AND gate 150.

The pulse train has a pulse density proportional to the magnitude of the power flow in one direction on the lead 10. Similarly, for a power flow in the opposite direction, Figure 5i shows a pulse train for a power of the second polarity from AND gate 152. Er various means are available for processing the first and second digital output signals shown in Figures 5f and 5i, respectively. For example, it will be convenient to supply the digital signals to counting means for counting the positive and negative polarity pulses. The counter could then output a Display or record the total power consumption. Counter 154 is an example of such a display idea. In addition, when a gate signal is applied to the counter 154, measurements of power in appropriate units, such as kilowatts, could be easily obtained. Separate power current readings in each direction could also be obtained.

As noted earlier, a slight lag is introduced into the modulated output since the bistable circuit 52 (Figure 2) is only 8420205-23 variable at predetermined clock intervals.

Figure 6 shows a new delta minus sigma modulator 30 'with a digital phase advance circuit to compensate for the phase lag. The same elements in the Figure 2 and Figure 6 modulators are indicated by the same reference numerals. It is noted that such a digital phase advance circuit has other applications than power measurement systems. In addition, if desired, a phase pre-lag can be provided which is more than sufficient to compensate for the phase-10 lag caused by the output bistable 52 of Figure 2.

The modified modulator 30 'of Figure 6, like the modulator of Figure 2, includes a bistable circuit 52 which controls a source of a feedback current I through the switches 58 and 60. A summing node 36 receives the input signal Ij through the input resistor 38. Instantaneous differences between the feedback and input signals are represented by 1 ^. and this difference signal is measured by the measuring circuit 42. The control signal output of the comparator 50 is high when the integrated difference signal is above the threshold of the comparator and is low when the integrated difference signal is below the threshold.

The modulator 30 'differs from the modulator 30 in Figure 2 in that it contains a digital shifter between the measuring circuit 42 and the bistable circuit 52. The digital shifter introduces a time delay in the control signal output of the comparator 50. In Figure 6, the digital shift a bistable circuit 59 which receives the control signal output from the comparator at its D input. For the purposes 30 of the example given below, the bistable circuit 59 is clocked at the same rate as the bistable circuit 52 but one half clock out of phase.

The operation of the modulator shown in Figure 6 to obtain phase advance in the modulated output signal will be described with respect to Figure 7.

8420205 - 24 -

The input input signal I to the modulator 30 'is shown ΆΧ in Figure 7a. The output of the first clock 56 is shown in Figure 7b. The first clock 56 also supplies the signal to the bistable circuit 59 through a reverser 57 and the second clock signal is shown in Figure 7c. If I is positive at the clock pulse a and the Q output of the bistable circuit 52 shown in Figure 7g is initially high then I will be positive.

F

be active in the summing node 36. This will give a positive input to the inverting input of the integration amplifier 46 to cause the integrated differential signal at point 47 to initially drop down at 21 of Figure 7d. Line 22 in Figure 7d represents the threshold of comparator 50. When the integrated difference signal exceeds threshold 22, the line shown in Figure 7e goes from high to low. Assuming that the bistable circuit 59 clocks in with the pulses a ', b', c ', d', e ', etc. moving upwards, the output of the bistable circuit 59 will go from high to low at clock pulse a'. The output of the bistable circuit 59 (Q ') is referred to herein as the delayed control signal which is then applied to the D input of the bistable circuit 52. Figure 7f shows the delayed control signal and Figure 7g shows the Q output of the bistable chain 52. When Q 'goes from high to low, the Q output of the bistable chain 52 will go from high 25 to low at its next clock pulse b. The change in Q opens switch 60 and closes switch 58 causing I_ to go negative. The integrated difference signal then increases, crossing comparator threshold 52 and again causing the control 30 signal to go high. At the clock pulse d 'of the second clock, the Q' output of the bistable circuit 59 again goes high. This causes the Q output of the first bistable circuit 52 to go high at its next clock pulse e.

The above-described process will continue with the Q output of the bistable circuit 52 providing the signals for controlling the feedback loop of the modulator. Assuming that the time delay introduced by the digital shifter represented by the bistable circuit 59 is not large enough to form instability in the feedback loop, modulator 301 will provide a modulated signal equivalent, but not identical, to this output of modulator 30. At equivalence it is meant that the Q output of the bistable circuit 52 will be a modulated signal changeable at predetermined first clock intervals 10 in a manner proportional to the signal input to the modulator.

The Q output bistable 59 will lead the Q output of the first bistable circuit 52 by an amount which depends on the difference in the clock signals supplied to the two bistable chains. This advance occurs as a natural consequence of the fact that the Q output of the bistable circuit 52 will change only at the next clock pulse following a change in the Q 'output of the bistable 59. The Q' output is thus a real "leading" signal to the Q output.

The output on line 34 will have a phase advance of half of a first clock interval compared to the Q and Q outputs of the bistable circuit 52. Since the clock intervals are applied to both the bistable circuit 59 and the bistable circuit 52 the same, the delayed control signal output on leads 34 will be changeable at the same intervals as the Q and Q outputs of the bistable circuit 52, and will otherwise be the same as any other delta minus sigma modulated signal. The clock signal supplied to the bistable circuit 59 actually becomes the determining clock controlling changes in the output of the modulator. It will be possible to substitute another type of digital slider such as a multi-stage shift register for the bistable chain 59 when the delay introduced is not so long as to destabilize the feedback pellet. The digital shifter used 8420205-26 can also be clocked at a different rate than the first bistable circuit 52, although that will change the characteristics of the delayed control signal. For example, if a multi-stage shift register clocked at a high speed were inserted in place of the bistable circuit 59, it would delay the control signal by a selected number of short intervals. The output of such a shift register would be a delayed control signal that is variable at the higher clock speed. A shift register could also be used with different stages clocked at different speeds. In such a construction, the longest clock interval used to clock one of the stages would determine the intervals at which the ultimately delayed control signal would be changeable. Each control signal delay system must include at least one bistable circuit clocked at discrete intervals such that the modulator's modulated output (the delayed control signal) will be changeable at these discrete intervals.

The phase advance produced in the modulator 20 * can be selected. Such a choice is made by adjusting the clock signals supplied to the bistable circuits 52 and 59. Assuming that a first clock signal supplying pulses at first clock intervals is supplied to the bistable circuit 52 and a second clock signal supplying 25 pulses at second clock intervals are applied to the digital shifter (bistable circuit 59), and both first and second clock intervals are equal, the phase shift between the clock signals will determine the amount of advance in the modulator output. In the example discussed with respect to Figure 7, the second clock was the inverse of the first clock and the total shift was half a clock interval. When the clock pulses supplied by the second clock to the bistable circuit 59 were three quarters of a clock interval prior to the pulses supplied to the bistable circuit 52, a phase advance of three quarters of the clock interval would be delivered. It is the amount of the delay between a change in the Q 'outputs of the bistable circuit 59 and the Q output of the bistable circuit 52 which determines the amount of the lead time in the signal output lines 34.

The amount of phase advance that can be obtained by the modulator of Figure 6 depends on the degree of tolerance that can be introduced into the feedback loop of a delta minus sigma modulator without causing its destabilization. However, it is known that a delay of part of a clock pulse in the manner described in the above example is functional and provides the phase advance in the modulated signal as described.

Figure 8 shows a measurement system according to a further embodiment of the invention which provides an additional output power measurement in either VARS or Q. As described in the background section above, VARS and Q represent power measurements in which a specified phase relationship is introduced between the current and the voltage signals.

VARS is obtained by multiplying the current by a voltage signal lagging by 90 °; Q is obtained by multiplying the current by a voltage signal that lags by 60 °. In the measurement system of this embodiment of the invention, VARS, Q or any other desired phase relationship power value can be easily obtained by delaying the output of modulator 30 by a selected amount. The delay can be easily provided by using time delay means such as a shift register in the manner described below.

The Q output of the modulator 30 of Figure 8 embodiment is supplied to both the gate member 80 and the shift register 160. The shift register 160 delays the output of the modulator 30 by a selected delay interval. The amount of delay depends on the desired selected phase relationship power value (VARS or Q), and also on the frequency of the AC waveform being measured (560 Hz).

To simplify the circuit, only the Q output of the modulator 30 is applied to the shift register 160. The time-delayed output of the shift register is then applied to an inverter 161 and both the inverted and non-inverted signals are time-delayed signal on lead 162. As used herein, the term "time delayed signal" is invariably used with "phase modified signal" / and it will be appreciated that the introduced phase modification is obtained through a time delay introduced into the signal.

Furthermore, the processing of the time-delayed modulated signal is exactly the same as for the first modulated signal of the embodiment of Figure 1. The time-delayed modulated signal is supplied to a second gate means 164 containing a pair of switches 166 and 168 controlled by the time-delayed modulated signal . The inverse and non-inverse current analog signal is supplied to switches 166 and 168. The phase modified modulated signal alternately closes switches 166 and 168 to multiply the current and voltage signal together and provide a second product signal at 170. The second product signal is then applied to the input of a VARS / Q converter 172 which is exactly the same as the converter 25 90 shown in Figure 2. VARS / O converter 172 first outputs a second output depending on the polarity of the power on line 10 in exactly the same manner as converter 90. The outputs of converter 272 are first and second outputs changeable between two levels at converter clock intervals in a manner proportional to the second product signal and the selected phase relationship power value (VARS or Q , 50 or 60 Hz) of the power on the line 10. Then there is a processing of the first and second outputs signals from VARS / Q converter 172 are exactly the same as for the outputs of converter 90 shown in Figure 1 8 4 2 U Z 0 5 - 29 - including the use of counting means suitable for an output of selected power values.

A selector (not shown) can be provided to choose either VARS or Q as the second output of the measurement system. The selector will set the shift register 160 to provide a voltage lag needed to generate the selected phase relationship and simultaneously select an appropriate display.

The exemplary and new digital phase selection technique indicated in Figure 8 is not limited to power measurement applications. The technique can be used in any signal multiplication application where the phase relationship between input signals can be set to measure selected phase relationship product values.

Figure 9 denotes a multiplier equal to the multiplier used in the power measurement system of Figure 8. The same elements are indicated with the same reference character signals. The signals to be multiplied together and assumed to have periodic waveforms are not necessarily sinusoidal with a predetermined phase relationship to each other. As in the power measurement system of Figure 8, a multiplication is obtained by the technique known as time extension or license plate space multiplication in which one of the signals I is modulated after being used to gate or reverse the polarity of the other signal I ^ product signal. The signal is applied to the gate member in both the reverse and inverse of a conventional inverter 72 supplied to the signal 82. The non-inverted signal is applied to the switch 65. The modulated signal for controlling the switches 65 and 66 is supplied to the gate member through line 34.

The modulator 30 of Figure 9 is equivalent in construction and operation to the corresponding modulator 30 8420205-30 of Figures 1 and 2. To obtain the selected phase relationship between the signal I and a digital shifter 160 introducing a selected delay in the output of the modulator 30. The digital shifter 160 may take numerous forms, with a simple version indicated in element 198 of Figure 11. The operation of the shift register can be conveniently indicated as a series of stages made from bistable chains 200 to 204 and connected such that the O output of one bistable chain is supplied to the D input of the adjacent bistable chain. A clock signal applied to each of the bistable chains through line 196 causes each stage to be clocked simultaneously. A digital pulse on line 53 in shift register 198 that goes either low to high or high to low will be delayed by one input clock interval through each bistable chain through which it passes. For example, when the signal passes a line 53 from low to high, the Q output of the bistable circuit 200 will go from low to high with the next clock pulse. Due to 20 inherent switching delays, When the O output of the bistable circuit 200 goes from low to high and this signal is applied to the D input of the bistable circuit 201, its O output must wait for the next clock pulse to go high . In this manner, digital signals can be appropriately delayed by any number of discrete intervals simply by providing enough delay steps in the shift register. It is common for shift registers to be provided with a number of output lines 206 where the signal can be extracted. The location of the pin contact determines the total delay introduced as a function of the clock frequency.

The digital time delay means 160 of the multiplication system shown in Figure 9 is assumed to be a conventional shift register such as shift register 198 of Figure 11. The multiplier system requests 8420205 - 31 - for introducing a selected time setting into one of the signals to be multiplied using a digital shifter to introduce a delay that is a selected number of discrete intervals. The shift register 98 is a suitable digital shifter for providing such a delay.

Referring now to Figure 10, it will be assumed that signals 1 ^ and must be multiplied together and a 90 ° phase lag will be introduced in the sig-10 sew I ^. Figure 10a shows an example of the first input

signals I (V) and figure 10 shows an example of an Al L.

second input signal to be multiplied together. Figure 10b shows the clock signal supplied by the clock 56 and Figure 10c shows the output of the integrator 42 resulting from the input signal. The output of modulator 30 is shown in Figure 10e and is carried over line 53 of Figures 9 and 11. The clock signal from modulator clock 56 is applied to shift register 198 through line 196. In the example given, clocks 20 intervals shown in Figure 10b 24 times the frequency of the signal 1 ^. 90 ° phase lag will therefore require a delay of six clock intervals. Assuming that the pin 206 'of the shift register 198 is the sixth pin, the signal 1 ^ 2i will be modulated and delayed by 90 ° thus delayed by a total of six clock intervals output from clock 56. The pin 206' output from the shift register 198 is indicated in Figure 10f. The delayed modulated signal shown in Figure 10f is an accurate reproduction of the modulated Q output of the modulator 30 shown in Figure 10e and moved 30 to the right six clock intervals.

The signal multiplication is obtained by supplying the delayed modulated signal shown in Figure 10 to the signal gate member through line 34. Line 34 includes both reverse and non-inverted versions of the delayed modulated signal to supply signal 8420205-32. to a conventional digital converter 161.

The signal I is that shown in Figure 10g in both inverted and non-inverted form. The multiplication is performed by means of the switches 82 and 86 which are alternately opened and closed with the switching point 88 of Figure 9 between the non-inverted and the inverted versions of the signal I. The resulting signal is shown in Figure 10h. The signal in Figure 10h can then be passed through a suitable low-pass filter 90 to give an average or DC value as shown on line 132 of Figure 10h. Line 132 represents a product signal proportional to the product value of I ^ and with a phase lag of 90 ° introduced in I ^. For example, if the signal I ^ was proportional to current carried across a power line and the signal was proportional to the line voltage, the product signal represented by the line 132 of Figure 10h will be proportional to VARS.

A particular advantage of using a delta minus sigma modulator such as modulator 30 in conjunction with the present multiplier is that the modulated signal is only changeable at predetermined clock intervals. Digital time delay techniques necessarily divide an incoming signal into discrete units or intervals. The length or duration of those intervals is a matter of design choice. Digital type signals carry information in pulse edges when the signal goes from low to high or from high to low. A shift register made from a series of bistable chains will "look out" for such pulse edges every time it is clocked. The higher the clock frequency, the more often the incoming signal is sampled for a pulse side. Since the delay introduced into the signal at each stage of the shift register depends on the clock frequency, shift registers clocked at high frequencies require more stages to provide a given delay than shift registers clocked at a low frequency.

8420205 - 33 -

Of course, clocking a shift register at a low frequency means that the incoming signal is sampled less often for pulse sides and this can be a drawback when the location of the pulse side is not known as in the case of conventional pulse width modulated signals.

The modulator 30 outputs a signal with pulse sides which only occur at predetermined clock intervals.

When synchronizing the clock signals supplied to the modulator and to the shift register 198, the shift register 10 will "look out" for pulse sides only at the times required.

This means that fewer shift register stages are required to introduce a given delay into a modulated signal than would be the case if the location of the pulse sides was not accurately known. In the above example 15, the shift register actually shows being clocked at a rate itself as the modulator 30 with no loss of information. It is therefore possible to use an economical shift register containing relatively few stages to provide a given delay in a delta-minus sigma-20 modulated signal that would require a much larger shift register to provide a similar delay in a signal with pulse sides at random places. Even if a relatively high frequency shift register was used to delay a randomly modulated signal at a considerably low frequency, some loss of information would occur if a pulse side was not accurately synchronized with the shift register clock. No such loss of information occurs in the embodiment of the invention described above since the modulator and shift register are synchronized with each other and therefore pulse sides are not displaced.

The clock intervals at which the shift register is clocked need not be exactly the same as the first clock intervals of the modulator 30. However, it is preferred that the shift register clock is synchronized with the modulator clock. To avoid loss of information, the shift register clock must operate at a frequency not lower than that of the modulator, but can operate at higher speeds to obtain truly any desired time delay. A suitable way of increasing the frequency of the shift register clock while maintaining synchronization with the first clock intervals of the modulator is to use a frequency divider for the modulator clock. While in the example described above, the desired time-delay in the modulated signal corresponded to an integer number of first clock intervals, this may not always be the case. In order to obtain additional flexibility in the selection of a time delay, it may be desirable to use either a second shift register or additional stages within a single shift register which are clocked at a higher frequency and which therefore introduce increment delays into the modulated signal. The shift register states within element 212 of Figure 11 demonstrate a technique for providing further selectivity in the digital timing of the present invention. In this example, the delayed signal output from any selected stage of shift register 198 is supplied to a second group of shift register stages shown in Figure 11 as a second shift register 212. A number of bistable circuits 216 yield shift register 25 212. The delayed signal from shift register 198 is applied to the input 214 of shift register 102. A clock signal, via line 208, preferably at a higher frequency than the first clock 56, is supplied to the bistable circuits constituting shift register 212. The higher clock frequencies can be conveniently provided by means of an oscillator 220 operating at a higher frequency than the first clock 56. Using an appropriate frequency divider 210, clock signals of different frequencies can be applied to the different shift register stages, as well as 35 to modulator 30, if desired.

8420205 - 35 -

As used herein, the first clock intervals generally refer to the clock signals from the first clock 56 and the second clock intervals will be from the second clock 220. In addition, the shift register stages drawn in Figure 11 may be thought of either as a first shift register 198 and a second shift register 212, or a single shift register with a number of stages which are clocked at different selected frequencies. Either through the use of separate oscillators 10 or a single oscillator with a frequency divider, providing different clock signals increases the flexibility of the digital shifting techniques used in the invention. Delay of a signal with a multi-stage shift register all clocked at the same rate, allows a signal to be delayed by any number of discrete intervals, up to the maximum number of stages in the shift register. By providing additional stages clocked by a different clock signal, additional selected delay intervals can be applied. A signal can be passed through a first shift register and delayed by a certain number of first intervals, and then passed through a second set of shift register stages and delayed by an additional number of second intervals. Thus, a delay of really any desired full or partial inclusion of the first intervals can be made. Corresponding flexibility in signal delays by digital means can be obtained by using a second clock operating at the same frequency as the first clock, but shifted in time by a selected value. For example, if a signal is passed through a first shift register clocked at first intervals and then fed to an additional stage clocked with the inverse of the first interval clock signal, an additional delay of half of a first clock interval will be input. Depending on the shift 35 between the clock signals supplied to the first and second group 8420205 - 36 - of shift register stages, almost any delay value can be entered.

An example of the operation of the modulator and digital time delay devices of Figures 9 and 11 is given in Figure 12. Assumed a first clock signal supplied by clock 56 to be drawn in Figure 12b and a second clock signal supplied by second clock 220 drawn in Figure 10a, a modulated signal input to the shift register will be delayed in the manner described below. In this example, the second clock 220 is exactly twice the frequency of the first clock 56. For example, if a delay in the modulated signal of two and a half first clock intervals is desired, the shift register will be configured to connect 15 output pin 206 "to the second shift register input 214. In this way, a modulated signal input via line 53 will pass through two first shift register stages 200 and 201 and in the first stage of second shift register 212, after which the signal is output at pin 218. The signal 20 will be delayed over two full first clock intervals and an additional second clock interval by such a system Assuming a modulated signal such as occurs in Figure 2c is input to the configuration described above, the output at pin 218 the signal will be drawn in Figure 12d. signal drawn in Figure 12d is exactly the same as the modulated si drawn in Figure 12c, delayed by two and a half first clock intervals.

The digital shifting technique of the present multiplier has the advantage inherent in digital electronics of being relatively drift-free and error-free. In addition, the time setting is made in a manner independent of the signal to be set. In other words, it does not depend on the frequency of the signal 35 for time adjustment. The system shown in Figure 9 8420205 - 37 - allows phase adjustment when multiplying two analog signals without the use of RC networks and their associated signal disturbances. If delta minus sigma modulation is used in the multiplication, the measure of the shift registers used need not be annoyingly large while obtaining a high level of accuracy.

In order to obtain high accuracy from the present power measurement system of the invention over a wide dynamic range, it is important that offset errors are eliminated from the active circuit elements. Shift errors of sufficient strength to adversely affect measurement accuracy are commonly found in low cost operational amplifiers. The 15 'expression voltage shift is generally defined as the voltage difference between a pair of inputs to an active circuit element such as an operational amplifier when the output is zero. It is an erroneous match between the amplifier inputs and the measurement system of the invention includes 20 offset compensation members which correct for such erroneous match.

Figure 13 shows a new shift compensation system as applied to a single amplifier.

The basic theory of the offset compensation system involves the use of a capacitor or other storage element connected to an input of the amplifier and then charged to a compensation voltage. It will be understood that other equivalent systems for storing and supplying a voltage to an amplifier input could be used instead of a capacitor. Operational amplifiers often have more than two inputs and sometimes include one or more inputs specially designated for offset compensation purposes. The invention will work equally well for offset offset amplifiers with additional inputs. Which input is designated for receiving a compensation voltage 8420205 - 38 - for correcting a voltage shift will be the input to which the capacitor is connected. The system further includes means for charging the capacitor to a shift voltage which practically cancels the effect of voltage shift from another amplifier input. For simplicity, only amplifier 70 (Figure 1) is shown in Figure 13, although the offset compensation members of the invention may successively correct a number of amplifiers, as explained below.

The amplifier offset compensating means used in amplifier 70 includes an offset storage element, such as a capacitor, connected to a first selected input 181 of the amplifier. A zero adjustment circuit 182, connected via switches to both the shift collector and the second selected input 183 of amplifier 70, is also provided. Zero setting circuit 182 includes a charge amplifier 184 connected to the second input of amplifiers 70 via a switch A1. The zero setting circuit also includes a temporary storage element, capacitor 186, and a series of switches B, D and E, which connect capacitor 186 to charge amplifier 184 as described below. Additional switches Gj and H ^ connect charge amplifier 184 to a charge circuit which adjusts the voltage stored on capacitor C1.

The line current signal is supplied to the reversing input 183 of amplifier 70, which is ideally an actual ground. Any voltage shift in amplifier 70 will initially act as a voltage on reversing input 183. When capacitor is charged, the voltage on reversing input 183 will increase until a true grounding condition is reached. The difference between the compensation voltage at and the actual voltage shift of amplifier 70 is called an error voltage V. It is error

Disturbance occurs at input 183. It is the object of the offset compensation members of the invention to minimize distortion.

8420205 - 39 -

The shift compensation means includes controls for performing the functions indicated in box 190. Essentially, the control means operates switches A1, B, D, E, G1 and H1 to provide a series of transfer and charge periods in succession. During an initial transfer period, switches A1, B and D are closed and switches E, Gl and HI are open. When switch A1 is closed, power is applied to the non-inversion input of charge amplifier 184, which is configured as a unit amplification amplifier. Switch B which is closed during the transfer periods makes a feedback connection between the output 192 of charge amplifier 184 and the non-reversing input 226. A first terminal 228 of temporary storage capacitor 186 is also connected to the reversing output 226. Switch D 15, when closed, a second valve 230 of capacitor 186 with ground. Thus, during the transfer period, Verrorij amplifier output 192 appears and is stored in temporary storage capacitor 186, along with the voltage shift of charge amplifier 184 (V...,.

* offset amp 184) 20 During a subsequent charge period, controller 190 opens switches A1, B and D and closes switches E, Gl and Hl. This serves to disconnect the second terminal 230 of capacitor 186 from ground and connect it to amplifier output 192, in a second feedback loop. The result is that a voltage-verror occurs at amplifier output 192. The internal shift of the charge amplifier 184a is canceled by the equal and opposite value of the component - V __, ... which becomes 5 r offset-amp 184 is supplied to output 192 of capacitor 186. Closing of switch G1 and opening of switch A1 during the charge period also supplies the voltage at shift storage capacitor C1 to the non-inverse input of charge amplifier 184. Met - V at charge amplifier output 192 error and V at its input (during the charge period) comp 35 a current - I is applied by impedance 224 and switch error 8420205 - 40 -

Hl which sets V in the necessary direction for the reduction of terror during the subsequent transmission period.

Figure 14 shows the operation of the shift compensation members during the start-up conditions. Assume that the voltage V __ ^ „represents the voltage

ofiset — cüüp / U

which is shifted between the inputs of the amplifier 70 and the charge on capacitor C. (V) initially zero isf 1 comp then, during the initial transfer period, verror will be equal to V __. During the subsequent charge J offset-amp 70 10 period, a voltage-error will occur at amplifier output 192. A current-I will then be supplied to 3 error capacitor 186. causing the value of V to increase. The comp voltage V on capacitor C. will serve to practically reduce the offset error of amplifier 70 to the next transfer period. The values of resistor 224 and capacitor C1 are chosen to supply a current - I which does not significantly increase the voltage on capacitor C.

error i will change during every single charge period. Capacitor C1 will therefore not be charged to the full displacement voltage during the first few transfer and charge cycles. When V approaches the voltage (V. _Λ comp offset — amp / 1), V will progressively decrease. Optionally, error 3 3 V will approach a stable minimum value sufficient to correct the error for leakage currents and other transition signals present in the circuit. At that point, the shift errors will really have been eliminated.

Subsequent transfer and charge periods can either follow immediately after previous transfer and charge periods, or be separated by a time delay. In the preferred embodiment, where additional amplifiers are offset in shift using the same zero setting circuit 182, the transfer and charge periods associated with each amplifier are separated by predetermined time intervals. According to Figure 14, the next transfer period shows a V which is smaller as shown at 222.

error 8420205 - 41 -

As before, V is first stored in capacitor 186 and then during the next charge period, a -V appears at the charge amplifier output 192. During error this charge period, the current - ^ error is added to

5 the charge on capacitor C ,, giving the value of V.

1 error is further reduced during the next transfer period. During subsequent cycles, V will appear on capacitor C.

approach comp 1 to the actual voltage shift of amplifier 70 /, reducing V to practically zero.

error e 10 The offset compensation system as described above with regard to amplifier 70 may correspondingly offset offset for a number of amplifier elements. Figure 15 shows the preferred embodiment of the offset compensation system used to provide offset compensation for five different amplifiers. The five amplifiers to be offset shifted by the compensation means of the measuring system are as follows: current signal amplifying amplifier 70, current signal reversing amplifier 74, first modulator integrating amplifier 20 46, Watt output converter integrating amplifier 108 and VARS / Q output converter integrating amplifier 180. Each of the amplifiers corresponds to the amplification amplifiers 70 discussed with reference to Figure 13 in that they all have actual ground inversion inputs to which a signal is applied. 25 Each of these amplifiers includes respective shift collectors, capacitors C. to C ... The non-

1 D

inversion inputs of the amplifiers are connected to the charge amplifier 184 of the zero setting circuit 182 via switches A1 to A5, respectively, as shown in Figure 15. Pairs of 30 switches equivalent to G1 and H1 of Figure 13, namely

G1 to G5 and H1 to H5 connect charge amplifier 184 to the respective shift storage capacitor of each amplifier.

A single zero adjustment circuit 82 will accumulate the error 35 voltage and charge the shift storage capacitor from 8420205 - 42 - each amplifier using the sequence described below. For clarity, the control circuit for operating the various switches in Figure 15 is omitted. A conventional controller of any suitable type can be used to control the switches in accordance with the time diagram drawn in Figure 16.

The controller first closes switches A1, B and D for an initial transfer period for amplifier 70, then opens switches A1, D and B and closes switches E, G1 and HI for a charge period. The controller then forms an additional subsequent transfer and charge period for each of the other amplifiers to be offset. After each charge period of amplifier 70, the transfer period of amplifier 74 begins, in which the controller closes switches A2, 15 D and B and then opens those switches and closes switches E, G2 and H2 during the subsequent charge period. For amplifier 46, switches A3, B and D are closed during the transfer period and switches E, G3 and H3 are closed during the charge period. For amplifier 108, 20 switches A4, B and D are closed during the transfer period and switches E, G4 and H4 are closed during the charge period. Finally, for amplifier 180, switches A5, B and D are closed during the transfer period, and switches E, G5, and H5 are closed during the charge period.

After completing a transfer and charge period for an amplifier, all switches associated with the amplifier, namely switches A, G and H, are left open. The charge stored on the respective shift storage capacitors will remain until the controller sequence provides a new charge period associated with that capacitor. Although some charge drop will occur, errors due to voltage shift are practically reduced for each of the amplifiers. The operating frequency 35 of the controller for opening and closing the switches 8420205 - 43 - associated with the offset compensation members is a matter of design choice, but may be considerably lower than the clocks associated with the measurement system.

The indicated offset compensation system can be used to correct offset errors in any number of amplifier elements associated with a measurement system. A single zero setting circuit such as circuit 182 may be sequentially connected to N amplifier elements and their associated storage elements during a succession of transfer and charge periods. Such a shift compensation system is economical and is ideally suited to the use of CMOS integrated circuit where shift errors can present problems. Although described with reference to the measurement system of the invention, the offset compensation system may equally well be used with other types of power measurement circuits using operational amplifiers. Such a measuring circuit may include, for example, any suitable means for multiplying the analog signals representing current and voltage, as well as any suitable converter or filter circuit for supplying an output signal from the product signal. Assuming that the measurement system uses up to N amplifier elements in its various components, the offset compensation system of the invention can substantially eliminate offset errors in the manner described below.

The N amplifier elements will each comprise a number of inputs. A first selected input in each such amplifier is the input for receiving a compensation voltage for correcting voltage offset. 30 N shift storage elements such as capacitors are also provided. One of the N shift storage elements is connected to the first selected input of each of the N amplifier elements. The shift storage elements receive compensation voltages which practically reduce the shift error at another input of the amplifier element to which it is connected, while the other input is indicated as the second selected input. Any difference between the compensation voltage on the shift storage element and the voltage shift of the amplifier element is an error voltage which occurs at the second selected input of the amplifier element. A zero setting circuit such as circuit 182 is also provided for the power measurement system. The zero adjustment circuit can be sequentially connected to each of the N amplifier elements and to the shift storage element associated therewith. In the following description, the amplifier element to which the zero setting circuit is connected, including its associated storage element, is indicated as the selected amplifier element. In the same manner as the above-described system, the zero setting circuit is first connected to the second input 15 of the selected amplifier element, during an intermediate transmission period. The zero setting circuit is then connected to the shift storage element associated with the selected amplifier element during the intermediate charging period following the transfer period. A control system then connects the zero setting circuit sequentially to the remainder of the N amplifier elements to provide transfer and charge periods for each of the amplifier elements. The sequence is repeated continuously, whereby all amplifier elements receive offset compensation and the offset errors in the measuring system are practically eliminated.

By incorporating the shift compensation members as described above, the measuring system of the invention measures power to a high degree of accuracy over a wide dynamic range. The need for relatively expensive calibrated or error-free amplifiers has been removed, making the measurement system relatively inexpensive. The system provides continuous parallel readings of power in both Watts and VARS or Q. Since the modulator output from modulator 30 is accurately clocked at the first clock 35 intervals, it is possible to manipulate the signal with 8420205 - 45 digital logic . A shift register can easily be used to introduce the time delay necessary to provide an appropriate phase shift for the VARS and O measurement. By simply selecting the appropriate stage in the shift register, the delay in the modulated signal can be adjusted to provide the desired output (VARS or Q, 50 or 60 Hz). Thus, the invention eliminates the need for tuned analog phase shifters to provide the desired voltage lag. Since the output 10 of the modulator can be supplied to both a power converter and a VARS / Q converter, simultaneous readings can be provided with only a single modulator. The system further provides digital outputs for any polarity of power flow on the line. Maximum information is therefore provided with a high degree of accuracy in an efficient and economical manner.

Figure 17 shows part of an alternative embodiment of modulator which is slightly simpler in construction than the modulator 30 of Figure 2. In this embodiment, a capacitor 44 is connected between a summing node 36 and ground. Capacitor 44 serves as the modulator integrator. The inversion input of a comparator 50 is also connected to node 36 with the non-inversion input connected to ground. Comparator 50 forms a control signal due to voltage changes on node 36 coupled to a bistable circuit 52. Circuit 52 is used to control a pair of switches that provide a feedback signal to node 36 as will be described below.

Figure 18 shows various signals provided by the Figure 17 modulator. Input signal V_ is indicated in Figure 18a. Of course, in AC power measurement applications, V will be sinusoidal. Initially, the switch 58 is assumed to be closed and a negative reference current is supplied to summing node 36 35 through resistor 40. The values of VI and resistor 40 are selected to provide a current 1 ^, which is large with respect to the input signal I j. Therefore, will have a net negative value, with current drawn from capacitor 44. Resulting, the integrated differential voltage signal initially decreases as shown in Figure 18c.

Clock 56 supplies a signal drawn at its output in figure 18b. Bistable circuit 52 clocks to the leading edge of each upwardly moving impulse. At clock pulse a, the integrated difference signal of Figure 18c has not yet exceeded the threshold of comparator 15, so that O remains low and Q remains high and the difference signal continues to integrate downward. Since the difference signal is supplied to the reversing input of comparator 50, when the signal exceeds the threshold, the comparator output switches from low to high. The control signal in Figure 18d gives the output of comparator 50. Thus, at clock pulse b, the bistable circuit 52 will change state and O will go from low to high. When Q goes high, Q goes low and switch 60 is closed and switch 58 is opened. A positive reference 20 signal is then applied to sum node 36, thereby integrally increasing to the next clock pulse at c. Between the clock pulses b and c, the integrated difference signal again crosses the threshold of comparator 50, making the first control signal low. Q then goes low at the next clock pulse, again forcing the reference signal to the summing node 36 to become negative. When increases, the slope of the difference signal changes and its value decreases until the threshold level is crossed again. 0 remains low until detecting a change in the first control signal at clock pulse f. Q then becomes high, again switching the reference signal from negative to positive.

The circuit and method described above operate as a delta-minus sigma converter in which only the difference between the input and reference signals is integrated and measured. The circuit always keeps the integrated difference signal around the threshold level of comparator 50. The Q output of bistable circuit 52 is selected as the first output signal with an average level or amplitude over time, proportional to the value of V.

J_l

Figure 19 shows a modulator circuit as in Figure 17 which includes an alternative shift compensation system. In this embodiment, comparator 15, which is an operational amplifier element, is provided with compensation means for practically eliminating any offset error resulting from a voltage offset consisting of amplifier inputs 306 and 308. As described above, a voltage offset is generally determined as the voltage required between inputs of an amplifier to provide a zero output. Ideally, the voltage shift is zero, but most actual operational amplifiers usually have a shift of unknown value. In the invention, a first storage element such as capacitor 302 is connected to the amplifier inputs and a shift voltage practically equal to the voltage offset of the amplifier is stored in the voltage shift compensation element. In the example of Figure 19, capacitor 302 is located in the electrical path between summing node 36 and inverter amplifier input 306.

It should be understood that capacitor 302, like capacitor 44 and the other storage elements used in the embodiments described below, represents some kind of storage element that can be used and that other types of circuit elements such as registers with DA converters and the like could are used for the various storage elements in the present invention.

The offset compensation system also includes a feedback loop 300, which is intermittently connected around amplifier 50, between reversing input 306 and amplifier 35 output through switch C. When switch C is closed, voltage difference occurs at a low impedance on input 306 to store the voltage supplied by the feedback loop on capacitor 302, switches A and B are provided to break an end of the capacitor from summing node 36 and connect it to the common ground 305.

The means for controlling the offset compensation system of Figure 19 are the clock 56 and Figure 20 shows the control function. The bistable circuit 52 clocks 10 at the leading edge of each clock cycle, as indicated by arrows 312. Each upward movement pulse represents a clock pulse. Just when the clock signal starts going from low to high, switches B and C are turned off and switch A is turned on, meaning that the feedback loop 15 around amplifier 50 is broken and capacitor 302 is connected to summing node 36. As soon as the clock pulse begins switches B and C are turned on and switch A is turned off, connecting the feedback loop around the amplifier and connecting a terminal of capacitor 302 to ground. During this period, called the zero setting period, the voltage offset + offset of amplifier 50 occurs at input 306. Since capacitor 302 is connected between input 306 and ground, the voltage + V_ offset is stored in the capacitor. During the last half of each clock cycle, called the measurement period, switches B and C are turned off and switch A is turned on.

With non-inversion input 308 connected to ground, the error at inversion input 306 is the negative value of the voltage offset - offset. Thus, the signal is compared to the threshold level by comparator 50 when A is closed and B

and C are open, the voltage at summing node 36, the integrated difference signal, plus + plus - vffff ^ The voltage shift of comparator 50 is thereby eliminated and the error that will otherwise be supplied at the threshold measurement 35 is essentially eliminated.

8420205 - 49 -

Another embodiment of the modulator using a shift compensation system is shown in Figure 21. In this embodiment, the measuring device 298 has first and second amplifier elements 328 and 336, respectively, which serve as comparators and which are alternately connected between summing node 36 and bistable circuit 52. First amplifier 328 includes switchable feedback loop 324 which connects output 330 to reversing input 326 via switch D. A first capacitor-shaped capacitor 316 is connected to the electrical path between summing node 36 and reversing input 320 via switch E. A path is formed between a terminal 318 of capacitor 316 and ground through switch F. Second amplifier element 336 also includes a switchable feedback loop 332 connected between output 15 338 and reversing input 334 via switch G, and a collection element such as capacitor 320 is in the electrical lane between reversing entrance 334 and summing node 36 via switch H. A path between a terminal 322 of capacitor 320 and ground is formed via switch J.

The embodiment of Figure 21 is designed to provide two parallel offset compensated comparator circuits for measuring the integrated verachil signal at summing node 36. When switches E and K are closed, first amplifier element 25 328 supplies the first control signal to bistable circuit 52 and when switches H and L are closed, the second amplifier element 336 supplies the first control signal to bistable circuit 52. By closing switches E, G, J and K and opening switches D, F, H and L, the first amplifier element 328 is formed in a measurement mode whereby the control signal is supplied to the bistable circuit 52, and the second amplifier element 336 is in a zero setting mode where the voltage shift of the amplifier element 336 is stored in capacitor 320. Storage of V . in condensa offset 35 tower 316 and 320 is performed in exactly the same way 8420205 - 50 - as with amplifier element 50 and capacitor 302 in the embodiment of figure 19. By reversing all switches, i.e. closing switches D, P, H and L and opening switches E, G, J and K, amplifier 328 is zero. 5 mode and is the amplifier 336 in the measurement mode where the integrated difference signal on summing node 36 is supplied to reversing input 334 via capacitor 320, compensating for the voltage shift of amplifier 336 and providing an error-free first control signal to the D input of the bistable chain 52.

An advantage of the embodiment of Figure 21 over that of Figure 19 is that a offset compensated amplifier is available at any time in its measurement mode. Furthermore, switching between 15 measurement and zero setting modes in the embodiment of Figure 19 was done with the clock frequency of the clock 56. If the sample frequency as determined by the frequency of the clock 56 is large, the amplifier elements serving as comparators will not be able to stabilize after every zero-setting period and errors will be entered. The embodiment of Figure 21, which uses conventional control logic to operate switches D, E, F, G, H, J and L, represented by element 340, can operate at a frequency different from the clock 56. A conventional frequency divider can be used to reduce the frequency of control actions, for example.

In order to ensure that sufficient time is created for the amplifiers in the embodiment of Figure 21 to stabilize after each zero setting period, control 30 extends logic 340, which serves as control for operating switches D, E, F, G, H, J, K and L, the measurement period for each amplifier element for allowing time for stabilization. Figure 22 shows the time diagram for the operation of switches D, E, F, G, H, J, K and L through the control logic 340.

Switches K and L, which connect the outputs of the first and second 8420205-51 amplifier elements to bistable circuit 52, respectively, are out of phase to each other. Switch K is turned on half the time and off half the time, and switch L is turned off when K 5 is turned on and vice versa. In addition to controlling the switches connecting the amplifiers to the bistable circuit 52, the control logic 340 also controls the switches that determine the zero setting and measuring periods of amplifiers 328 and 336. Switches D, E and F serve to connect the feedback loop around amplifier 328 and connect one terminal 318 of capacitor 316 to ground in exactly the same way as the embodiment of Figure 19. Switches G, H and J perform the same function for amplifier 336. As can be seen from Figure 22, the amplifier mull set and measure periods 15 of each amplifier element are not of the same duration. For example, the zero setting period for the first amplifier 328 begins when switch K is turned off and ends before switch K is turned on again. Accordingly, the zero setting period of second amplifier 336 begins when switch L 20 is turned off and ends before switch L is turned on again. Thus, the zero setting period of each amplifier is shorter than the measuring period over a predetermined interval.

This is done to allow time for the amplifiers to stabilize before they are connected to the bistable circuit 52.

It should be noted that outside of allowing additional time for amplifier stabilization prior to connecting either the first or the second amplifier to the bistable chain, the control logic 340 is inherently slower than clock 56. As shown in Figure 22, the clock signal, not drawn to scale, at a considerably higher frequency than any switch in Figure 21. The control logic 340 preferably includes a frequency divider for this purpose. Thus, the embodiment of Figure 21 can be used with a relatively high frequency clock, for example 10 kHz, 8420205 - 52 - to provide frequent sampling and relatively high resolution, while zero adjustment and shift compensation work for the amplifier elements at a sufficiently low frequency for minimizing errors due to slow amplifier response.

The method according to the invention performed with the embodiment of figure 21 comprises an extra step in the measuring step, for switching between the first and second amplifier elements 328 and 336, respectively. The compensating step includes measuring with the first amplifier element and zero setting of the second amplifier element and then measuring with the second amplifier element and zero setting of the first amplifier element, in a continuous cycle, so that at least one of the offset compensated amplifier elements is connected to the summation node at any time. In the preferred embodiment of the method, the zero adjustment periods and measurement periods are different and preferably slower than the clock intervals. Furthermore, the zero adjustment periods are shorter than the measurement periods for each amplifier element, in accordance with the timing diagram of Figure 22. The measurement period of one amplifier element is started before the end of the measurement period of the other amplifier element such that any error due to slow response of comparison by the first of the amplifier elements if this is initially switched from zero setting to measuring is eliminated.

Operation of the embodiment of Figure 21 will yield the results drawn in Figure 18. Assuming that V is as shown in Figure 18a, then the integrated 30 will be the difference signal occurring at summing node 36 shown in Figure 18c. Both the first control signal of Figure 18d and Q output of Figure 18e will remain unaffected by the interrupted operation and cyclical zero and measurement periods of amplifiers 328 and 336. The embodiment 35 of Figure 21 provides greater accuracy at higher clock rates. frequencies, but is otherwise functionally identical to the embodiment of Figure 19.

Modulator 30 used in the measurement system of Figure 1, can be used in other applications where it is necessary to provide modulated output signals indicative of the polarity of the input signal. In Figure 23, an alternative embodiment of modulator can be seen which provides such output signals. Input signal I ^ is supplied to summing node 36 through resistor 38. One of the two reference signals, which are, for example, of equal strength and opposite polarity, is also supplied to the summing node via resistor 40. The reference voltages V1 and V1 + are connected to the summing node via a pair of switches 58 and 60, respectively, which are controlled by the modulator output. Momentary differences between input current Ij and feedback current I_ at node 36 are supplied to an integrator which provides an increasing or decreasing ramp voltage. The integrated signal is then compared to the threshold level of a comparator 50, which provides an output control signal indicating whether the integrator output is above or below the threshold level. The output of comparator 50 is applied to a bistable circuit, such as flip-flop 52.

The bistable circuit changes state only at predetermined clock intervals as determined by clock 56. When the integrated signal crosses the threshold level of comparator 50, the outputs of the bistable circuit 52 reverse state at the next clock pulse. The Q output of the bistable circuit 52, which is the first modulated signal of the invention, controls switch 60, which connects the positive reference voltage V1 + to sum node 36. The Q output which is always the inverse of the Q output , operates switch 58, connecting the negative reference voltage V1- to the summing node 8420205-54 - point 36. Switches 58 and 60 are always operated alternately, which means that one or the other of the reference signals is always supplied to the summation node 36.

The Q output of the bistable circuit 52 is connected to the D input of a second bistable circuit 53 and both receive clock signals from the same clock 56. Due to gate delays, changes in the Q output of the bistable circuit 53 will always change in the 10 Q output of the bistable circuit 52 delayed by a clock pulse. An AND gate 350 is also provided to receive the Q outputs from both bistable circuits 52 and 53, as well as a clock signal from clock 56. The AND gate serves as an output means for a first digital signal proportional to the strength of a polarity of the input signal.

Figure 24 shows the operation of the above-described chain elements. Assuming for purposes of explanation that the voltage waveform at node 32 is supplied to the alternative embodiment of modulator as shown in Figure 24a, the signal is converted into a first modulated signal at the Q output of the bistable circuit 52 in the manner as described above. The Q output of the bistable circuit 52 is assumed to be that drawn in the wave | form of figure 24d. The output of the clock 56 is represented by the waveform of Figure 24b. The output of the second bistable circuit 53 is indicated as "delayed Q" and is represented by the waveform of Figure 24e. Delayed Q is practically equal to 0, but delayed in time over a clock interval. The present invention is directed to combining Q, delayed Q and a clock signal at an AND gate 350 (see Figure 23).

Although not necessary in idealized circuits in which component delays do not exist, for actual components it is preferred to insert a reverser 35 57 between clock 56 and AND gate 350. Inverter 8420205 - 55 - 57 reverses the clock signal to obtain a reverse clock signal drawn in Figure 24c. The reason for supplying a reverse clock signal to the AND gate is because of propagation delays in bistable chains 52 and 53 which can cause their outputs to lag slightly behind the clock 56 output and briefly provide simultaneous "high" conditions on all three. signals at the wrong time. The result of non-reversal of the clock is an excessive spike output from AND gate 350, which would display an error IM-10 pulse. For this reason, the inverter 57 is included in Figure 23. The resulting waveform output of AND gate 350 is shown in Figure 24f.

The Figure 24f waveform is essentially a digital representation of the value by which the time that Q is high is greater than the time that 0 is low. In the example of Figure 24, waveform 24f includes only two pulses, generated successively, and appearing on the right side of the drawing. These two impulses roughly coincide with the region where the Figure 24a input is the most negative. Preferably, the frequency of the clock will greatly exceed the variations of the analog input signal, to provide higher resolutions than those shown in Figure 24. The principle of operation is exactly the same, however. Essentially, combining a delayed modulated signal with the original modulated signal at an AND gate provides an output which becomes high only when Q remains high for at least two subsequent clock pulses. The clock signal causes the AND gate output to be a pulse train, with pulses at intervals no less than the clock intervals of the clock signal. In the example just described, the AND gate supplies output pulses only when the signals applied thereto are high. If Q is low for two or more consecutive clock pulses, this will have no effect on the output of AND gate 350 since only high inputs are measured.

Thus, the output of the AND gate represents the strength of H20205 - 56 of only one polarity of the input signal. The output is in fact a single rectified signal, digitized.

In order to provide a digital output proportional to the other polarity of the input waveform, the alternative execution modulator uses the Q outputs of bistable circuits 52 and 53 as the first and second inverse modulated signals, respectively. Assuming that the same input signal and clocks as shown in Figure 24 occur, Q will be as shown in the waveform of Figure 24g. Bi-stable circuit 53 provides a delayed Q signal as shown in Figure 24h. Both signals are applied to a second AND gate 352 (Figure 23) together with the reverse clock signal drawn in Figure 24c. The output of the second EN-15 gate 352 is drawn with the waveform of Figure 24i and is called a second digital signal. The second AND gate serves as a means of supplying a second digital signal to the output, which contains pulses in proportion to the amount of time by which one level of the first reverse modulated signal is greater than the other level. When all three inputs to the AND gate are high, pulses are delivered at intervals not less than the clock intervals of the clock 120. In the present example, the waveform 24i represents the positive polarity component of the input signal. As can be seen, the location of the pulses roughly corresponds to the areas where the figure 24a input signal is high. The Figure 24i waveform provides a digital representation of the strength of the positive half-wave components of the input signal.

According to Figure 23, the present invention can be further used to provide a digital signal proportional to the strength of the full waveform of the input signal. This is accomplished by supplying the first digital signal output from AND gate 350 and the second digital signal output from AND gate 352 to an OR gate 2, which serves as gate for combining the digital signals and outputting a sum digital signal drawn in Figure 24j. The figure 24j waveform is proportional to the strength of the full input signal, including both polarities, which is expressed as "absolute strength". The outputs of AND gates 350 and 352 are coupled to up and down inputs of an up / down counter 354 so that the number of positive and negative pulses can be compared during each selected time interval.

8420205

Claims (75)

Measuring system for measuring electric power conducted along a line, characterized in that means are provided for testing current and voltage signals on the line, provided with first signal means for supplying a first analog signal proportional with one of the current and voltage signals and second signal means for supplying a second analog signal proportional to the other of the current and voltage signals, modulator means for converting one of the analog signals into a first modulated signal changeable between two levels at predetermined first clock intervals in a manner proportional to said one of the analog signals, first multipliers including gate operation means of the other 15 of the analog signals responsive to the first modulated signal for multiplying the analog signals by each other and supplying a product signal proportional to the power fed ov there is the line, and first converters for converting the product signal into a first output signal which is modulated in a manner proportional to the value of the product signal and with the power passed over the line. Measuring system according to claim 1, characterized in that the modulator means delivers the first modulator-25 the signal via a bistable circuit changeable at the first clock intervals, the modulator means further comprising modulator feedback means for providing a feedback signal that changes values simultaneously with changes in the first modulated signal 30 and one of the analog signals balances over time, and a modulator measuring circuit for currently measuring differences between the feedback signal and the one of the analog signals and outputting a signal indicating such difference to the bistable circuit such that the first 35 modulated signal levels change due to the measured difference between one of the analog signals and the 8420205 - 59 feedback signal. Measuring system according to claim 2, characterized in that the modulator means comprises a modulator sum node where one of the analog signals and the feedback signal are combined, while the modulator measuring circuit comprises an integrator for integrating the signal at the modulator sum node and a comparator for comparing the integrated value provided by the integrator with a predetermined modulator threshold level. Measuring system according to claim 2, characterized in that the first converters supply the first output signal via a bistable circuit with an output changeable between two levels at predetermined turnover organ clock intervals, the first converters further comprising means for supplying from the product signal to a summing node, feedback means responsive to the first output signal for supplying a second signal to the summing node which balances the product signal over time, while the second signal is determined by the level of the first output signal, wherein each current difference between the product signal and the second signal is a difference signal occurring at the summing node, and a measuring circuit for integrating the difference signal and for comparing the integrated difference signal with a first threshold level while outputting the measuring circuit is fed to d The bistable circuit causing the first output signal to be at one of two levels depending on the level of the integrated difference signal relative to the first threshold level at each converter clock interval, so that the average level over time for the first output signal is proportional to the product signal and with the power carried over the line. Measuring system according to claim 1, 84 2.0: 60, characterized in that the first analog signal is proportional to the voltage signal and the second analog signal is proportional to the current signal. Measuring system according to claim 1, 5, characterized in that the first converter supplies the first output signal via a bistable chain, changeable at the converter clock intervals, the first converter further comprising means for supplying the product signal to a summing node feedback means responsive to the first output signal for supplying a second signal to the summing node which balances the product signal over time, the second signal being determined by the level of the first output signal, wherein any current difference between the product signal and the second signal is a difference signal occurring at the summing node, and a measuring circuit for integrating the difference signal and for comparing the integrated difference signal with a first threshold level, while the output of the measuring circuit is supplied to the bistable circuit, whereby is causing it first output at one of the two levels is dependent on the level of the integrated difference signal from the first threshold level at each converter clock interval such that the average level over time for the first output signal is proportional to the product signal and power fed across the line. Measuring system according to claim 6, characterized in that the product signal is predominant of first polarity when power on the line is of first polarity, wherein the predominant direction of power flow is in a first direction, the feedback means are provided with a first reference source used when power is on the line of the first polarity, while the first reference source has a polarity opposite to the first polarity and a strength sufficient to balance the product 8420205 - 61, while the first reference source is used interrupted as the second signal when the first output signal is at a level for driving the integrated difference signal over the first threshold in a 5 direction, and further includes a second reference source which is alternately used as the second signal when the first output signal on the the other of the two levels is for allowing da the integrated difference signal crosses the first threshold level in the other direction such that the integrated difference signal is maintained in the vicinity of the first threshold level when power on the line is of first polarity. 8. Measuring system according to claim 7, characterized in that first digital gate means are present for receiving the first output signal and for supplying a first pulse series with a pulse speed proportional to the first output signal. 9. Measuring system according to claim 7, characterized in that the product signal predominantly of a second polarity is opposite to the first polarity when power on the line is of a second polarity, the predominant direction of power flow being in a second direction opposite to the first direction, wherein the converters are provided with means for comparing the integrated difference signal with a second threshold level, the converters are provided with a second bistable circuit for delivering a second output signal at one of the two levels depending on the level of the integrated difference signal from the second threshold level at each converter clock interval, the feedback means including a third reference source used when power is on the line of the second polarity, the third reference source having a polarity opposite to the second polarity and a magnitude sufficient to balance the product signal, while the third 8 * 20205 - 62 reference source interrupted is used as the second signal when the second output signal is at a level driving the integrated difference signal over the second threshold level in one direction and further comprising a fourth reference source which is alternately used as the second signal when the second output signal is at the other of the two levels to allow the integrated difference signal to cross the second threshold level in the other direction such that the integrated difference signal 10 is maintained in the vicinity of the second threshold level when power on the line is of second polarity. Measuring system according to claim 9, characterized in that the second and fourth reference sources have the same value. Measuring system according to claim 10, characterized in that the second and fourth reference sources both form connections to a common ground for the measuring system, and the first output signal is proportional to the first polarity of power flow and the second output signal is proportional to the second polarity of power flow on the line. 12. Measuring system according to claim 9, characterized in that second digital gate members are present for receiving the second output signal and for supplying a second pulse train with a pulse frequency proportional to the second output signal. Measuring system according to claim 12, characterized in that first digital gate means are present for receiving the first output signal and for supplying a first pulse train with a pulse frequency proportional to the first output signal and provided with counting means for receiving the first and second pulse trains and for counting the pulses therein for determining the power flow on the line. Measuring system according to claim 1, 8420205 - 63 - characterized in that means are provided for supplying the other of the analog signals in both inverted and non-inverted forms, the inverted and non-inverted forms of the others of the analog signals are applied to the multipliers, while the multipliers further include switching means for supplying the inverted and non-inverted forms of the other analog signal to a common point alternately due to the first modulated signal. forming the product signal. Measuring system according to claim 1, characterized in that phase shifters are provided for adjusting the phase relationship between the signals supplied to the multipliers such that the product signal is proportional to a selected phase relationship power value of the power carried at the line. Measuring system according to claim 15, characterized in that the phase-shifting members form a time-delay member which delays one of the signals delivered to the multipliers over a selected time interval. Measuring system according to claim 1, characterized in that a shift register is provided for delaying the first modulated signal by a selected time interval such that the phase relationship between the signals multiplied in the measuring system is changed to measure a selected phase relationship power value, wherein the shift register receives the first modulated signal and delivers a delayed first modulated signal 30 delayed in time by a selected interval. Measuring system according to claim 17, characterized in that the delayed first modulated signal and the other of the analog signals are supplied to a second multiplier provided with gate operation means of the other of the analog signals 8420205 - 64 due to the delayed first modulated signal for multiplying the signals with each other and supplying a second product signal proportional to a selected phase relationship power value of the power passed across the line, and provided with second converters for converting the second product signal in a phase relationship first output signal which is modulated in a manner proportional to the value of the second product signal and to the selected phase relationship power value of the power supplied on the line. Measuring system according to claim 1, characterized in that at least one of the test members, modulator members and first converting members is provided with N amplifier elements, each with a number of inputs, the system being provided with shift compensation members for the mash-15. optically eliminating errors due to voltage offset between selected inputs of each of the N amplifier elements while the offset compensation members are provided with N offset storage elements connected to a selected first input of each amplifier element for receiving a compensation voltage which is practically the reduces offset error at a selected second input of the amplifier element, where any difference between the compensation voltage and the voltage offset of the amplifier element is an error voltage that occurs at the second input, and a zero adjustment circuit is provided which can be connected successively to each of the N amplifier elements and with the shift storage element associated therewith so that each amplifier element subsequently becomes the selected amplifier element to be offset in shift, the zero-30 adjustment circuit first being connected to the second input of the selected amplifier element during an interrupted transmission period to determine the error voltage and then connected to the shift collector connected to the first input of the selected amplifier element for transferring charge to the shift collector during an interrupted transfer period following the charge period, wherein the shift compensation means are provided of means for sequentially supplying the transfer and charge periods for each of the N amplifier elements 5 such that offset errors in the measurement system are practically eliminated. Measuring system according to claim 19, characterized in that the zero setting circuit comprises a charge amplifier, a temporary storage element connected to the charge amplifier, and means for transmitting the error voltage from the second input of the selected amplifier element via the charge amplifier. to the temporary storage element during the transfer period. 21. Measuring system according to claim 20, characterized in that the temporary storage element has first and second connection members and the displacement compensation members are provided with means for connecting the first clamp of the temporary storage element with a feedback loop between an input and the output of the charge amplifier 20 and for connecting the second terminal of the temporary storage element to a common ground during each transfer period such that the fault voltage is transferred to the temporary storage element, and provided with means for disconnecting the second connecting means 25 from the common ground and for connecting this second terminal to the output of the charge amplifier during each successive charge period such that a voltage proportional to the error voltage of the selected amplifier element occurs at the output of the charge amplifier during the charge period. Measuring system according to claim 21, characterized in that the shift compensation means further comprises means for connecting the output of the charge amplifier to the shift collecting element connected to the selected amplifier element during 8420205 - 66 - the charge period such that a current is supplied to the shift storage element proportional to the error voltage of the selected amplifier element to thereby adjust the voltage on the shift storage element in a direction which reduces the error voltage during the next transfer period of the selected amplifier element. Measuring system for measuring electric power conducted along a line, characterized in that means are provided for testing current and voltage signals on the line and for supplying a first analog signal and proportional to one of the current and voltage signals and a second analog signal proportional to the other of the current and voltage signals, means for multiplying the first and second analog signals with each other to provide a product signal proportional to the power transported on the line, and means for converting the product signal into an output signal proportional to the value of the product signal and with the power passed over the line and comprising N amplifier elements each having a plurality of inputs in at least one of the test, multiply multipliers and converters, a shift compensation system for practically eliminating errors due to voltage shift between g selected inputs from each of the N amplifier elements, wherein the offset compensation system includes N offset storage elements, one of which is respectively connected to a selected first input of each amplifier element to receive a compensation voltage which practically reduces the offset voltage at a selected second input of the amplifier element 30, wherein any difference between the compensation voltage and the voltage shift of the amplifier element is an error voltage which occurs at the second input, and includes a zero adjustment circuit which can be successively connected to each of the N amplifier elements and the shift storage -35 element associated therewith so that each amplifier element subsequently becomes the selected amplifier element to be offset shifted, while the zero setting circuit is first connected to the second input of the selected amplifier element for a period of time. n interrupted transfer period for determining the error voltage and then connected to the shift storage element connected to the first input of the selected amplifier element for transferring charge to the shift storage element during an interrupted charge period following the transfer period, while the shift compensation system includes means for sequentially supplying transfer and charge periods for each of the N amplifier elements such that offset errors in the measurement system are practically eliminated. Measuring system according to claim 23, characterized in that the zero setting circuit comprises a charge amplifier, a temporary storage element connected to the charge amplifier and means for transferring the error voltage from the second input of the selected amplifier element to the charge amplifier. the temporary storage element 20 during the transfer period. 25. Measuring system according to claim 23, characterized in that the temporary storage element in the shift compensation system is provided with first and second connection members and the shift compensation system is provided with means for connecting the first connection member of the temporary storage element. with a feedback loop between an input and the output of the charge amplifier and for connecting the second terminal of the temporary storage element to a common ground during each transfer period, such that the error voltage is transferred to the temporary storage element, and provided with means for disconnecting the second connector from the common ground and for connecting the second connector to the output of the charge amplifier during each successive charge period such that 8420205 - 68 - a voltage proportional to the error voltage of the selected amplifier elements t occurs at the output of the charge amplifier during the charge period. 26. Measuring system according to claim 25, characterized in that the offset compensation system further comprises means for connecting the output of the charge amplifier to the offset storage element connected to the selected amplifier element during each charge period such that a current is supplied to the shift storage element proportional to the error voltage of the selected amplifier element to thereby adjust the voltage on the shift storage element in a direction that reduces the error voltage during the next transfer period of the selected amplifier element. 27. Shift compensation system for a number of amplifier elements up to N amplifier elements each with a number of inputs for practically eliminating errors due to voltage shift between selected inputs of each of the amplifier elements, characterized in that N storage elements are connected to the N amplifier elements so that one of the storage elements is connected to a selected input of each amplifier element, the collection elements serving to receive a compensating voltage which practically reduces the displacement error at a selected second input of the associated amplifier element and any difference between this compensation voltage and the voltage shift of the amplifier element occurs as an error voltage at the second input, and includes a zero adjustment circuit which can be connected successively to each of the 30 N amplifier elements and to the associated storage element such that each amplifier element t subsequently the selected amplifier element to be offset compensated with the zero adjustment circuit first connected to the second input of a selected amplifier element during an interrupted transmission period to determine the error voltage 8420205-69 and then connected to the storage element with the first input of the selected amplifier element for transferring charge to the storage element during an interrupted charge period following the transfer period, wherein the shift compensation system includes means for sequentially supplying transfer and charge periods for each of the N amplifier elements such that offset errors at the second input are practically eliminated. 28. Shift compensation system according to claim 27, characterized in that the zero setting circuit comprises a charge amplifier, a temporary storage element connected to the charge amplifier, and means for transferring the error voltage from the second input of the selected amplifier element to the charge amplifier. the temporary storage element during the transfer period. 29. Shift compensation system according to claim 27, characterized in that the temporary storage element in the shift compensation system is provided with first and second connecting members and the shift compensation system is provided with means for connecting the first connecting member of the temporary storage element with a feedback loop between an input and the output of the charge amplifier and for connecting the second terminal of the temporary storage element to a common ground during each transfer period such that the error voltage is transferred to the temporary storage element, and provided with means for disconnecting the second terminal from the common ground and for connecting this second terminal to the output of the charge amplifier during each subsequent charge period such that a voltage proportional to the error voltage of the selected amplifier element occurs at the output of the charge amplifier during the charge period. 30. Shift compensation system according to 8420205 - 70 - claim 29, characterized in that further means are provided for connecting the output of the charge amplifier to the storage element connected to the selected amplifier element during the charge period so that a current is supplied. to the storage element proportional to the error voltage of the selected amplifier element to thereby adjust the voltage on the storage element in a direction which reduces the error voltage during the next transmission period of the selected amplifier element. 31. A method of measuring electric power passed along a line, characterized in that the steps are taken of testing current and voltage on the line and supplying a first analog signal proportional to one of the current and voltage signals and supplying a second analog signal proportional to the other of the current and voltage signals, modulating one of the analog signals to supply a first modulated signal proportional to one of the analog signals, which is changeable between two levels at predetermined first 20 clock intervals, gating the other of the analog signals due to changes in the level of the first modulated signal for multiplying the signals with each other and providing a product signal proportional to the power passed across the line, and converting the product signal into a first output signal which is modulated in a manner equal to proportional to the Value of the product signal and the power carried across the line. 32. A method according to claim 31, characterized in that the modulation step consists of supplying a feedback signal that changes its value simultaneously with changes in the first modulated signal and balances one of the analog signals over time, and measuring instantaneous differences between the feedback signal and one of the analog signals and supplying a signal for indicating such difference to a bi-8420205 - 71 stable circuit which delivers the first modulated signal at one of the two levels depending on the measured difference between the feedback signal and one of the analog signals at each first clock interval. 33. A method according to claim 32, characterized in that the modulation step consists of supplying one of the analog signals and the feedback signal to a summing node, and the measuring step comprises integrating the signal at the summing node for displaying of the difference between one of the analog signals and the feedback signal, and then comparing the integrated value provided by the integrating step with a predetermined modulator threshold level. 34. A method according to claim 31, characterized in that the step of converting the product signal consists of supplying the first output signal through a bistable chain with an output changeable between two levels at predetermined converter clock intervals, providing the product signal to a summing node, supplying a second signal to the summing node from a number of reference sources due to the level of the first output signal, the second signal balancing the product signal over time and any current difference between the product signal and the second signal is a difference signal and the integrated difference signal is compared to a first threshold level and then the bistable circuit is forced to supply the first output signal at one of the two levels depending on the level of the integrated difference signal relative to the first 30 level at any sales body clock interval. A method according to claim 34, characterized in that the product signal is predominant of first polarity when power on the line is of a first polarity wherein the predominant direction of power flow is in a first direction, while the converting step is 8420205 - 72 - From supplying the second signal to the summing node from a first reference source with a polarity opposite to the first polarity and a magnitude sufficient to balance the product signal, using the first reference source as the second signal when the first output signal is at a level for driving the integrated difference signal over the first threshold level in one direction, and alternating the first reference source with a second reference source when the first output signal is at the other of the two levels allowing the integrated difference signal to cross the first threshold level i n the other direction, such that the integrated difference signal is maintained in the vicinity of the first threshold level when power on the line is of first polarity. 36. A method according to claim 35, characterized in that the product signal predominantly of a second polarity is opposite to the first polarity when power is on the line of a second polarity where the predominant direction of power flow in a second direction is opposite to the first direction is, while the converting step consists of comparing the integrated difference signal with a second threshold level different from the first threshold level, and outputting a second output signal through the second bistable circuit outputting the second output signal on one of the two levels depending on the level of the integrated difference signal relative to the second threshold level at each converter organ clock interval, and supplying the second signal 30 from a third reference source when power is on the line of second polarity, the third reference source having a polarity opposite to the second po larity and strength sufficient to balance the product signal, while the third reference source is used as the second signal when the second output signal is at a level 8420205 - 73 - for driving the integrated difference signal over the second threshold level in one direction, and alternating the third reference source with a fourth reference source when the second output signal is at the other of the two levels to allow the integrated difference signal to cross the second threshold level in the other direction, so that the integrated difference signal is maintained in the vicinity of the second threshold level when power is on the line of the second polarity. A method according to claim 36, characterized in that the second and fourth reference sources are the same and the converting step consists of supplying the second signal to the summing node from one of the first, third and equal second and fourth reference sources. A method according to claim 31, characterized in that the other of the analog signals is inverted and both the inverted signal and the non-inverted other of the analog signals are both supplied to means for performing the gating step. 20 A method according to claim 31, characterized in that use is made of N amplifier elements each with a plurality of inputs for performing at least some of the steps of the method and providing the additional steps of offset compensation at the N 25 amplifier elements for eliminating errors due to voltage shift between selected inputs of each of the N amplifier elements, each of the amplifier elements being respectively connected to a shift storage element at a first selected input thereof in which a compensation voltage is stored by the shift compensation steps of the method for practically correcting each offset error at a second selected input of the amplifier element, and wherein any difference between the compensation voltage in the offset storage element and the voltage shift of the amplifier element is an error voltage 8420205 - 74 edt on the second input, while the offset compensation steps consist of sequentially connecting a zero adjustment circuit to each of the N amplifier elements and to the offset storage element associated therewith to compensate for offset at each selected amplifier element in sequence by means of the offset input circuit. shift compensation steps, consisting of first connecting the zero adjustment circuit to the second input of the selected amplifier element during an interrupted transmission period for determining the error voltage and then connecting the zero adjustment circuit to the shift storage element connected to the first input of the selected amplifier element during an interrupted charge period following the transfer period for adjusting the charge on the shift storage element during the charge period such that the error voltage is reduced during the next transfer period of the selected amplifier element e n with the steps of successively ensuring transfer and charge periods for each of the N amplifier elements in a continuous cycle. 40. A method according to claim 39, characterized in that the zero setting circuit comprises a charge amplifier and a temporary storage element with first and second connecting means, the shift compensation steps comprising connecting an input of the charge amplifier to the second input. of the selected amplifier element and connecting the first terminal of the temporary storage element in a feedback loop between an input and an output of the charge amplifier during each transfer period, and simultaneously connecting the second terminal of the temporary storage element to a common ground during that transfer period such that the error voltage is transferred through the charge amplifier to the temporary storage element, and then the second terminal is disconnected from the common ground and connected to the output of the charge 8420205-75 amplifier during e the subsequent charge period whereby a voltage proportional to the error voltage occurs at the output of the charge amplifier during the charge period. 41. A method according to claim 40, characterized in that the offset compensation steps further comprise connecting, during each charge period, the output of the charge amplifier to the offset storage element connected to the selected amplifier element via an impedance such that a current is supplied to the shift storage element proportional to the error voltage to thereby adjust the voltage on the shift storage element in a direction which reduces the error voltage during the next transfer period of the selected amplifier element. 42. A method of measuring electric power passed along a line, characterized in that the current and voltage on the line are tested, a first analog signal is formed proportional to one of the current and voltage signals and a second analog signal proportional to the other of the current and voltage signals, multiplying the first and second analog signals together to provide a product signal proportional to the power passed across the line, converting the product 25 into an output signal proportional with the value of the product signal and the power passed across the line, the measurement system for performing the method includes N amplifier elements each having a plurality of inputs, while N amplifier elements are used to output at least some of the steps of the method, and consists of the additional steps of offsetting the N amplifier elements for shifting r eliminating errors due to voltage shift between selected inputs of each of the N amplifier elements, each of the amplifier elements being respectively connected to 8420205 - 76 - a shift storage element at a first input thereof on which a compensation voltage is stored by the offset compensation steps of the method for practically correcting each offset error at a second input of the amplifier element, and wherein any difference between the compensation voltage on the offset storage element and the voltage offset of the amplifier element is an error voltage occurring at the second input, which offset compensation voltages consist of sequentially connecting a zero setting circuit to each of the N amplifier elements and to the shift storage element associated therewith to compensate for shift in each selected amplifier element in sequence, consisting of the first connecting the zero adjustment circuit to the second input of the selected amplifier-15 element during an interrupted transmission period to determine the error voltage, then connecting the zero adjustment circuit to the displacement storage element connected to the first input of the selected amplifier element during an interrupted charging period following the transfer period 20 for setting the charge on the displacement storage element during the charge period, such that the error voltage is reduced during the next transfer period of the selected amplifier element, and comprising the steps of successively providing transfer and charge periods 25 for each of the N amplifier elements in a continuous cycle. A method according to claim 42, characterized in that the zero setting circuit comprises a charge amplifier and a temporary storage element with first and second terminals, the offset compensation steps further comprising connecting an input of the charge amplifier to the charge amplifier. another input of the selected amplifier element and connecting the first terminal of the temporary storage element in a feedback loop between an input and output of the charge amplifier during every transmission period, and simultaneously connecting the second 8420205 - 77 terminal of the temporary storage element to a common ground during the transfer period, such that the error voltage is transferred through the charge amplifier to the temporary storage element, and then disconnecting the second terminal from the common ground and connecting the second terminal to the output of the charge amplifier during the subsequent charge period whereby a voltage proportional to the error voltage occurs at that output of the charge amplifier during the charge period. 44. A method according to claim 43, characterized in that the offset compensation steps further comprise connecting the output of the charge amplifier to the offset storage element through an impedance during each charge period such that a current is supplied to the offset storage element proportional to the error voltage to thereby adjust the voltage on the shift storage element in a direction which reduces the error voltage during the next transfer period of the selected amplifier element. 45. A method of compensating offset on a plurality of amplifier elements to N amplifier elements each having a number of inputs for practically eliminating errors due to voltage shift between N inputs of each of the amplifier elements, characterized in that a zero adjustment circuit is used for measuring a voltage and for supplying a current proportional to the voltage, each of the amplifier elements being connected respectively to a storage element at a first input thereof on which a compensation voltage is accumulated by the steps of the method of practical correction of each offset error at a second input of the amplifier element, and where any difference between the compensation voltage on the storage element and the voltage offset of the amplifier element is an error voltage occurring at the second input, 8420205 - 78, consisting of subsequent connection steps Van den ulcer circuit with each of the N amplifier elements and with the associated storage element for compensating for displacement at each selected amplifier element in sequence, consisting of first connecting the zero adjusting circuit to the second input of the selected amplifier element transfer period for determining the error voltage, then connecting the zero setting circuit to the storage element connected to the first input of the selected amplifier element during an interrupted charge period following the transfer period for setting the charge in the storage element during the charge period, such that the error voltage is reduced during the next transfer period of the selected amplifier element, and comprising the steps of sequentially supplying transfer and charge periods for each of the N amplifier elements in a continuous cycle. 46. A method according to claim 45, characterized in that the zero setting circuit comprises a charge amplifier and a temporary storage element with first and second terminals, the method further comprising the steps of connecting an input of the charge amplifier to the other input of the selected amplifier element and connecting the first terminal of the temporary storage element in a feedback loop between an input and output of the charge amplifier during each transfer period, and simultaneously connecting the second terminal of the temporary storage element to a common ground during the transfer period such that the error voltage is transferred through the charge amplifier to the temporary storage element, and then disconnecting the second terminal from the common ground and connecting the second terminal to the output of the charge amplifier during the Subsequent charge period through which a voltage proportional to the error voltage, 8420205 - 79 - occurs at the output of the charge amplifier during the charge period. A method according to claim; 45, characterized in that during each charge period the output 5 of the charge amplifier is connected to the storage element such that a current is supplied to the storage element proportional to the error voltage to thereby adjust the voltage on the storage element in a direction which reduces the error voltage during the next transfer period of the selected amplifier element. 48. Modulator for converting an input signal into an output pulse train which varies between two levels and which has an average level over time proportional to the input signal, characterized in that means are provided for supplying the signals to a summing node, switching means for supplying a second signal to the summing node selected from at least two different reference signals of predetermined strengths, the difference at any time between the input signal and the second signal being a difference signal, measuring means for integrating the difference signal at the summing node and for determining when the integrated difference signal reaches a threshold level, the measuring means including an amplifier element and offset compensation means for practically eliminating any offset error resulting from a voltage offset occurring between the gain amplifier inputs of the amplifier element, the compensation means comprising a first storage element connected to an amplifier input and means for transmitting a shift voltage to the first storage element for compensating for the voltage shift, a clock for supplying clock pulses at predetermined clock intervals, a bistable circuit responsive to the measuring members and the clock 35 and providing a first output signal changeable at 8420205 - 80 - each clock pulse between first and second levels when the integrated difference signal has crossed the threshold level during a clock interval, while the switches are actuating on the bistable circuit such that one of the reference signals is applied to the summing node when the first output signal is at its first level and another reference signal is applied to the summing node when the first output signal is at its two is the level at which the mean value of the reference 10 signals over time balances the input signal at the summing node and the mean level over time at the first output signal is proportional to the input signal. 49. Modulator according to claim 48, characterized in that the second signal is selected from the two reference signals which are substantially equal in strength and opposite in polarity. 50. Modulator according to claim 48, characterized in that the measuring means comprise a second storage element connected between the summing node and a common ground, the second storage element providing part of a passive integrator for integrating the difference signal, the voltage on summing node is the integrated difference signal. 51. A modulator according to claim 50, characterized in that the amplifier element serves as a comparator for determining when a signal input to the amplifier element reaches a threshold level, the amplifier element having an input connected in an electrical path with the summing node and the output is connected to the bistable circuit, so that the amplifier element delivers a first control signal which is high when the integrated difference signal is above the threshold level and low when the integrated difference signal is below the threshold level. 52. Modulator according to claim 51, 8420205 - 81 - characterized in that the first storage element is in the electrical path between the soramer node and the inversion input of the amplifier element, while the non-inversion input is connected to the common ground, while the displacement 5 offset compensators are provided with a feedback loop around the amplifier element between the inversion input of the amplifier element and its output which is periodically connected during an interrupted zero setting period so that each voltage shift occurs at low impedance at the reversing input during the zero setting period, together with means for simultaneously disconnecting a terminal of the first storage element of the summing node and connecting the one terminal to the common ground such that the voltage shift is stored in the first storage element during the zero setting period, while the zero setting period and alternating with the measurement periods in which the feedback loop around the amplifier element is disconnected and a connector of the first storage element is reconnected to the summing node, thereby balancing the voltage shift of the amplifier element by the voltage on the first storage element during the measurement period. 53. A modulator according to claim 52, characterized in that means are provided for synchronizing the zero setting and measuring periods with the clock pulses such that the zero setting periods occur during a part of each clock interval and the measuring periods occur when the first output signal is off. the bistable chain is changeable due to the measuring members. 54. A modulator according to claim 50, characterized in that the measuring means are provided with first and second amplifier elements which serve as comparators for determining when a signal input to the amplifier element reaches a threshold level, while the amplifier elements each have an input which is connected in an electrical path to the summing node, together with shift compensation means having a first storage element in which the shift voltage is stored, connected in the electric path with an input of each amplifier element, while the outputs of the first and second amplifier elements are connected to the bistable circuit alternately during respective first and second measurement periods in which the amplifier element is connected to the bistable chain and provide a first control signal high when the integrated difference signal is above the threshold level and low when the integrated difference signal is below the threshold level, and includes means for charging the first storage element connected to the first amplifier element to the shift voltage during a first amplification mullet adjustment period while the second amplifier element is connected to the bistable circuit and for modifying the first storage element connected to the second amplifier element to the shift voltage during a second amplifier zero adjustment period while the first amplifier element 20 is connected to the bistable circuit, the first amplifier nuclear adjustment periods occurring between first measurement periods and the second amplifier amplification adjusting periods occurring between second measurement periods. 55. A modulator as claimed in claim 54, characterized in that the one input of each amplifier element connected in an electrical path to the summing node is its inversion input and the offset compensation means includes a switchable feedback loop around each amplifier element which becomes selective connected for each respective amplifying mullet adjustment period between the inversion input of the respective amplifier element and its output such that each voltage shift occurs at low impedance at the respective inversion input, and means for transmitting each amplifier element of the voltage shift of the distant during the zero adjustment period. - 8420205 - 83 - stronger element to the connected first storage element. 56. A modulator according to claim 54, characterized in that the offset compensation means causes the zero setting period of each amplifier element to be shorter than the measuring period thereof such that the first amplifier zero setting period ends a predetermined interval before the start of the measuring period of the first amplifier element and the second amplifier zero setting period ends a predetermined interval before the measuring period of the first amplifier element begins so as to minimize errors due to slow comparator response. 57. Modulator according to claim 48, characterized in that a connection element of the amplifier element is connected to the summing node and the other connection element of the amplifier element is connected to the first storage element in which the shift voltage is stored. 58. Modulator according to claim 57, characterized in that the amplifier element is a first amplifier element of the measuring elements, which also comprises a second storage element connected to a negative feedback loop between the reversing input and output of the first amplifier element, while the reversal input is also connected to the summing node such that the integrated difference signal 25 occurs over the second storage element, and includes a comparator element connected between the output of the first amplifier element and the bistable circuit, while the comparator element determines when the integrated difference signal on the second storage element reaches a threshold value. 59. Modulator according to claim 58, characterized in that any difference between the shift voltage on the first storage element and the actual voltage shift of the first amplifier element is an error voltage which occurs at the reversing input of the first amplifier element, while the shift compensation means 8420205 - 84 - are provided with means for interrupted connection of the reversing input of the first amplifier element to the non-reversing input of the second amplifier element during a transfer period, and provided with a temporary storage element 5 connected to a first connecting element during the transfer period with both the output and the reversing input of the second amplifier element, and a second terminal connected to a common ground during the transfer period, the offset compensation members also forming a charge period during which the first storage element is connected to the non-inversion input of the second amplifier element and its output is disconnected from the first and connected to the second terminal of the temporary storage element such that a negative voltage equal to the error voltage occurs at the output of the second amplifier element, and means for connecting the output of the second amplifier element to the first storage element via an impedance during the charge period such that a current is supplied to the first storage element proportional to the error voltage for changing the voltage on the first storage element in a direction whereby the error voltage during the next transmission period is reduced. 60. System for supplying digital signals proportional to selected parameters of an input signal converted to a first modulated signal varying between two levels in a manner proportional to the amplitude and polarity of the input signal, characterized in that means are provided for delivering clock pulses at predetermined clock intervals, delay means for receiving the first modulated signal and for delivering a second modulated signal are substantially equal to the first modulated signal and delayed over a clock interval, and means for delivering of a first digital signal 35 containing output pulses at intervals of not less than 8420205 - 85 - the clock intervals when first and second modulated signals are simultaneously at predetermined levels such that the first digital signal carries strength and polarity information regarding the input signal. 61. A system according to claim 60, characterized in that the first modulated signal is changeable between first and second levels at the clock intervals in such a way that an average level is formed over each sufficient interval proportional to the input signal, while the means for adjusting the supplying a first digital signal delivering pulses at not less than the clock intervals when the first and second modulated signals are simultaneously on the first level such that the first digital signal contains pulses in proportion to the amount of time over which the first level of the first modulator signal exceeds the second level. 62. System according to claim 61, characterized in that inverters are provided for supplying a first inverse modulated signal which is the inverse of the first modulated signal and a second inverse modulated signal which is the inverse of the second modulated signal. and means for delivering a second digital signal containing pulses at not less than the clock intervals when the first and second inverted modulated signals are simultaneously at predetermined levels, so that the second signal contains pulses in proportion to the amount time over which a level of the first reverse modulated signal exceeds the other level. System according to claim 62, characterized in that the input signal is converted into a modulator containing a first bistable chain with O and Ö outputs, while the first modulated signal is the Q output of the bistable chain, while the inverters include using the Q output of the first bi-8420205-86 stable circuit to supply the first inverse modulated signal, while the delay means are a bistable circuit having Q and Q outputs, the second bistable chain receives the first modulated signal on its Q output 5 which duplicates the first modulated signal with a time delay of a clock interval, while the inverters use the Q output of the second bistable circuit to form the second reverse modulated signal . The system of claim 62, characterized in that the amount of time over which a level of the first modulated signal exceeds the other over each sufficient interval is proportional to the magnitude of a polarity of the input signal, the system further comprising gate means for recording first and second digital signals and for outputting a digital sum signal which is the sum of the first and second digital signals and is proportional to the absolute strength of the input signal. System according to claim 60, 20, characterized in that the delay means comprise a bistable circuit which receives the first modulated signal at an input thereof and supplies clock pulses and an output which is the second modulated signal and which follows and duplicates each change. in the first modulated signal, delayed in time by a clock interval. 66. System for supplying digital signals proportional to selected output parameters of an input signal, characterized in that means are provided for supplying clock pulses at predetermined clock intervals, a modulator for converting the input signal into a first signal, the modulator comprising a first bistable circuit which, at a Q output thereof, outputs the first modulated signal that is changeable at the clock pulses between first and second levels 35 in a manner that provides an average level over each vol. 8420205 - 87 - acting interval proportional to the input signal, a second bistable circuit which receives the first modulated signal and the clock pulses and delivers a second modulated signal with a time delay of one of the clock intervals, 5 and means for delivering a first digital signal containing output pulses included at intervals not less than the predetermined at intervals when the first and second modulated signals are simultaneously on the first level, such that the first digital signal includes pulses in proportion to the amount of time over which the first level of the modulated signal exceeds the second level and also in proportion to the strength of a polarity of the input signal. 67. System according to claim 66, characterized in that the first and second bistable chains each have an additional Q output, the Q output of the first bistable circuit providing a first inverse modulated signal which is the inverse of the first modulated signal and the Q output of the second bistable circuit provides a second inversely modulated signal which is the inverse of the second modulated signal, means for delivering a second digital signal containing output pulses at no less than the predetermined intervals when the first and second reverse modulated signals are simultaneously on the first level, so that the second digital signal carries pulses in proportion to the amount of time over which the second level of the first modulated signal exceeds the first level and also proportional to the strength of the other polarity of the input signal. 68. Devices in a system for multiplying a first and a second signal together to provide a product signal, to adjust the phase relationship between the first and second signals, and to provide a product signal proportional to a 35 curved phase relationship product value, characterized in that digital sliders are provided for providing a selected time setting in at least one of the first and second signals for providing a selected phase relationship between the first and second signals the digital sliders including means for delaying a signal input thereto by a selected number of discrete intervals for providing a selected time setting in a manner independent of the signal to be set, and means for multiplying the first and second signals with each other to produce a product signal proportional to me t is the product value of the first and second signals with the selected phase relationship. 69. A device according to claim 68, characterized in that a modulator is provided for modulating one of the first and second signals to provide a modulated signal changeable between two levels at predetermined clock intervals with the modulated signal changes in a manner proportional to said one of the first and second signals and is used in the multiplication means to provide the product signal. 70. A device according to claim 69, characterized in that the digital shifters receive the modulated signal and provide the selected time delay by delaying the modulated signal by a selected number of discrete intervals. 71. Devices according to claim 70, characterized in that the discrete intervals over which a signal is delayed by the delaying means are synchronized with the clock intervals of the modulator. 72. Devices according to claim 70, characterized in that the delaying means comprises a first shift register which is clocked at selected predetermined first intervals for delaying the modulated signal by a selected number of the first 8420205 - 89 - intervals. A device according to claim 72, characterized in that the first intervals are equal to the clock intervals of the modulator. Bodies according to claim 72, characterized in that the first intervals are shorter than the clock intervals of the modulator. 75. Devices as claimed in claim 70, characterized in that the delay means comprises a plurality of shift registers clocked at selected predetermined intervals, comprising a first shift register clocked at first intervals for delaying the modulated signal over a selected number of the first intervals and a second shift register clocked at second inter-15 fall shorter than the first intervals for delaying the modulated signal by a selected value which is shorter than one of the first intervals causing a delay in the modulated signal which is the sum of a selected number of first and second intervals can be obtained. 84 20 205,? \, \ '* 1 * \