GB1559583A - Complementary mosfet device and method of manufacturing the same - Google Patents

Complementary mosfet device and method of manufacturing the same Download PDF

Info

Publication number
GB1559583A
GB1559583A GB29283/76A GB2928376A GB1559583A GB 1559583 A GB1559583 A GB 1559583A GB 29283/76 A GB29283/76 A GB 29283/76A GB 2928376 A GB2928376 A GB 2928376A GB 1559583 A GB1559583 A GB 1559583A
Authority
GB
United Kingdom
Prior art keywords
well layer
semiconductor substrate
transistor
current amplification
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB29283/76A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP50087395A external-priority patent/JPS6031108B2/ja
Priority claimed from JP50088066A external-priority patent/JPS5211876A/ja
Priority claimed from JP50088064A external-priority patent/JPS5211874A/ja
Priority claimed from JP50088065A external-priority patent/JPS6048912B2/ja
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Publication of GB1559583A publication Critical patent/GB1559583A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
GB29283/76A 1975-07-18 1976-07-14 Complementary mosfet device and method of manufacturing the same Expired GB1559583A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP50087395A JPS6031108B2 (ja) 1975-07-18 1975-07-18 半導体装置の製造方法
JP50088066A JPS5211876A (en) 1975-07-18 1975-07-18 Semiconductor device
JP50088064A JPS5211874A (en) 1975-07-18 1975-07-18 Semiconductor device
JP50088065A JPS6048912B2 (ja) 1975-07-18 1975-07-18 半導体装置製造方法

Publications (1)

Publication Number Publication Date
GB1559583A true GB1559583A (en) 1980-01-23

Family

ID=27467378

Family Applications (1)

Application Number Title Priority Date Filing Date
GB29283/76A Expired GB1559583A (en) 1975-07-18 1976-07-14 Complementary mosfet device and method of manufacturing the same

Country Status (6)

Country Link
US (1) US4302875A (https=)
CH (1) CH613071A5 (https=)
DE (1) DE2632448B2 (https=)
FR (1) FR2318500A1 (https=)
GB (1) GB1559583A (https=)
MY (1) MY8100313A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2128021A (en) * 1982-09-13 1984-04-18 Standard Microsyst Smc CMOS structure including deep region and process for fabrication

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5591162A (en) * 1978-12-27 1980-07-10 Fujitsu Ltd Semiconductor device
DE3173901D1 (en) * 1981-10-28 1986-04-03 Ibm Process for characterising the reliability behaviour of bipolar semiconductor devices
US4527325A (en) * 1983-12-23 1985-07-09 International Business Machines Corporation Process for fabricating semiconductor devices utilizing a protective film during high temperature annealing
US4728998A (en) * 1984-09-06 1988-03-01 Fairchild Semiconductor Corporation CMOS circuit having a reduced tendency to latch
US4603471A (en) * 1984-09-06 1986-08-05 Fairchild Semiconductor Corporation Method for making a CMOS circuit having a reduced tendency to latch by controlling the band-gap of source and drain regions
US4762802A (en) * 1984-11-09 1988-08-09 American Telephone And Telegraph Company At&T, Bell Laboratories Method for preventing latchup in CMOS devices
JP3375659B2 (ja) * 1991-03-28 2003-02-10 テキサス インスツルメンツ インコーポレイテツド 静電放電保護回路の形成方法
JPH08181598A (ja) * 1994-12-27 1996-07-12 Oki Electric Ind Co Ltd 半導体装置
JPH09199607A (ja) * 1996-01-18 1997-07-31 Nec Corp Ｃｍｏｓ半導体装置
DE10001871A1 (de) * 2000-01-18 2001-08-02 Infineon Technologies Ag Verfahren zur Herstellung eines steuerbaren Halbleiterschalt-elements und steuerbares Halbleiterschaltelement
US7132696B2 (en) 2002-08-28 2006-11-07 Micron Technology, Inc. Intermeshed guard bands for multiple voltage supply structures on an integrated circuit, and methods of making same
JP4387119B2 (ja) * 2003-03-27 2009-12-16 三菱電機株式会社 半導体装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3615873A (en) * 1969-06-03 1971-10-26 Sprague Electric Co Method of stabilizing mos devices
FR2139667A1 (en) * 1971-05-28 1973-01-12 Radiotechnique Compelec Diffused base transistor - with a source of recombination centres
US3712995A (en) * 1972-03-27 1973-01-23 Rca Corp Input transient protection for complementary insulated gate field effect transistor integrated circuit device
US3955210A (en) * 1974-12-30 1976-05-04 International Business Machines Corporation Elimination of SCR structure
US4053925A (en) * 1975-08-07 1977-10-11 Ibm Corporation Method and structure for controllng carrier lifetime in semiconductor devices
US4203126A (en) * 1975-11-13 1980-05-13 Siliconix, Inc. CMOS structure and method utilizing retarded electric field for minimum latch-up

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2128021A (en) * 1982-09-13 1984-04-18 Standard Microsyst Smc CMOS structure including deep region and process for fabrication

Also Published As

Publication number Publication date
MY8100313A (en) 1981-12-31
FR2318500A1 (fr) 1977-02-11
CH613071A5 (https=) 1979-08-31
US4302875A (en) 1981-12-01
DE2632448A1 (de) 1977-01-20
FR2318500B1 (https=) 1979-08-17
DE2632448B2 (de) 1981-04-16

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
746 Register noted 'licences of right' (sect. 46/1977)
PE20 Patent expired after termination of 20 years

Effective date: 19960713