CH613071A5 - - Google Patents

Info

Publication number
CH613071A5
CH613071A5 CH923576A CH923576A CH613071A5 CH 613071 A5 CH613071 A5 CH 613071A5 CH 923576 A CH923576 A CH 923576A CH 923576 A CH923576 A CH 923576A CH 613071 A5 CH613071 A5 CH 613071A5
Authority
CH
Switzerland
Application number
CH923576A
Inventor
Kazuo Satou
Mitsuhiko Ueno
Original Assignee
Tokyo Shibaura Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP50088066A external-priority patent/JPS5211876A/ja
Priority claimed from JP50088065A external-priority patent/JPS6048912B2/ja
Priority claimed from JP50088064A external-priority patent/JPS5211874A/ja
Priority claimed from JP50087395A external-priority patent/JPS6031108B2/ja
Application filed by Tokyo Shibaura Electric Co filed Critical Tokyo Shibaura Electric Co
Publication of CH613071A5 publication Critical patent/CH613071A5/xx

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
CH923576A 1975-07-18 1976-07-19 CH613071A5 (xx)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP50088066A JPS5211876A (en) 1975-07-18 1975-07-18 Semiconductor device
JP50088065A JPS6048912B2 (ja) 1975-07-18 1975-07-18 半導体装置製造方法
JP50088064A JPS5211874A (en) 1975-07-18 1975-07-18 Semiconductor device
JP50087395A JPS6031108B2 (ja) 1975-07-18 1975-07-18 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
CH613071A5 true CH613071A5 (xx) 1979-08-31

Family

ID=27467378

Family Applications (1)

Application Number Title Priority Date Filing Date
CH923576A CH613071A5 (xx) 1975-07-18 1976-07-19

Country Status (6)

Country Link
US (1) US4302875A (xx)
CH (1) CH613071A5 (xx)
DE (1) DE2632448B2 (xx)
FR (1) FR2318500A1 (xx)
GB (1) GB1559583A (xx)
MY (1) MY8100313A (xx)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5591162A (en) * 1978-12-27 1980-07-10 Fujitsu Ltd Semiconductor device
DE3173901D1 (en) * 1981-10-28 1986-04-03 Ibm Process for characterising the reliability behaviour of bipolar semiconductor devices
GB2128021A (en) * 1982-09-13 1984-04-18 Standard Microsyst Smc CMOS structure including deep region and process for fabrication
US4527325A (en) * 1983-12-23 1985-07-09 International Business Machines Corporation Process for fabricating semiconductor devices utilizing a protective film during high temperature annealing
US4603471A (en) * 1984-09-06 1986-08-05 Fairchild Semiconductor Corporation Method for making a CMOS circuit having a reduced tendency to latch by controlling the band-gap of source and drain regions
US4728998A (en) * 1984-09-06 1988-03-01 Fairchild Semiconductor Corporation CMOS circuit having a reduced tendency to latch
US4762802A (en) * 1984-11-09 1988-08-09 American Telephone And Telegraph Company At&T, Bell Laboratories Method for preventing latchup in CMOS devices
JP3375659B2 (ja) * 1991-03-28 2003-02-10 テキサス インスツルメンツ インコーポレイテツド 静電放電保護回路の形成方法
JPH08181598A (ja) * 1994-12-27 1996-07-12 Oki Electric Ind Co Ltd 半導体装置
JPH09199607A (ja) * 1996-01-18 1997-07-31 Nec Corp Ｃｍｏｓ半導体装置
DE10001871A1 (de) * 2000-01-18 2001-08-02 Infineon Technologies Ag Verfahren zur Herstellung eines steuerbaren Halbleiterschalt-elements und steuerbares Halbleiterschaltelement
US7132696B2 (en) * 2002-08-28 2006-11-07 Micron Technology, Inc. Intermeshed guard bands for multiple voltage supply structures on an integrated circuit, and methods of making same
JP4387119B2 (ja) * 2003-03-27 2009-12-16 三菱電機株式会社 半導体装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3615873A (en) * 1969-06-03 1971-10-26 Sprague Electric Co Method of stabilizing mos devices
FR2139667A1 (en) * 1971-05-28 1973-01-12 Radiotechnique Compelec Diffused base transistor - with a source of recombination centres
US3712995A (en) * 1972-03-27 1973-01-23 Rca Corp Input transient protection for complementary insulated gate field effect transistor integrated circuit device
US3955210A (en) * 1974-12-30 1976-05-04 International Business Machines Corporation Elimination of SCR structure
US4053925A (en) * 1975-08-07 1977-10-11 Ibm Corporation Method and structure for controllng carrier lifetime in semiconductor devices
US4203126A (en) * 1975-11-13 1980-05-13 Siliconix, Inc. CMOS structure and method utilizing retarded electric field for minimum latch-up

Also Published As

Publication number Publication date
GB1559583A (en) 1980-01-23
DE2632448A1 (de) 1977-01-20
FR2318500B1 (xx) 1979-08-17
MY8100313A (en) 1981-12-31
FR2318500A1 (fr) 1977-02-11
US4302875A (en) 1981-12-01
DE2632448B2 (de) 1981-04-16

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Legal Events

Date Code Title Description
PL Patent ceased