GB1559581A - Complementary mosfet device - Google Patents

Abstract

The semiconductor circuit has a semiconductor substrate (1) within which an island (2) having the opposite conductivity type and two MOS transistors (Q1) and (Q2) of opposite channel conductivity type are constructed. The influence of at least one of two parasitic bipolar transistors (Tr1) and (Tr2) occurring in such a circuit, namely of a first parasitic bipolar transistor (Tr1) whose base is formed by the substrate (1), and a second parasitic bipolar transistor (Tr2) whose base is formed by the island, is suppressed. The substrate has a first contact zone, and the island has a second contact zone, contact recesses being formed in the surfaces of the contact zones. The distance between the edge of at least one of the first and second contact recesses and the boundary between the substrate and the island is chosen in such a way that at least one of the first and second parasitic bipolar transistors cannot be effective. <IMAGE>

Description

(54) A COMPLEMENTARY MOSFET DEVICE (71) We, TOKYO SHIBAURA ELECTRIC COMPANY LIMITED, a Japanese corporation, of 72 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Japan, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to a complementary MOSFET (hereinafter called CMOS) device.

Hitherto various circuits constituted by CMOS's have been known. A typical example is a CMOS inverter circuit. As well known, a CMOS inverter circuit is constituted by a p-channel MOS transistor and an n-channel MOS transistor. The threshold voltage of one of these MOS transistors has the opposite characteristics to that of the other MOS transistor For this reason, generally only one of the two MOS transistors is switched on in response to input information. Thus no current flows between the power source of the CMOS inverter circuit, except during the transient period of the input information pulse.

Thus, almost no operation power needs to be consumed, except that during the transient period of the pulse, both MOS transistors are switched on but for a moment, thereby causing only a transient current for a moment, that a leak current occurs at the PN junction, and that a current flows due to charge or discharge of a storage capacitor at the output terminal of the CMOS inverter circuit.

However, when noise is applied impulsively to the output or input of such a CMOS circuit system, an abnormally large DC current of tens of mA to hundreds of mA flows between the positive and negative power sources of the CMOS circuit. Even after removing the noise, such abnormal current is observed to keep flowing regularly. This regular flow of the abnormally large current sometimes causes the CMOS circuit connection to be melted and thus cut. The impulse corresponding to the noise has both polarities, positive and negative, and serves to generate an abnormal current. To remove this abnormal current it is necessary either to lower the power source voltage below a specific value or to disconnect the CMOS circuit system from the power source.

Accordingly, an object of the invention is to provide a CMOS device in which an abnormally large current is prevented from being generated by impulse noise and thus from flowing.

According to this invention there is provided a semiconductor device which comprises a semiconductor substrate of one conductivity type; a well layer formed in the surface of said substrate with the opposite conductivity type to the substrate, the intersection of said well layer and the surface of said substrate defining a boundary edge between said substrate and said well layer comprising an edge of said substrate and an edge of said well layer ; first drain and source regions in said substrate forming a first MOS transistor of one channel type in the substrate; and second drain and source regions in said well layer forming a second MOS transistor in the well with the opposite channel type to said one channel type MOS transistor and, in the presence of impulse noise, said semiconductor device resulting in at least first and second parasitic bipolar transistors, said first parasitic bipolar transistor having a base comprising said substrate and further comprising one of said first drain and source regions and said well layer and said second parasitic transistor having a base comprising said well layer and further comprising one of said second drain and source regions and said substrate ; said substrate further including a first contact region formed with the same conductivity type as but of higher conductivity than said substrate; said well layer further including a second contact region formed with the same conductivity type as but of higher conductivity than said well layer; an insulating layer covering the surface of the substrate; and first and second contact holes formed in the insulating layer in register with the surfaces of said first and second contact regions respectively, said first and second contact regions being connected, in use, to respective power sources through said first and second contact holes respectively, the edge of at least one of said first and second contact holes being positioned a distance from said boundary edge between said substrate and well layer sufficiently small to suppress the operation of the corresponding one of said first and second parasitic bipolar transistors.

The invention can provide a CMOS device in which the circuit connection is never melted nor cut even if impulse noise is applied.

The invention can provide a CMOS device which can keep operating with a low power consumption even if an impulse noise signal is applied.

The invention can provide a CMOS device in which an abnormally large current is prevented from being generated by impulse noise even if the product of a current amplification factor of two parasitic bipolar transistors is more than 1.

By controlling the distance from the edge of at least one of said first and second contact holes to the boundary edge between the substrate and the well layer, the operation of the parasitic circuit formed in the substrate or well layer is suppressed, even if the product of the current amplification factor of the first parasitic transistor and the current amplification factor of the second parasitic transistor is more than 1.

This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figure 1 is a circuit diagram of an inverter constituted by CMOS's ; Figure 2 is a cross-sectional side view of a semiconductor device to explain the present invention; Figure 3 shows an equivalent circuit diagram to a parasitic circuit in the form of a CMOS circuit semiconductor device; Figure 4 is a diagram indicating the dependence of the current amplification factor of a lateral transistor having an N substrate as its base on the base width thereof; Figure 5 is a diagram indicating the dependence of the current amplification factor of a vertical transistor having a P well layer as its base on the base width thereof; Figure 6 is a diagram showing the dependence of the region where a latch up occurs on the base widths of both a parasitic lateral transistor and a parasitic vertical transistor and the location of a contact hole ; Figure 7 is a plan view showing a pattern layout of the semiconductor device according to the present invention to show a location of a contact hole ; Figure 8 is a diagram showing the relationship between a location of a contact hole and a minimum source voltage and input signal voltage to produce an abnormal current; Figure 9 is a diagram showing the relationship between a base width of a lateral transistor having an N substrate as its base and a minimum source voltage and input signal voltage to produce an abnormal current; and Figures 10 to 25 are plan views showing various pattern layouts of the semiconductor device of this invention.

The invention shall now be explained in detail with reference to the accompanying drawings.

The CMOS inverter circuit illustrated in Figure 1 is comprised of a p-channel MOS transistor Q, and n-channel MOS transistor Q2. The source electrode of the MOS transistor Q, is connected to the positive power source Ver), while the drain electrode thereof is connected to the output terminal, jointly with the drain electrode of the MOS Qz.

The source electrode of the MOS transistor Q7 is connected to the negative power source Vss. The gate electrodes of the MOS transistors 01 and Q. are coupled to each other so as to form the input terminal of the CMOS inverter circuit.

Figure 2 shows a semiconductor device wherein the CMOS inverter circuit shown in Figure 1 is formed in a semiconductor wafer. The substrate I of the embodiment is an N type silicon substrate with an N type impurity, for example phosphorus, doped in concentration of about 1 x 10l5 atoms/cm3. From the surface of the N type silicon substrate 1 a P type impurity, for example boron, is diffused into a portion of the substrate 1 in concentration of about 2 x 1016 atoms/cm3, thereby forming a P well layer 2. Further, boron is diffused into the N type substrate 1, the P well layer 2 and the junction edges between the N type substrate 1 and the P well layer 2, in concentration of about 1019 atoms/cm3, thereby simultaneously forming in the N type substrate 1 a Pu type source region 3 and a P+ type drain region 4 which constitute a p-channel MOS transistor Qt, a P+ type conductive coupling region 6 in the P well layer, and P+ tvpe guard rings 5 in the junction edges between N type substrate 1 and the P well layer 2.'thereafter, phosphorus is diffused into the P well layer 2 and the N type substrate 1 in concentration of about 102 atoms/cm, thereby forming simultaneously an Ne type source region 7 and an N+ type drain region 8 which constitute an n-channel MOS transistor Q2 in the P well layer 2 and an N+ type conductive coupling region 9 in the N type substrate 1. When this is done, a field silicon oxide 10 is formed on the entire surface of the substrate 1.

Thereafter, in order to form gate regions of the MOS transistors Q, and Q2, photo-etching is conducted on the substrate 1, thereby making holes in the field oxide film 10. At the bottoms of these holes gate oxide films 11 and 12 having a thickness of 1500A are formed by oxidizing the holes at a high temperature. Then in order to effect such a circuit connection as shown in Figure 1, contact holes of predetermined sizes are bored in the silicon oxide film 10, and a conductive film of, for example, aluminum is deposited all over the surface of the substrate 1. The conductive film is then cut in a specific pattern so as to connect the P+ tyne drain region 4 and the N+ type drain region 8 to each other and connect the gate regions (or oxide films) 11 and 12 to each other. Thus, the drain regions 4 and 8 form an output terminal, and the gate regions 11 and 12 an input terminal. At the same time the P+ type conductive coupling region 6 and the N+ type conductive coupling region 9 are connected to the negative power source Vgg (ground) and the positive power source VDD, respectively. Further, if necessary, a silicon oxide film may be laid by chemical growth on the entire surface, except for desired portions, of the aluminum conductive film so as to protect the aluminum conductive film and enhance the reliability of the semiconductor device. Though not shown in Figure 2, a stopper may be disposed between the MOS transistors Q1 and Q2- When noise is applied impulsively to the output cr input of the semiconductor device which is so constituted as mentioned above and which serves as a CMOS inverter circuit, an abnormal current of 10 mA to 100 mA does flow. The inventors of the present invention have closely observed and studied this phenomenon. Finally the inventors have found out that when an impulse noise current is applied to the semiconductor device, a specific parasitic circuit is formed in the semiconductor device. as depicted by dotted lines in Figure 2. Namely, four kinds of parasitic bipolar transistors are formed in the semiconductor substrate 1. More specifically, a PNP lateral trans, stor Trl, whose emitter, base and collector are the source region 3 of the p-channel MOS transistor Q the N type semiconductor substrate 1 and the P well layer 2, respectively, is formed in the direction parallel to the surface of the substrate 1. An NPN vertical transistor Tr, whose emitter, base and collector are the N+ type source region 7 of the n-channel MOS transistor Q, the P well layer 2 and the N type semiconductor substrate 1, respectively, is formed in the direction perpendicular to the surface of the substrate 1. Similarly, a PNP lateral transistor Tr3, whose emitter, base and collector are the P+ type drain region 4 of the p-channel MOS transistor Q1, the N type semiconductor substrate 1 and the P well layer 2, respectively, is formed in the direction paralel to the surface of the substrate 1. Lastly an NPN vertical transistor Tr4, whose emitter, base and collector are the N+ type drain region 8 of the n-channel MOS transistor Q., the P well layer 2 and the N type semiconductor substrate 1, respectively, is formed in the direction perpendicular to the surface of the substrate 1.

In the semiconductor device shown in Figure 2 the collectors of the lateral transistors Trl and Tr3 and the bases of the vertical transistors Tr2 and Tr4 are constituted commonly by the P well layer 2. Thus, they are connected to one another and to the negative power source Vss (that is, grounded) through a resistance Rpweu snd the P+ type conductive coupling region 6 both formed in the P well layer 2. On the other hand, the bases of the lateral transistors Tri and Tr3 and the collectors of the vertical transistors Trz and Tr4 are constituted commonly by the semiconductor substrate 1. They are therefore connected together and to the positive power source VDD through a resistance RNsub and the N+ type conductive coupling region 9 both formed in the serriconductor substrate 1. Further, the emitters of the transistors Tr3 and Tr4 are connected to the output terminal OUTPUT, and the emitters of the transistors Tri and Tr2 are connected to the positive power source VDD and the negative power source Vss, respectively.

The connection of the lateral and vertical transistors being as such, the parasitic circuit formed in the CMOS circuit device of Figure 2 and indicated in dotted lines in Figure 2 can be expressed as such an equivalent circuit as illustrated in Figure 3. With reference to Figure 3, it shall be explained how the thyristor forme d in the CMOS circuit device shown in Figure 2 operates. In the following explanation,'a"denotes a current amplification factor which is a bipolar transistor term generally em) loyed to mean the ratio of collector current to the emitter current," "a current amplification factor, i. e. the ratio of the collector current to the base current ( =a a), and'I"current. Similarly,"e","b"and "c"stand for emitter, base and collector, respectis ely, and employed as suffix signs.

Further, suffix numerals are used thereby to denote the transistors indicated by the corresponding numerals. In addition"r"is employed to denote the internal resistance of each transistor.

In Figure 3, when a positive impulse noise current Iin is applied to the output terminal as shown by the solid arrow, current of a3 x Iin flows in the collector of the transistor Tr3. The current of &alpha;3 # Iin then flows through the resistance Rp wen of the P well layer 2, which serves as a by-pass. When the voltage across the resistance becomes over the threshold voltage Vbe2 between the base and emitter of the transistor Tr2, the transistor Tr2 is rendered conductive, and base current Ib2 flows through its base. The resistance Rp well in the P well layer is far greater than the internal resistance Vb between the base and emitter of the transistor Tr2. For this reason, the collector current a3 x Iin of the transistor Tr3 hardly flows through the resistance Rp we". Consequently, the base current Ib2 of the transistor Tr2 is almost equal to the collector current a3 x Ijn of the transistor Tr3. Namely, Ib2=C (3l,n(Rpwe)!Vbe2).(1) Ic2 = P2lb2 = fIin. (2) Similarly, when the collector current lc2 of the transistor Tr2 acts as drive current and the voltage at both terminals of the resistance R,, S, b of the substrate rises to the threshold voltageVbel between the base and emitter of the transistor Tr ;, the transistor Trl is rendered conductive. Thus a base current lbl flows through the base of the transistor Tr,.

The base current lbi is nearly equal to the collector current IC2 of the transistor Tr2 since the resistance of RNsub is very much greater than the internal resistance Vbe1 between the base and emitter of the transistor Tr,. That is, Ibl # Ic2 (RNsub Vbe1) Id=jIbl=PIc2=PifI.n (4) When the MOS transistors Tr, and Tr2 are made conductive, current flows between the positive power source VDD and the ground through these transistors Tri and Tr2. In other words, when an impulse noise is applied to the CMOS inverter circuit, an abnormal current flows between the positive power source VDD and the ground through the semiconductor substrate 1 and the P well layer 2.

To keep a current flow between the positive power source VDD and the ground even after the noise application is stopped, it is required that the loop circuit constituted by the transistors Trl and Tr2 should perform a positive feedback operation. This is achieved only if the base current Ib, of the transistor Tr2 which is rendered conductive first when the impulse noise is applied is made equal to or smaller than the collector current 1, of the transistor Trl which is rendered conductive after the transistor Tr2. That is, Ih2 # Ic1 (5) Namely, Ib2 = a3Iin S l02a3Iin Therefore, 1 PiP2.(6) From the formula (6) it is understood that when the product of the current amplification factors Pi and 52 of the transistors Tr, and Trr is equal to or larger than 1, an abnormal current keep flowing between the positive power source VDD and the ground of the CMOS inverter circuit.

So long as the product of 1 and 8. is larger than 1, in the loop circuit including the transistors Trl and Tr2 the base current Ib2 in a specific cyclic period becomes greater than the base current Ib2 in the preceding cyclic period. Thus, the more times the current flows cyclically in the loop circuit, the greater the current between the power source Vpp and the ground becomes. However the current does not increase indefinitely. The current amplification factor of a transistor is a function of current, and its value increases with the current. However, it starts growing smaller one when it has reached a maximum value, (3 max. For this reason, the abnormal current flowing between the positive power source VDD and the ground of the CMOS inverter circuit is eventuallv maintained at a specific value, i. e. point of balance between the current increase effected bv the loop circuit and the current decrease achieved by the reduction of current amplification factor. Namely, usually the abnormal current comes to have such a value as is defined when the following two conditions are satisfied at the same time: a. Ib2 (n1) = Ib2 (n) b. 1(n)# 2(n) # 1, where"n"denotes the number of cyclic periods during which the abnormal current flows in the loop circuit.

The size of a transistor does not make a primary factor of the possibility of an abnormal current flow. But when the current amplification factor (3 of the transistor was measured with the size of the transistor (strictly speaking, the drain area) as parameter, it was ascertained that there existed an interrelationship between the size of the transistor and the current value at which the abnormal current was finally maintained. This fact indicates that the larger is the drain area of a transistor, the greater is the abnormal current.

When a negative impulse noise is applied to the output of the CMOS inverter circuit as shown in Figure 3, such current as indicated by the dotted-line arrow flows between the positive power source VDD and the output terminal OUTPUT, and the following formulas are established similarly as in case a positive impulse noise is applied to the output terminal: Ibi=aj,, (RbVbci)-(7) Ic1 = 1Ib1 = 1&alpha;4Iin Ib2 = Icl tRpwell rbe2) and Ic2 = P2lb2 = P2PlI = PiMin To maintain current in the circuit constituted by the transistors Trl and Tr2 and it is required that the collector current 1, of the transistor TR2 which is rendered conductive after the transistor Tri should be greater than the base current Ibl of the transistor Trl. That is, Ibl lc2....... I...... (8) In order to maintain an abnormal current in the CMOS inverter circuit in case a negative noise is applied thereto, it is required as in case a positive noise is applied that the following formula be established: I pip2..(6) It will be seen that if the abnormal current is maintained the parasitic circuit will be thyristor-like.

Thus it is ascertained that to avoid generation of an abnormal current and perpetual flow of the same in such a parasitic circuit as illustrated in Figures 2 and 3 it is sufficient to keep smaller than 1 the products of the current amplification factors pi and P2 of the transistors Trl and Tr2. To generalize it, in order to prevent generation of an abnormal current and a perpetual flow thereof in a CMOS inverter due to the operation of the parasitic circuit, it is sufficient to hold less than 1 the product of the current amplification factors of a lateral transistor formed substantially in parallel to the surface of the semiconductor substrate and a vertical transistor formed perpendicular to the surface of the semiconductor substrate.

To satisfy this requirement in practice, the following measures are effective: 1 To increase the base width of one or both of the lateral and vertical transistors.

2 To conduct a heat treatment on the semiconductor substrate during the manufacture process, thereby to shorten the life time of the carrier in the substrate.

(3) To shorten the life time of the carrier in the semiconductor wafer of which the substrate is formed.

(4) To dope the semiconductor substrate with gold.

In the diagram of Figure 4, plotted on the axis of ordinate is the current amplification factor , of the lateral transistor Trl in logarithmic notation, and plotted on the axis of abscissa is the base width Wb ( ) of the lateral transistor Trl, i. e. the distance between the edge of the P well layer 2 and the edge of the source region 3 of the p-channel MOS transistor Ql formed in the portion of the semiconductor substrate 1 other than the P well layer 2. The diagram shows that as the base width We increases, the current amplification factor pi becomes smaller. The length of each vertical line in Figure 4 indicates the range within which the current amplification factor l varies according to individual wafers and the position within the same wafer when the factor is measured, though the base width Wt7 is one and the same.

In the diagram of Figure 5, plotted on the axis of ordinate is the current amplification factor p2 of the vertical transistor TR2 in logarithmic notation, and plotted on the axis of abscissa is the base width W" ( ) of the vertical transistor Tir2, i. e. the thickness of the P well layer 2 minus the thickness of the source region 7 of the n-channel MOS transistor Q2 formed in the P well layer 2. This diagram teaches that as the base width Wy increases, the current amplification factor ss becomes smaller. In Figure 5 the length of each vertical line indicates the range within which the current amplification factor ss) varies according to individual wafers and the position within the same wafer where the factor is measured, though the base width W, is the same. The length of vertical lines further indicate the variation of the current amplification factor 2 when the doping amount of impurities is so regulated that the impurity concentration may become the same in case the slumping time, i. e, the period during which the wafer undergoes a heat treatment, varies as 20 hours, 40 hours and 60 hours, respectively, thereby causing a change of the base width Wu ouf the vertical transistor Tr2. Since the base width Wv of the vertical transistor Tr2 much depends on the thickness of the P well layer 2, it is influenced by the variation of the slumping time.

The relationship between the base width and the current amplification factor of the lateral or vertical transistor differs since the current amplification factors ssl and P2 varies according to the process of manufacturing the semiconductor device. For this reason, the straight lines A and B which show the relationship obtained from different experiments A and B using different semiconductor devices incline at different angles as shown in Figures 4 and 5. In Figure 5, no other current amplification factor of the vertical transistor Tr2 than indicated by the line B could be measured.

In the diagram of Figure 6, plotted on the axis of abscissa is the base width W, of the vertical transistor Tr2, and plotted on the axis of ordinate is the base width We of the lateral transistor Trl. In this semiconductor device, the P well layer was formed by diffusing, for example, boron into the semiconductor substrate. Its thickness was 12.5u when the wafer slumping was conducted for 60 hours at 1200 C, 10. 2 when the wafer-slumping was conducted for 40 hours at the same temperature, and 7. zut when the wafer-slumping was conducted for 20 hours at the same temperature. The product of the current amplification factors pi and P, was 8.1 in a CMOS inverter circuit wherein the base widths We and W,, of the lateral and vertical transistors Tr and Tr2 were of such value as denoted at point (a) in Figure 6. It was 4.8 in a CMOS inverter circuit in which the b ase widths Wg and W, were of such values as denoted at points (b) and (c) and 1.0 in a CMOS inverter circuit in which the base widths We and Wv were valued at points (d), (e) and (f), respectively. Any CMOS inverter circuit, wherein the base widths W and W, have suc (h values as denoted at a point located above the straight line on which points (d), (e) and (f) are aligne, had the product pi and B2 smaller than 1. Thus no abnormal large current was observed to flow in such CMOS inverter circuit. By contrast, an abnormal current was observed to flow in the CMOS inverter circuits in which the base widths Wg and ssA7v of the lateral and vertical transistors Tr, and Tr2 were at a point below said straight boundary line in Figure 6. That is, the so-called"latch up"phenomenon was seen in these CMOS inverter circuits.

Further based on the above-mentioned consideration, the present inventors have discovered that occurrence and sustenance of abnormal current can be suppressed even when product of the current amplification factors PI, P2 is larger than 1, namely, when the base widths Wb, Wv of the bipolar transistors are so narrow as to lie below a solid line of Figure 6 denoting 0102 = 1. In other words, the present inventors have found that occurrence or nonoccurrence of abnormal current depends on the area and position of a contact hole formed in the surface of a contact region to connect the semiconductor substrate and well layer to a power source.

With the CMOS inverter circuit of Figure 2, a power source VDD is connected to an N type semiconductor substrate 1 at the same potential through an N+ contact region 9. A power source Vss (GND) is connected to a P well region 2 at the same potential through a P+ contact region 6. The N+ and P+ contact regions 9,6 are required for an ohmic contact between the power sources VDD, Vss and the substrate, P well layer respectively.

Where the CMOS circuit is supplied with a trigger signal by an external noise, current never flows across the power sources VDD VSS through the N type substrate 1 and P well layer 2 b fore a parasitic bipolar transistor constituting part of the parasitic circuit of Figure 3 is operated in the N type substrate 1 or P well layer 2. Only where a potential difference defined hy the product of the current and the resistance of the N type semiconductor substrate 1 or P well layer 2 that is, a level of voltage impressed across the base and emitter of a bipolar transistor reaches a sufficiently high level for operation of the bipolar transistor, i. e. a thre shold voltage level between the base and emitter of the bipolar transistor, then the parasitic bipolar transistor whose base is formed of the N type semiconductor substrate 1 or P well layer 2 is put into operation to form a parasitic circuit connection shown in Figure 3.

Even if a noise signal is supplie to the CMOS circuit and unless voltage defined by the product arrived at by multiplying the current passing across the power sources VDD, Vss by the resistance Rh",ub of the N type semiconductor substrate 1 or the resistance Rpwell of the P well layer 2 reaches the level of the threshold voltage across the base and emitter of the bipolar transistor, the bipolar transistor is not actuated and thus the parasitic circuit is not operated, resulting in that abnormal current is little likely to arise in a sustained state, though some amount of current may momentarily flow through the CMOS circuit. Where, therefore, an amount of current initially flowing between the power sources VDD, Vss upon the supply of a noise impulse signal is supposed to be constant, then it is necessary to decrease the resistance RNsub of the N substrate or RpWe"of the P well in order to reduce a potential difference between both terminals of said resistance RNsub or Rpwel itself to a lower level than that of the threshold voltage across the base and emitter of the bipolar transistor, thereby suppressing the sustained flow of abnormal current.

The resistance RNsub and Rpwell has a maximum value over a path extending from the contact holes formed in the surface of the N+ contact region 9 and P+ contact region 6 to the boundary edge between the P well layer 2 and the N type substrate 1. To minimize the resistance Rub'Rpwen. therefore, it is advised to shorten, as prescribed, a distance from the edge of the contact hole of the N+ contact region 9 to the P well layer 2 and the distance from the edge of the contact hole of the P+ contact region 6 to the N type semiconductor substrate 1 or either of said two distances. To suppress the sustained flow of abnormal current, it is desired to shorten a distance between the edge of the contact hole of the N+ contact region 9 and/or P+ contact region 6 and the boundary edge between the P well layer 2 and the N type semiconductor substrate 1 in order to decrease the voltage occurring across the resistance RNsub or Rpweth namety, the voltage applied across the base and emitter of the parasitic bipolar transistor whose base is constituted by the Pw. en layer 2 or N type semiconductor substrate 1 to a lower level than that of the threshold voltage across the base and emitter of the bipolar transistor.

Figure 7 presents the pattern layout of a CMOS circuit. The portions of said circuit corresponding to the respective regions of the semiconductor substrate of Figure 2 are denoted by the same numerals as those of Figure 2, description thereof being omitted.

The locations and areas of contact holes A, B, C, D, E are shown in Figure 7 and Table 1 below.

TABLE 1 Location Extension of How contact hole is of contact contact hole spaced from semicon- Contact hole ductor substrate or Area resistance well layer (#) A Center of one Remotest 64 2 58 crosswise edge Extending fully along said one crosswise edge up to two B side edges disposed Remote 2,700 2 < 5 at right angles to said one crosswise edge Extending fully along said one crosswise edge and halfway of C each of said two side Slightly near 6,787 2 < 5 edges disposed at right angles to said one crosswise edge Extending fully along said one crosswise edge and three quarters of the total D length of said two Near 9,440 2 < 5 side edges disposed at right angles to said one crosswise edge Extending fully along said one crosswise edge and substantial E ly the whole length Nearest 10,00 2 < 5 of said two side edges disposed at right angles to said one crosswise edge As seen from Figure 7 and Table 1 above, the contact holes A to E formed on one of the MOS transistors Q1, Q2 progressively approach the N type semiconductor substrate 1 or P well layer 2 which constitutes the other of the MOS transistors Q, and Q2 in the order of A to E with the resultant decrease in the resistivity of the resistance RNsub. Ppweu-Further, since the contact holes A to E are successively increased in area in the order mentioned, the contact resistances of said holes A to E become smaller similarly in succession. Therefore, abnormal current arises with greater difficulty, as expected, in the order of the contact holes A to E. In Table 1, however, the contact resistances of the contact holes B to E are merely shown as less than 5 ohms. The results of experiments carried out in this connection are set forth in Figure 8. In Figure 8, the positions of the contact holes are shown on the abscissa, and input signal voltage and minimum levels VDD MIN of power source voltage to produce abnormal current are plotted on the ordinate. Where an abnormal input signal having a maximum amount of current of 500 mA was applied to the CMOS circuit as the result of an external noise, it was proved that said abnormal current occurred with progressively greater difficulty in the order of the contact holes A to E. It was further disposed that a minimum level VDD MIN power source voltage causing the generation of abnormal current depended on the manner in which the contact holes were formed, and progressively increased in the order in which a value obtained by adding the resistance Rsub'. Rpwen to a contact resistance successively became smaller, that is, in the order of the contact holes A to E. It was also found that where, with the product of the current amplification factors pi, ss2 of both transistors taken to be 3 1, it was tried to decrease the current amplification factor ss2 of the vertical transistor Tr2 by providing a P well layer with a layer depth xj in forming the contact holes A, B, C, it was still impossible to suppress abnormal current, but that where the contact holes were formed in the same manner as in the case of the contact holes D, E, the formation of the P well with a greater depth was effective to eliminate the occurrence of abnormal current. A solid line, one dot-chain line and two dots-chain line of Figure 8, as in Figure 5, respectively denote slumping times of 20 hr, 40 hr and 60 hr used in manufacturing a semiconductor wafer. It is seen from Figure 8 that with the contact holes A, B, C formed as described in connection with Figure 7, abnormal current appeared regardless of the slumping time, when the product of the current amplification factors pi, ss2 of the bipolar transistors was indicated : 1 ; with the contact hole D, abnormal current arose in a semiconductor device prepared by slumping of 20 hr, when the base width We of a lateral transistor Tr, was chosen to be 50 microns and no abnormal current took place in a semiconductor device manufactured by slumping of 60 hr.

Referring to Figure 9, the base width of a lateral transistor Trl is shown on the abscissa, and an amount of input signal current and a minimum level VDD IN of power source voltage to produce abnormal current are plotted on the ordinate.

Figure 9 shows the occurrence or nonoccurrence abnormal current in the contact hole D with the base width of a lateral transistor Trl varied. With the base width We of the lateral transistor taken to be 70 microns, no abnormal current occurs, whereas, in case of Wu ouf 30 microns, abnormal current actually arises. With W taken to be 50 microns, abnormal current is or is not produced according to the kind of semiconductor wafer itself or length of slumping time. With the contact hole D, therefore, a critical condition for the emergence of abnormal current is supposed to be that the base width We of the lateral transistor is 50 microns. Figure 9 shows that with We taken to be 50 microns, and slumping time to be 20 hr or the depth x of the P well layer to be 8 microns, abnormal current is or is not generated according to the kind of semiconductor wafer. Therefore, slumping time of 20 hr is considered necessary. The base of a vertical transistor Tr2 has a width Wv of 5.24 microns in the case of 20 hr-slumping. With W taken to be 50 microns and Wv to be 5.24 microns, a product of current amplification factors pi, ss2 determined from Figures 4 and 5 is expressed as 2.0 x 102 x 2.4 x 10-2 = 4.8. Therefore, it is seen in Figure 6 that with the contact hole D, a boundary region determining the occurrence or no occurrence of abnormal current lies at a point at which a product of the current amplification factors pi, P2 of the bipolar transistors indicates 4.8. This means that with the contact hole D, abnormal current can be suppressed even in the region where the product of ssl, ss2 is larger than 1.

Further experiments show that with the contact hole E, a region where a product of the amplification factors p;,p of the bipolar transistors indicates 8.1 as shown in Figure 6 constitutes a boundary determining the presence or absence of abnormal current. When formation of a contact hole proceeds from D to E, a distance between the contact hole and the semi-conductor substrate or well layer is more shortened, with the resultant increase in the area of that portion of the Wf, Wv where no abnormal current is generated, thereby enablin the CMOS semiconductor device presenting a larger product of amplification factors to be saved from abnormal current. Namely, depending on the manner in which a contact hole is formed, it is possible to prevent the occurrence of abnormal current even in the case where a product of the amplification factors Pi, ss2 of the bipolar transistors is larger than 1.

The following experimental formula has been obtained to express the relationship between a current amplification factor and the base width of the parasitic transistor: Current amplification factor P = Kexp (-aW). (10) where: K, a = coefficients W = base width of a parasitic bipolar transistor Further, the present inventors have adopted a parameter 6 associated with the manner in which a contact hole is formed, thereby experimentally establishing the following formula showing the relationship between the base width Wb of a lateral transistor Trl and the base width W, of a vertical transistor Tr2 which cooperate to suppress abnormal current.

We > I log K,, K, ~ n W, Where; K#, Kv = values of a coefficient K of the formula (10) in the lateral and vertical transistors Trl and Tr2 m, n = values of a coefficient a of the formula (10) in the lateral and vertical transistors Tri an I Tr There will now be described the above-mentioned formula (11) by reference to Figure 6.

The base width We of the lateral transistor Tri is plotted on the ordinate, and the base width Wu ouf the vertical transistor Tr2 is shown on the abscissa. The formula 11 denotes a region lying above a straight line whose contact with the ordinate (not shown in Figure 6) is expressed as l/mlogK#Kv/#.

Change of the location of a contact hole or the manner in which a contact hole is formed leads to variation of o. Where, therefore, formation of a contact hole is shifted from A to E, then the line of the formula 11 denoting the boundary region of the occurrence of abnormal current is shifted downward in parallel with a line representing a product of the current amplification factors PI, 02 = 1 to enlarge a region lying above a line satisfying the formula 11, namely, a region enabling the lateral and vertical transistors to have a base width adapted to suppress abnormal current.

Where, therefore, a contact hole is so formed as to satisfy 6 given in the above-mentioned formula 11, then the operation of a parasitic bipolar transistor in which a product of current amplification factors is larger than 1 can be so controlled as to suppress abnormal current.

Further, even when a product of the current amplification factor ssl of the lateral transistor Tri and the vertical transistor Tro is larger than 1, the operation of the lateral anc vertical transistors Trl, Tr2 can be suppressed by causing either or both of the P+ source region of a P channel type MOS transistor and the N+ source region of an N channel type MOS transistor to have the same potential as the N type semiconductor substrate and P well layer.

As mentioned above, abnormal current can be suppressed by defining a distance from the edge of a contact hole being formed in the N'contact region of the P channel MOS transistor to the col-cor of the lateral transistor Trl or P well layer, and a distance from the Ps contact region of the N channel MOS transistor to the collector of the vertical transistor Tr2 or the N type semiconductor substrate or either of said distances so as to cause a potential difference occurring at both terminals of the resistance RNsub and resistance Rp,. ell respectively to fall below the level of threshold voltage across the base and emitter of the lateral transistors Trl, Tr3 and also the level of threshold voltage across the base and emitter of the vertical transistors Tr, Tr4. In this case, the threshold voltage is chosen to be about 0.5 volt.

Figures 10 to 25 set forth the concrete patterns of the CMOS circuit, showing the positions and areas of contact holes formed is the P channel MOS transistor and N channel transistor. Regions enclose by dotted lines denote contact holes. The parts of Figures 10 to 25 corresonding to those of Figures 2 and 7 are denoted by the same numerals, description thereof being omitted.

This invention is applicable not only to a CMOS inverter circuit but also various forms of CMOS circuit in which parasitic bipolar transistors are formed. The CMOS circuit may obviously be formed by forming an N well layer in a P type semiconductor substrate.

Attention is directed to our copending patent Application No. 29282/76 (Serial No.

1559582) and 29283/76 (Serial 1559583) which contain subject matter common to this application.

Claims (5)

1. WHAT WE CLAIM IS: 1. A semiconductor device which comprises a semiconductor substrate of one conductivity type ; a well formed in the surface of said substrate with the opposite conductivity type to the substrate, the intersection of said well layer and the surface of said substrate defining a boundary edge between said substrate and said well layer comprising an edge of said substrate and an edge of said well layer ; first drain and source regions in said substrate forming a first MOS transistor of one channel type in the substrate ; and second drain and source regions in said well layer forming a second MOS transistor in the well layer with the opposite ch innel type to said one channel type MOS transistor and, in the presence of impulse noise, si id semiconductor device resulting in at least first and second parasitic bipolar transistors, said first parasitic bipolar transistor having a base comprising said substrate and further comprising one of said first drain and source regions and said well layer and said second parasitic transistor having a base comprising said well layer and further comprising one of said second drain and source regions and said substrate; said substrate further including a first contact region formed with the same conductivity type as but of higher conductivity than said substrate; said well layer further including a second contact region forn. ed with the same conductivity type as but of higher conductivity than said well layer ; an i tsulating layer covering the surface of the substrate; and first and second contact holes form d in the insulating layer in register with the surfaces of said first and second contact regi ns respectively, said first and second contact regions being connected, in use, to respective power sources through said first and second contact holes respectively; the edge of at least one of said first and second contact holes being positioned a distance from sa d boundary edge between said substrate and well layer sufficiently small to suppress the ope ation of the corresponding one of said first and second parasitic bipolar transistors.
2. 2. A semiconductor device according to claim 1, wherein the distance from the edge of said firs-contact hole to the boundary edge between said substrate and said well layer is so chosen vs to cause the potential difference, in use, between the emitter and base of said first parasitic transistor to fall below the threshold voltage across said emitter and base at which said first parasitic transistor is caused to conduct.
3. 3. A semiconductor device according to claim 1 or claim, wherein the distance from the edge of said second contact hole to the boundary edge of between the substrate and the well layer is so chosen as to cause the potential difference, in use, between the emitter and base of said second parasitic transistor to fall below the threshold voltage across said emitter and base at which said second parasitic transistor is caused to conduct.
4. 4. A semiconductor device according to any of claims 1 to 3, wherein a product of the amplification factor p, of the first parasitic transistor whose base is constituted by the semiconductor substrate and the amplification factor P2 of the second parasitic transistor whose base is for ned of the well layer is larger than 1.
5. 5. A complem mtary MOSFET device as claimed in claim 1 and substantially as hereinbefore deso ibed with reference to the accompanying drawings.