GB1525274A - Memory arrangements - Google Patents

Memory arrangements

Info

Publication number
GB1525274A
GB1525274A GB47215/75A GB4721575A GB1525274A GB 1525274 A GB1525274 A GB 1525274A GB 47215/75 A GB47215/75 A GB 47215/75A GB 4721575 A GB4721575 A GB 4721575A GB 1525274 A GB1525274 A GB 1525274A
Authority
GB
United Kingdom
Prior art keywords
registers
array
data
address
shifted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB47215/75A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1525274A publication Critical patent/GB1525274A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318385—Random or pseudo-random test pattern
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/20—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits using counters or linear-feedback shift registers [LFSR]

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
GB47215/75A 1974-12-20 1975-11-17 Memory arrangements Expired GB1525274A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/534,606 US3961252A (en) 1974-12-20 1974-12-20 Testing embedded arrays

Publications (1)

Publication Number Publication Date
GB1525274A true GB1525274A (en) 1978-09-20

Family

ID=24130783

Family Applications (1)

Application Number Title Priority Date Filing Date
GB47215/75A Expired GB1525274A (en) 1974-12-20 1975-11-17 Memory arrangements

Country Status (7)

Country Link
US (1) US3961252A (enExample)
JP (1) JPS5441450B2 (enExample)
CA (1) CA1038079A (enExample)
DE (1) DE2556822C2 (enExample)
FR (1) FR2295531A1 (enExample)
GB (1) GB1525274A (enExample)
IT (1) IT1043514B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2235074A (en) * 1989-06-10 1991-02-20 Samsung Electronics Co Ltd Testing a memory device

Families Citing this family (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IN146507B (enExample) * 1975-09-29 1979-06-23 Ericsson Telefon Ab L M
US4055754A (en) * 1975-12-22 1977-10-25 Chesley Gilman D Memory device and method of testing the same
US4066880A (en) * 1976-03-30 1978-01-03 Engineered Systems, Inc. System for pretesting electronic memory locations and automatically identifying faulty memory sections
DE2904874A1 (de) * 1979-02-09 1980-08-14 Standard Elektrik Lorenz Ag Monolithisch integrierte grosschaltung und deren betriebsschaltung
DE2824224A1 (de) * 1978-06-02 1979-12-20 Standard Elektrik Lorenz Ag Monolithisch integrierte grosschaltung
AU530415B2 (en) * 1978-06-02 1983-07-14 International Standard Electric Corp. Integrated circuits
FR2432175A1 (fr) * 1978-07-27 1980-02-22 Cii Honeywell Bull Procede pour tester un systeme logique et systeme logique pour la mise en oeuvre de ce procede
US4225957A (en) * 1978-10-16 1980-09-30 International Business Machines Corporation Testing macros embedded in LSI chips
DE2902375C2 (de) * 1979-01-23 1984-05-17 Siemens AG, 1000 Berlin und 8000 München Logikbaustein für integrierte Digitalschaltungen
EP0019150B1 (en) * 1979-05-15 1984-07-18 Mostek Corporation Method of testing the operation of an internal refresh counter in a random access memory and circuit for the testing thereof
JPS5614357A (en) * 1979-07-16 1981-02-12 Matsushita Electric Ind Co Ltd Diagnostic control unit
GB2070779B (en) * 1980-02-28 1984-02-15 Solartron Electronic Group Apparatus for testing digital electronic circuits
DE3029883A1 (de) * 1980-08-07 1982-03-11 Ibm Deutschland Gmbh, 7000 Stuttgart Schieberegister fuer pruef- und test-zwecke
DE3030299A1 (de) 1980-08-09 1982-04-08 Ibm Deutschland Gmbh, 7000 Stuttgart Schieberegister fuer pruef- und test-zwecke
US4380805A (en) * 1980-09-08 1983-04-19 Mostek Corporation Tape burn-in circuit
EP0059188A1 (en) * 1980-09-08 1982-09-08 Mostek Corporation Tape burn-in circuit
US4404519A (en) * 1980-12-10 1983-09-13 International Business Machine Company Testing embedded arrays in large scale integrated circuits
US4433412A (en) * 1981-05-15 1984-02-21 Rockwell International Corporation Method and apparatus for testing and verifying the operability of register based state machine apparatus
US4441182A (en) * 1981-05-15 1984-04-03 Rockwell International Corporation Repetitious logic state signal generation apparatus
US4441075A (en) * 1981-07-02 1984-04-03 International Business Machines Corporation Circuit arrangement which permits the testing of each individual chip and interchip connection in a high density packaging structure having a plurality of interconnected chips, without any physical disconnection
US4556840A (en) * 1981-10-30 1985-12-03 Honeywell Information Systems Inc. Method for testing electronic assemblies
US4808915A (en) * 1981-10-30 1989-02-28 Honeywell Bull, Inc. Assembly of electronic components testable by a reciprocal quiescent testing technique
US4481627A (en) * 1981-10-30 1984-11-06 Honeywell Information Systems Inc. Embedded memory testing method and apparatus
US4503386A (en) * 1982-04-20 1985-03-05 International Business Machines Corporation Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks
US4527115A (en) * 1982-12-22 1985-07-02 Raytheon Company Configurable logic gate array
US4499579A (en) * 1983-03-10 1985-02-12 Honeywell Information Systems Inc. Programmable logic array with dynamic test capability in the unprogrammed state
EP0146661B1 (fr) * 1983-12-28 1988-03-02 International Business Machines Corporation Procédé de diagnostic électrique pour identifier une cellule défectueuse dans une chaîne de cellules formant un registre à décalage
US4608669A (en) * 1984-05-18 1986-08-26 International Business Machines Corporation Self contained array timing
JPH073865B2 (ja) * 1984-08-07 1995-01-18 富士通株式会社 半導体集積回路及び半導体集積回路の試験方法
US4715034A (en) * 1985-03-04 1987-12-22 John Fluke Mfg. Co., Inc. Method of and system for fast functional testing of random access memories
GB8507613D0 (en) * 1985-03-23 1985-05-01 Int Computers Ltd Testing digital integrated circuits
GB8511188D0 (en) * 1985-05-02 1985-06-12 Int Computers Ltd Testing digital integrated circuits
GB8511187D0 (en) * 1985-05-02 1985-06-12 Int Computers Ltd Testing digital integrated circuits
US4719411A (en) * 1985-05-13 1988-01-12 California Institute Of Technology Addressable test matrix for measuring analog transfer characteristics of test elements used for integrated process control and device evaluation
JPS6238600A (ja) * 1985-08-14 1987-02-19 Fujitsu Ltd 半導体記憶装置
US4783782A (en) * 1985-12-12 1988-11-08 Alcatel U.S.A. Corporation Manufacturing test data storage apparatus for dynamically reconfigurable cellular array processor chip
US4669081A (en) * 1986-02-04 1987-05-26 Raytheon Company LSI fault insertion
US4726023A (en) * 1986-05-14 1988-02-16 International Business Machines Corporation Determination of testability of combined logic end memory by ignoring memory
DE3619255A1 (de) * 1986-06-07 1987-12-10 Ant Nachrichtentech Einrichtung zur pruefung von schreib-/lesespeichern
US4853628A (en) * 1987-09-10 1989-08-01 Gazelle Microcircuits, Inc. Apparatus for measuring circuit parameters of a packaged semiconductor device
US4841485A (en) * 1987-11-05 1989-06-20 International Business Machines Corporation Read/write memory device with an embedded read-only pattern and method for providing same
US4852094A (en) * 1987-11-10 1989-07-25 Eaton Corporation Dual path switch gate array
US4878209A (en) * 1988-03-17 1989-10-31 International Business Machines Corporation Macro performance test
US4875209A (en) * 1988-04-04 1989-10-17 Raytheon Company Transient and intermittent fault insertion
US4975641A (en) * 1988-07-14 1990-12-04 Sharp Kabushiki Kaisha Integrated circuit and method for testing the integrated circuit
FR2653913B1 (fr) * 1989-10-31 1992-01-03 Sgs Thomson Microelectronics Systeme de test d'un microprocesseur.
US5228040A (en) * 1990-03-09 1993-07-13 At&T Bell Laboratories Testable implementations of finite state machines and methods for producing them
US5254940A (en) * 1990-12-13 1993-10-19 Lsi Logic Corporation Testable embedded microprocessor and method of testing same
US5369648A (en) * 1991-11-08 1994-11-29 Ncr Corporation Built-in self-test circuit
US5442640A (en) * 1993-01-19 1995-08-15 International Business Machines Corporation Test and diagnosis of associated output logic for products having embedded arrays
US5371748A (en) * 1993-03-26 1994-12-06 Vlsi Technology, Inc. Technique and apparatus for testing an electrically programmable ROM embedded among other digital circuitry on an IC chip
JPH0773699A (ja) * 1993-09-02 1995-03-17 Sony Corp デュアルポートメモリの埋込みテスト回路
GB9417266D0 (en) * 1994-08-26 1994-10-19 Inmos Ltd Testing a non-volatile memory
GB2295700B (en) * 1994-12-02 1999-04-21 Westinghouse Brake & Signal Data testing
US5847561A (en) * 1994-12-16 1998-12-08 Texas Instruments Incorporated Low overhead input and output boundary scan cells
US6041007A (en) * 1998-02-02 2000-03-21 Motorola, Inc. Device with programmable memory and method of programming
GB2345976B (en) * 1999-01-22 2003-06-25 Sgs Thomson Microelectronics Test circuit for memory
US6928581B1 (en) 1999-09-14 2005-08-09 International Business Machines Corporation Innovative bypass circuit for circuit testing and modification
US6931580B1 (en) 2000-03-13 2005-08-16 International Business Machines Corporation Rapid fail analysis of embedded objects
US7707472B1 (en) * 2004-05-17 2010-04-27 Altera Corporation Method and apparatus for routing efficient built-in self test for on-chip circuit blocks
US7257745B2 (en) * 2005-01-31 2007-08-14 International Business Machines Corporation Array self repair using built-in self test techniques
US7908532B2 (en) * 2008-02-16 2011-03-15 International Business Machines Corporation Automated system and processing for expedient diagnosis of broken shift registers latch chains

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1382401A (fr) * 1962-12-08 1964-12-18 Olympia Werke Ag Procédé et dispositif pour la détection d'erreurs dans une mémoire de calculatrice
US3387276A (en) * 1965-08-13 1968-06-04 Sperry Rand Corp Off-line memory test
US3631229A (en) * 1970-09-30 1971-12-28 Ibm Monolithic memory array tester
US3758761A (en) * 1971-08-17 1973-09-11 Texas Instruments Inc Self-interconnecting/self-repairable electronic systems on a slice
US3790885A (en) * 1972-03-27 1974-02-05 Ibm Serial test patterns for mosfet testing
US3789205A (en) * 1972-09-28 1974-01-29 Ibm Method of testing mosfet planar boards
US3761695A (en) * 1972-10-16 1973-09-25 Ibm Method of level sensitive testing a functional logic system
JPS4992970A (enExample) * 1972-10-31 1974-09-04
US3781670A (en) * 1972-12-29 1973-12-25 Ibm Ac performance test for large scale integrated circuit chips
FR2256706A5 (enExample) * 1973-12-27 1975-07-25 Cii

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2235074A (en) * 1989-06-10 1991-02-20 Samsung Electronics Co Ltd Testing a memory device

Also Published As

Publication number Publication date
FR2295531B1 (enExample) 1978-05-12
CA1038079A (en) 1978-09-05
US3961252A (en) 1976-06-01
FR2295531A1 (fr) 1976-07-16
IT1043514B (it) 1980-02-29
DE2556822A1 (de) 1976-06-24
JPS5441450B2 (enExample) 1979-12-08
JPS5178142A (enExample) 1976-07-07
DE2556822C2 (de) 1982-10-21

Similar Documents

Publication Publication Date Title
GB1525274A (en) Memory arrangements
CA1075770A (en) Method of propagation delay testing a level sensitive embedded array logic system
US3783254A (en) Level sensitive logic system
US6327685B1 (en) Logic built-in self test
US5383143A (en) Self re-seeding linear feedback shift register (LFSR) data processing system for generating a pseudo-random test bit stream and method of operation
US5680543A (en) Method and apparatus for built-in self-test with multiple clock circuits
US6442723B1 (en) Logic built-in self test selective signature generation
CA1233906A (en) Test and diagnostic arrangement for digital computers
US4680539A (en) General linear shift register
FR2203543A5 (enExample)
FR2203231B1 (enExample)
EP0419734B1 (en) Method for testing a hierarchically organised integrated circuit device, and integrated circuit device suitable for being so tested
US5469445A (en) Transparent testing of integrated circuits
JPH03214083A (ja) 回路ボードテストシステムとテストベクトル供給システム及び生成方法
EP2135104B1 (en) Testable integrated circuit and test data generation method
JP2572497B2 (ja) 論理誤り検出のための内蔵自己テストを持つ集積回路チップ
US5905737A (en) Test circuit
US3739160A (en) Method and apparatus for fault testing binary circuit subsystems
Mosalgi et al. Power optimized TPG for BIST architecture
Jone et al. A scheme for overlaying concurrent testing of VLSI circuits
GB1340157A (en) Testing logic circuits
US20040003330A1 (en) Logic built-in self-test (BIST)
KR100319711B1 (ko) 디버깅기능을갖는내장자기테스트회로
KR100220201B1 (ko) 패턴 발생 회로
Nayana et al. Modified low power STUMPS architecture

Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee