GB2235074A

GB2235074A - Testing a memory device

Info

Publication number: GB2235074A
Application number: GB9012833A
Authority: GB
Inventors: Hyung-Sub Chung
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1989-06-10
Filing date: 1990-06-08
Publication date: 1991-02-20
Also published as: JPH0312099A; DE4018438C2; KR920001079B1; KR910001778A; DE4018438A1; GB9012833D0

Abstract

In a test method for a memory device comprising RAM 1, with internal serial-data paths, data stored in the RAM are supplied through serial data paths 2, register 3 and sense amplifier 4 to an output buffer 5 and to a comparator 8 for comparison with a nominally identical set of data previously stored in a pattern register 7. The result of the comparison is output 9. This method avoids parallel access paths, thus saving chip space, and it enables self-testing by loading the RAM and the pattern register 7 with an arbitrary test pattern. <IMAGE>

Description

A 1 1 M&C FOLIO: 230P61387 TESTING A MEMORY DEVICE t - -_ - -- _. ( -) -

_- The present invention relates to a method and apparatus wherein a constant data pattern is stored in a memory device, e.g. a high-density integrated memory device (e.g., a DRAM) and is read from the memory device in order to check whether it coincides with the original data or not.

As DRAMs become more and more highly integrated, many layers and patterns are required. The fault ratio of DRAMs is determined by the amount of impurities to which the device is exposed during fabrication. The integrated DRAMs must be sorted according to whether they are good or bad, by a RAM test using precise processes. In a conventional RAM test, a fast testing method accessed the stored data from the RAM using parallel paths and compared the data with the original data.

With such a method, however, the number of parallel paths has to be increased for high speed processing. Such an increase in the number of the parallel pat.hs is not desirable since the chip size of the DRAM would become large. With reference to figure. 1 of the c 2 accompanying drawings, the conventional test method will now be explained.

After the start routine P1, a test-cycle routine P2 is carried out. In the next routine P3, the test data to be compared are stored in the RAM. Neict, the test data are read out from the RAM in routine P4, and are compared with the original test data in the next routine P5. By comparing two data sets, an error is detected when the two data sets are different from each other. The existence of a fault in the RAM is indicated in the subsequent routine P6.

If, however, the data read from the RAM coincide with the original data that are supplied, the program goes to the next routine P7 to determine whether all the data have been compared. If not all the data have been compared yet, the address of the DRAM is increased, in the next routine P8, to read the next portion of the stored data so that the test cycle is repeated from routine P4.

When all the data have been compared with the coresponding original data in the routine P5, the. program goes to a final routine P9 to generate a flag for indicating that the RAM is normal. But, with the 1 4 3 use of such a RAM test method, parallel data paths are required in order to read, write and compare, thereby bringing about an increase in the size of the chip accommodating the RAM due to the increase in number of the data paths.

It is therefore an object of this invention to provide a memory device test method which can avoid such an increase in the chip size.

It is another object of this invention to reduce the testing time by providing an improved testing method for comparing the stored pattern data with the original pattern data.

These objects can be achieved by a test method for a memory device having internal serial-data paths comprising the steps of: (a) supplying pattern data stored in the memory device through serial data paths; and (b) comparing the pattern data supplied through the serial data paths with nominally identical, corresponding pattern data stored in a pattern register.

The invention also provides apparatus for testing a memory device having internal serial-data paths, I,-- 4 comprising a means for latching pattern data supplied thereto from the memory device via a serial-data path, a pattern register for storing pattern data nominally identical to those stored in the memory device, and means for comparing at least corresponding portions of the pattern data supplied from the serial data register and of the pattern data stored in the pattern register.

A test method embodying the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

Fig. 1 is a flow chart illustrating the conventional test method for a RAM, Fig. 2 is a block diagram of apparatus embodying the present invention, and Fig. 3 is a flow chart illustrating a RAM test method embodying the present invention.

With reference to Figure 2, a high-density integrated RAM 1 as a memory device is connected to a data register 3 through a first path 2. A sense amplifier 4 is connected for amplyfying the output of the data register 3, and a buffer 5 receives the output of the sense amplifier 4. A pattern register 7 is connected through a second path 6 to the output of the sense amplifier 4, 1 t & C k_ - 5 between the sense amplifier 4 and the buffer 5, for comparing the data provided through the second path 6 with pattern data PD. A comparator 8 is connected to the pattern register 7 and provides an output, by way of a third path 9, to the buffer 5. Here, PD represents pattern data written into both the RAM 1 and the pattern register 7.

The operation of the apparatus will now be explained with reference to the flow chart of Fig. 3. First, the power supply condition and the readiness for data testing are checked in a start routine P11, and if normal, a test-cycle routine P12 is carried out. In the routine P12, a program for a fast RAM test is loaded and carried out according to the program sequence.

In the next routine P13, a test pattern input cycle is carried out, to store the pattern data PD in both the RAM 1 and the pattern register 7.

In the next routine P14, a data transfer cycle is carried out, in which the data in one row of the RAM 1 are stored in the data register 3 through the first path 2. The data register 3 consists of latches to latch the data for serial access. In the next routine P15, the data latched in the data register 3 are amplified by the r l- 6 sense amplifier 4 and transferred by the second path 6 to the pattern register 7 for comparison with the pattern data PD loaded therein, and the latched data in the data register 3 and amplified by the sense amplifier 4 are also sent to the buffer 5.

Using the comparator 8, the pattern register 7 compares the output data of the data register 3 with the previously stored pattern data PD, by way of a built-in test, as described below.

Firstly, a check is made, in routine P16, whether the storage of all the data provided from the data register 3 through the second path 6 in the pattern register 7 has been completed or not. If the data storage in the pattern register 7 is not complete, the program goes to a routine P17 to increase a counter. The operation of the routine P15 is thus repeatedly carried out to store all the data to be compared in the pattern register 7.

When all the data to be compared have been stored in the pattern register 7, routines P18 and P20 are carried out. The routine P18 is carried out to determine if all the data stored at the current row address in the-RAM have been entered into the data register 3. If this transfer has been completed, the row address is i A c 7 increased in a routine P19 in order to latch the data stored at the next row address in the RAM 1 in the data register 3.

Also, the comparison between the data stored in the pattern register 7 and the previously stored original pattern data PD is carried out by the comparator 8, in the routine P20. A flag representing the result of the comparison made between the two data sets is generated and provided to the third path 9, in a routine P21. The data are then output, in the routine P22.

When the pattern register 7 has completed the comparison operation between the pattern data and the data transferred through the second path 6, new data are received for comparison. It is at this point that the flag notifying whether the two data sets were consistent or not is generated through the third path 9 as a logic signal, so that either a normal or a fault condition of the data is indicated.

The present apparatus stores the data in the data register 3 through the serial data path 2, according to each successive unit of the row address, using thQ routine P18, thereby improving the data processing time by avoiding any use of the additional column address.

c 8 This use of serial-data paths also avoids the need to increase the chip size, so preserving the high-density integration. Moreover, a test using arbitrary data can be carried out using the internal pattern register and a fast RAM test is possible by means of the serial access technique.

An explanation of the reduced time of the RAM test follows: In the conventional case of using four parallel paths for a 1M DRAM, the time spent is calculated as follows: 1M x 200 ns (cycle time) / 4 = 0.05 sec. The present apparatus takes a time of 1M x 30 ns (serial cycle time) 4 + 2K x 200 ns (data conversion cycle) = 0.008 sec. Thus, the test time is lower than that of the parallel test system.

As mentioned above, the present test method determines whether there is a normal or a fault condition in the memory device 1 by comparing the accessed data supplied through the first and second data paths with the pattern data of the pattern register 7.

The test method embodying the invention can not only avoid increasing the chip size of the memory device but can also provide a faster RAM test than before.

9 Moreover, the self test, in which the comparison is undertaken with arbitrary test pattern data, is made possible by the present invention.

The invention is in no way limited to the embodiment described hereinabove. Various modifications of the disclosed embodiment as well as other embodiments of the invention will become apparent to persons skilled in the art upon reference to the description of the invention.

Claims

1. A test method for a memory device having internal serial-data paths comprising the steps of:

(a) supplying pattern data stored in the memory device through serial data paths; and (b) comparing the pattern data supplied through the serial data paths with nominally identical, corresponding pattern data stored in a pattern register.

2. A test method according to claim 1, wherein the memory device is a RAM device and the data stored in RAM device is supplied through serial data paths which include a first serial data path to provide data to be latched in a data register connected to the RAM, a second serial data path to provide the latched data amplified by a sense amplifier to the pattern register, and a third serial data path to provide the result of the comparison between the pattern data provided through the second data path and the said corresponding pattern data stored in the pattern register.

3. A test method according to claim 2, wherein the third serial data path for providing the comparative result provides a flag signal for notifying consistency or inconsistency of the compared data as a logic signal.

z 1 C_ I-

4. A test method according to claim 1, 2 or 3, wherein the pattern register compares the pattern data with the data provided through the second serial data path, and receives a further set of the accessed data from the data register through the second serial data path, to compare it with the corresponding pattern data when the data comparison is completed.

5. Apparatus for testing a memory device having internal serial-data paths, comprising a means for latching pattern data supplied thereto from the memory device via a serial data path, a pattern register for storing pattern data nominally identical to those stored in the memory device, and means for comparing at least corresponding portions of the pattern data supplied from the serial data register and of the pattern data stored in the pattern register.

6. Apparatus according to claim 5, in which the latching means is a serial data register whose output is connected by way of a sense amplifier and a second serial data path to the pattern register.

7. Apparatus according to claim 6, comprising a third serial data path connected to the output of the comparing means-for providing data indicative of the result of the comparison.

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8. Apparatus according to claim 5, 6 or 7, in which the memory device is a RAM device, and comprising address control means for accessing successive rows of the pattern data stored in the RAM device for storage in the latching means.

9. A test method substantially as described herein with reference to Figures 2 and 3 of the accompanying drawings.

10. Apparatus for testing a memory device, substantially as described herein with reference to Figures 2 and 3 of the accompanying drawings.

Published 1991 atThe Patent Office. State House. 66/71 High Holborn. L4DndonWCIR47?. Further copies may be obtained from SaJes Branch, Unit 6. Nir!t Mile Point Cvvmfelinfach. Cross Keys. Newport. NPI 7HZ. Printed by Multiplex techniques ltd, St Mary Cray. Kent