KR910001778A - Test method of memory device with built-in serial data path - Google Patents

Test method of memory device with built-in serial data path Download PDF

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Publication number
KR910001778A
KR910001778A KR1019890008001A KR890008001A KR910001778A KR 910001778 A KR910001778 A KR 910001778A KR 1019890008001 A KR1019890008001 A KR 1019890008001A KR 890008001 A KR890008001 A KR 890008001A KR 910001778 A KR910001778 A KR 910001778A
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KR
South Korea
Prior art keywords
data
path
pattern
test method
serial
Prior art date
Application number
KR1019890008001A
Other languages
Korean (ko)
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KR920001079B1 (en
Inventor
정형섭
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019890008001A priority Critical patent/KR920001079B1/en
Priority to JP2018100A priority patent/JPH0312099A/en
Priority to GB9012833A priority patent/GB2235074A/en
Priority to DE4018438A priority patent/DE4018438C2/en
Publication of KR910001778A publication Critical patent/KR910001778A/en
Application granted granted Critical
Publication of KR920001079B1 publication Critical patent/KR920001079B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/32—Serial access; Scan testing

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

내용 없음No content

Description

직렬데이타 통로가 내장된 메모리소자의 테스트방법Test method of memory device with built-in serial data path

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 실시회로도를 나타낸 블럭 다이어그램도,2 is a block diagram showing an implementation circuit diagram of the present invention;

제3도는 본 발명의 메모리소자의 테스트방법을 나타낸 플로우챠트이다.3 is a flowchart showing a test method of the memory device of the present invention.

Claims (4)

램에 저장된 데이타가 직렬로 전송하는 데이타통로를 통하여 공급되게 하는 수단과, 패턴레지스터내의 패턴데이타(PD)와 직렬 데이타 통로를 통하여 공급되는 데이타를 비교하는 수단과, 로 램테스트를 행하는 직렬데이타 통로가 내장된 메모리소자의 테스트방법.Means for causing data stored in the RAM to be supplied through a serial data transmission path; means for comparing the data supplied through the serial data path with the pattern data (PD) in the pattern register; and a serial data path for performing a raw RAM test. Test method for a built-in memory device. 제1항에 있어서, 데이타를 전송하는 직렬데이타 통로는 램(1)과 연결된 데이타 래지스터(3)에 래치될 데이타를 공급하는 제1통로(2)와, 센스앰프(4)에서 증폭된 데이타가 비교 데이타 패턴제지스터(7)에 전달하는 제2통로(6)와, 패턴데이타와 상기 제2통로를 통하여 공급되는 데이타를 비교한 출력이 발생되는 제3통로(8)와, 를 가지는 직렬데이타 통로가 내장된 메모리소자의 테스트방법.2. The serial data path for transmitting data according to claim 1, wherein the serial data path for transmitting data includes a first path (2) for supplying data to be latched to a data register (3) connected to the RAM (1), and data amplified by the sense amplifier (4). A second passage (6) to be transmitted to the comparison data pattern resistor (7), a third passage (8) where an output comparing the pattern data and the data supplied through the second passage is generated, and a serial having Test method for a memory device with a built-in data path. 제1항 또는 제2항에 있어서, 패턴데이타와 제2통로를 통하여 공급되는 데이타를 비교하는 비교데이타 패턴레지스터(7)에서 상기 비교데이타 패턴레지스터의 동작이 완료된 경우에 새로운 데이타를 받아들여 새로운 비교 동작을 행하도록한 직렬데이타 통로가 내장된 메모리소자의 테스트방법.The comparison data pattern register 7 according to claim 1 or 2, wherein new data is received when the operation of the comparison data pattern register is completed in the comparison data pattern register 7 for comparing the pattern data and the data supplied through the second passage. A test method for a memory device having a built-in serial data path for performing an operation. 제1항 또는 제2항에 있어서, 비교된 출력을 발생하는 제3통로(9)는 상기 비교된 데이타의 일치 및 불일치에 대한 프래그신호가 논리신호로서 공급되게한 직렬데이타 통로가 내장된 메모리소자의 테스트방법.3. The memory according to claim 1 or 2, wherein the third passage (9) which generates the compared output includes a memory having a serial data path for supplying a flag signal for the coincidence and inconsistency of the compared data as a logic signal. Device test method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890008001A 1989-06-10 1989-06-10 Method which tests memory material KR920001079B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019890008001A KR920001079B1 (en) 1989-06-10 1989-06-10 Method which tests memory material
JP2018100A JPH0312099A (en) 1989-06-10 1990-01-30 Method of testing recording element with series data transmission path
GB9012833A GB2235074A (en) 1989-06-10 1990-06-08 Testing a memory device
DE4018438A DE4018438C2 (en) 1989-06-10 1990-06-08 Method for testing a RAM memory device with internal serial data paths

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890008001A KR920001079B1 (en) 1989-06-10 1989-06-10 Method which tests memory material

Publications (2)

Publication Number Publication Date
KR910001778A true KR910001778A (en) 1991-01-31
KR920001079B1 KR920001079B1 (en) 1992-02-01

Family

ID=19286969

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890008001A KR920001079B1 (en) 1989-06-10 1989-06-10 Method which tests memory material

Country Status (4)

Country Link
JP (1) JPH0312099A (en)
KR (1) KR920001079B1 (en)
DE (1) DE4018438C2 (en)
GB (1) GB2235074A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5790559A (en) * 1996-03-29 1998-08-04 Advantest Corporation Semiconductor memory testing apparatus
DE19930169B4 (en) 1999-06-30 2004-09-30 Infineon Technologies Ag Test device and method for testing a memory
DE10139724B4 (en) 2001-08-13 2004-04-08 Infineon Technologies Ag Integrated dynamic memory with memory cells in several memory banks and method for operating such a memory
DE102004040799A1 (en) * 2004-08-23 2006-03-09 Infineon Technologies Ag Computer memory chip testing method in which an external test unit is used and test data written to reference and test registers prior to a bit by bit comparison of the two
KR100825013B1 (en) * 2006-09-28 2008-04-24 주식회사 하이닉스반도체 Semiconductor device for command test of package level
CN110501554B (en) * 2019-08-15 2022-04-26 苏州浪潮智能科技有限公司 Detection method and device for installation of memory chip

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3961252A (en) * 1974-12-20 1976-06-01 International Business Machines Corporation Testing embedded arrays
WO1983002164A1 (en) * 1981-12-17 1983-06-23 Ryan, Philip, Meade Apparatus for high speed fault mapping of large memories
JPS59121687A (en) * 1982-12-27 1984-07-13 Fujitsu Ltd Method for testing bubble memory element
NO843375L (en) * 1983-10-06 1985-04-09 Honeywell Inf Systems DATA PROCESSING SYSTEM AND PROCEDURE FOR MAINTENANCE AND REQUEST
DE3886038T2 (en) * 1988-07-13 1994-05-19 Philips Nv Storage device which contains a static RAM memory adapted for carrying out a self-test and integrated circuit which contains such a device as built-in static RAM memory.

Also Published As

Publication number Publication date
KR920001079B1 (en) 1992-02-01
GB9012833D0 (en) 1990-08-01
DE4018438C2 (en) 1995-10-19
DE4018438A1 (en) 1991-01-24
JPH0312099A (en) 1991-01-21
GB2235074A (en) 1991-02-20

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