GB1470264A - Process for forming contact area between polycrystalline silicon and single-crystal silicon and semiconductor structures including such contact area - Google Patents

Process for forming contact area between polycrystalline silicon and single-crystal silicon and semiconductor structures including such contact area

Info

Publication number
GB1470264A
GB1470264A GB683675A GB683675A GB1470264A GB 1470264 A GB1470264 A GB 1470264A GB 683675 A GB683675 A GB 683675A GB 683675 A GB683675 A GB 683675A GB 1470264 A GB1470264 A GB 1470264A
Authority
GB
United Kingdom
Prior art keywords
silicon
contact area
substrate
insulation
single crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB683675A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera and Instrument Corp filed Critical Fairchild Camera and Instrument Corp
Publication of GB1470264A publication Critical patent/GB1470264A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H10P50/644—Anisotropic liquid etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/66—Wet etching of conductive or resistive materials
    • H10P50/663—Wet etching of conductive or resistive materials by chemical means only
    • H10P50/667—Wet etching of conductive or resistive materials by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/02—Contacts, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Recrystallisation Techniques (AREA)
GB683675A 1974-04-01 1975-02-18 Process for forming contact area between polycrystalline silicon and single-crystal silicon and semiconductor structures including such contact area Expired GB1470264A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/456,499 US3936331A (en) 1974-04-01 1974-04-01 Process for forming sloped topography contact areas between polycrystalline silicon and single-crystal silicon

Publications (1)

Publication Number Publication Date
GB1470264A true GB1470264A (en) 1977-04-14

Family

ID=23813006

Family Applications (1)

Application Number Title Priority Date Filing Date
GB683675A Expired GB1470264A (en) 1974-04-01 1975-02-18 Process for forming contact area between polycrystalline silicon and single-crystal silicon and semiconductor structures including such contact area

Country Status (6)

Country Link
US (1) US3936331A (enExample)
JP (1) JPS5847852B2 (enExample)
CA (1) CA1019468A (enExample)
DE (1) DE2511773A1 (enExample)
FR (1) FR2266302A1 (enExample)
GB (1) GB1470264A (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51114079A (en) * 1975-03-31 1976-10-07 Fujitsu Ltd Construction of semiconductor memory device
US4305760A (en) * 1978-12-22 1981-12-15 Ncr Corporation Polysilicon-to-substrate contact processing
JPS55153338A (en) * 1979-05-18 1980-11-29 Fujitsu Ltd Surface treatment of semiconductor substrate
JPS5638838A (en) * 1979-09-06 1981-04-14 Pioneer Electronic Corp Manufacture of semiconductor device
US4477963A (en) * 1980-12-23 1984-10-23 Gte Laboratories Incorporated Method of fabrication of a low capacitance self-aligned semiconductor electrode structure
NL8105920A (nl) * 1981-12-31 1983-07-18 Philips Nv Halfgeleiderinrichting en werkwijze voor het vervaardigen van een dergelijke halfgeleiderinrichting.
JPS63198323A (ja) * 1987-02-13 1988-08-17 Mitsubishi Electric Corp 半導体装置およびその製造方法
KR900005871B1 (ko) * 1987-09-21 1990-08-13 삼성전자 주식회사 반도체 메모리소자의 제조방법
KR910010167B1 (ko) * 1988-06-07 1991-12-17 삼성전자 주식회사 스택 캐패시터 dram셀 및 그의 제조방법
US5068707A (en) * 1990-05-02 1991-11-26 Nec Electronics Inc. DRAM memory cell with tapered capacitor electrodes
JP3474286B2 (ja) * 1994-10-26 2003-12-08 株式会社半導体エネルギー研究所 薄膜トランジスタの作製方法
US5773346A (en) * 1995-12-06 1998-06-30 Micron Technology, Inc. Semiconductor processing method of forming a buried contact
US6436744B1 (en) 2001-03-16 2002-08-20 International Business Machines Corporation Method and structure for creating high density buried contact for use with SOI processes for high performance logic
DE102007010563A1 (de) * 2007-02-22 2008-08-28 IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik Selektives Wachstum von polykristallinem siliziumhaltigen Halbleitermaterial auf siliziumhaltiger Halbleiteroberfläche

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3768150A (en) * 1970-02-13 1973-10-30 B Sloan Integrated circuit process utilizing orientation dependent silicon etch
US3675319A (en) * 1970-06-29 1972-07-11 Bell Telephone Labor Inc Interconnection of electrical devices
US3761785A (en) * 1971-04-23 1973-09-25 Bell Telephone Labor Inc Methods for making transistor structures
JPS5217995B2 (enExample) * 1972-02-18 1977-05-19

Also Published As

Publication number Publication date
FR2266302A1 (enExample) 1975-10-24
US3936331A (en) 1976-02-03
DE2511773A1 (de) 1975-10-09
CA1019468A (en) 1977-10-18
JPS5847852B2 (ja) 1983-10-25
JPS50134576A (enExample) 1975-10-24

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee