GB1437112A - Semiconductor device manufacture - Google Patents

Semiconductor device manufacture

Info

Publication number
GB1437112A
GB1437112A GB4213173A GB4213173A GB1437112A GB 1437112 A GB1437112 A GB 1437112A GB 4213173 A GB4213173 A GB 4213173A GB 4213173 A GB4213173 A GB 4213173A GB 1437112 A GB1437112 A GB 1437112A
Authority
GB
United Kingdom
Prior art keywords
layer
recess
oxide
nitride
semi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4213173A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Components Ltd
Original Assignee
Mullard Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mullard Ltd filed Critical Mullard Ltd
Priority to GB4213173A priority Critical patent/GB1437112A/en
Priority to DE2441170A priority patent/DE2441170C2/de
Priority to US05/502,147 priority patent/US3958040A/en
Priority to JP10143574A priority patent/JPS5342635B2/ja
Priority to FR7430482A priority patent/FR2243523B1/fr
Publication of GB1437112A publication Critical patent/GB1437112A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
    • H10W10/0124—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves the regions having non-rectangular shapes, e.g. rounded
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/143—Shadow masking

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Weting (AREA)
GB4213173A 1973-09-07 1973-09-07 Semiconductor device manufacture Expired GB1437112A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
GB4213173A GB1437112A (en) 1973-09-07 1973-09-07 Semiconductor device manufacture
DE2441170A DE2441170C2 (de) 1973-09-07 1974-08-28 Verfahren zur Herstellung einer Halbleiteranordnung
US05/502,147 US3958040A (en) 1973-09-07 1974-08-30 Semiconductor device manufacture
JP10143574A JPS5342635B2 (https=) 1973-09-07 1974-09-05
FR7430482A FR2243523B1 (https=) 1973-09-07 1974-09-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB4213173A GB1437112A (en) 1973-09-07 1973-09-07 Semiconductor device manufacture

Publications (1)

Publication Number Publication Date
GB1437112A true GB1437112A (en) 1976-05-26

Family

ID=10422998

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4213173A Expired GB1437112A (en) 1973-09-07 1973-09-07 Semiconductor device manufacture

Country Status (5)

Country Link
US (1) US3958040A (https=)
JP (1) JPS5342635B2 (https=)
DE (1) DE2441170C2 (https=)
FR (1) FR2243523B1 (https=)
GB (1) GB1437112A (https=)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0051488A3 (en) * 1980-11-06 1982-09-22 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
DE3334624A1 (de) * 1982-10-08 1984-04-12 N.V. Philips' Gloeilampenfabrieken, 5621 Eindhoven Verfahren zum herstellen einer halbleiteranordnung und nach diesem verfahren hergestellte halbleiteranordnung
US5118641A (en) * 1990-09-13 1992-06-02 Micron Technology, Inc. Methods for reducing encroachment of the field oxide into the active area on a silicon integrated circuit
US5229318A (en) * 1991-02-07 1993-07-20 France Telecom Process for buried localized oxidation of a silicon substrate and corresponding integrated circuit
US5696022A (en) * 1993-12-29 1997-12-09 Hyundai Electronics Industries Co., Ltd. Method for forming field oxide isolation film
US5726093A (en) * 1995-12-06 1998-03-10 Taiwan Semiconductor Manufacturing Company Ltd. Two-step planer field oxidation method
US5861339A (en) * 1995-10-27 1999-01-19 Integrated Device Technology, Inc. Recessed isolation with double oxidation

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3966514A (en) * 1975-06-30 1976-06-29 Ibm Corporation Method for forming dielectric isolation combining dielectric deposition and thermal oxidation
US3961999A (en) * 1975-06-30 1976-06-08 Ibm Corporation Method for forming recessed dielectric isolation with a minimized "bird's beak" problem
JPS5246784A (en) * 1975-10-11 1977-04-13 Hitachi Ltd Process for production of semiconductor device
JPS5922381B2 (ja) * 1975-12-03 1984-05-26 株式会社東芝 ハンドウタイソシノ セイゾウホウホウ
JPS5396671A (en) * 1977-02-03 1978-08-24 Oki Electric Ind Co Ltd Manufacture of semiconductor device
NL7706802A (nl) * 1977-06-21 1978-12-27 Philips Nv Werkwijze voor het vervaardigen van een half- geleiderinrichting en halfgeleiderinrichting vervaardigd met behulp van de werkwijze.
JPS54115085A (en) * 1978-02-28 1979-09-07 Cho Lsi Gijutsu Kenkyu Kumiai Method of fabricating semiconductor
JPS5538084A (en) * 1978-09-11 1980-03-17 Nec Corp Semiconductor integrated circuit device
US4278705A (en) * 1979-11-08 1981-07-14 Bell Telephone Laboratories, Incorporated Sequentially annealed oxidation of silicon to fill trenches with silicon dioxide
US4271583A (en) * 1980-03-10 1981-06-09 Bell Telephone Laboratories, Incorporated Fabrication of semiconductor devices having planar recessed oxide isolation region
US4333965A (en) * 1980-09-15 1982-06-08 General Electric Company Method of making integrated circuits
US4506435A (en) * 1981-07-27 1985-03-26 International Business Machines Corporation Method for forming recessed isolated regions
US4454647A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
US4454646A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
US4372033A (en) * 1981-09-08 1983-02-08 Ncr Corporation Method of making coplanar MOS IC structures
US4563227A (en) * 1981-12-08 1986-01-07 Matsushita Electric Industrial Co., Ltd. Method for manufacturing a semiconductor device
US4443932A (en) * 1982-01-18 1984-04-24 Motorla, Inc. Self-aligned oxide isolated process and device
US4398992A (en) * 1982-05-20 1983-08-16 Hewlett-Packard Company Defect free zero oxide encroachment process for semiconductor fabrication
DE3225961A1 (de) * 1982-07-10 1984-01-12 Engl, Walter L., Prof. Dr.rer.nat., 5120 Herzogenrath Verfahren zum herstellen eines isolationsbereiches bei halbleiteranordnungen
JPS5990925A (ja) * 1982-11-17 1984-05-25 Matsushita Electronics Corp 半導体装置の製造方法
US4407696A (en) * 1982-12-27 1983-10-04 Mostek Corporation Fabrication of isolation oxidation for MOS circuit
NL8401711A (nl) * 1984-05-29 1985-12-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een siliciumlichaam waarin plaatselijk een verzonken oxidelaag is aangebracht.
US4561172A (en) * 1984-06-15 1985-12-31 Texas Instruments Incorporated Integrated circuit fabrication method utilizing selective etching and oxidation to form isolation regions
US4538343A (en) * 1984-06-15 1985-09-03 Texas Instruments Incorporated Channel stop isolation technology utilizing two-step etching and selective oxidation with sidewall masking
US4583281A (en) * 1985-03-13 1986-04-22 General Electric Company Method of making an integrated circuit
US4631113A (en) * 1985-12-23 1986-12-23 Signetics Corporation Method for manufacturing a narrow line of photosensitive material
US4862232A (en) * 1986-09-22 1989-08-29 General Motors Corporation Transistor structure for high temperature logic circuits with insulation around source and drain regions
US4714685A (en) * 1986-12-08 1987-12-22 General Motors Corporation Method of fabricating self-aligned silicon-on-insulator like devices
US4797718A (en) * 1986-12-08 1989-01-10 Delco Electronics Corporation Self-aligned silicon MOS device
US4749441A (en) * 1986-12-11 1988-06-07 General Motors Corporation Semiconductor mushroom structure fabrication
US4903107A (en) * 1986-12-29 1990-02-20 General Electric Company Buried oxide field isolation structure with composite dielectric
US4923563A (en) * 1987-06-15 1990-05-08 Ncr Corporation Semiconductor field oxide formation process using a sealing sidewall of consumable nitride
US4760036A (en) * 1987-06-15 1988-07-26 Delco Electronics Corporation Process for growing silicon-on-insulator wafers using lateral epitaxial growth with seed window oxidation
DE3728348A1 (de) * 1987-08-25 1989-03-09 Siemens Ag Mehrlagenverdrahtung fuer hoechstintegrierte halbleiterbauelemente
JPH0227338A (ja) * 1988-07-15 1990-01-30 Konica Corp 写真フィルム用マガジン
US5443998A (en) * 1989-08-01 1995-08-22 Cypress Semiconductor Corp. Method of forming a chlorinated silicon nitride barrier layer
KR0149527B1 (ko) * 1994-06-15 1998-10-01 김주용 반도체 소자의 고전압용 트랜지스터 및 그 제조방법
US7118991B2 (en) * 2004-04-01 2006-10-10 Delphi Technologies, Inc. Encapsulation wafer process
US9142400B1 (en) 2012-07-17 2015-09-22 Stc.Unm Method of making a heteroepitaxial layer on a seed area
US11646361B2 (en) 2021-03-04 2023-05-09 Globalfoundries U.S. Inc. Electrical isolation structure using reverse dopant implantation from source/drain region in semiconductor fin

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1208577A (en) * 1966-10-05 1970-10-14 Philips Electronic Associated Methods of manufacturing semiconductor devices
NL153374B (nl) 1966-10-05 1977-05-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting voorzien van een oxydelaag en halfgeleiderinrichting vervaardigd volgens de werkwijze.
GB1235178A (en) * 1967-06-08 1971-06-09 Philips Electronic Associated Methods of manufacturing semiconductor devices
GB1235179A (en) * 1967-06-08 1971-06-09 Philips Electronic Associated Methods of manufacturing semiconductor devices
NL152707B (nl) * 1967-06-08 1977-03-15 Philips Nv Halfgeleiderinrichting bevattende een veldeffecttransistor van het type met geisoleerde poortelektrode en werkwijze ter vervaardiging daarvan.
NL157662B (nl) * 1969-05-22 1978-08-15 Philips Nv Werkwijze voor het etsen van een oppervlak onder toepassing van een etsmasker, alsmede voorwerpen, verkregen door toepassing van deze werkwijze.
NL170348C (nl) * 1970-07-10 1982-10-18 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een tegen dotering en tegen thermische oxydatie maskerend masker wordt aangebracht, de door de vensters in het masker vrijgelaten delen van het oppervlak worden onderworpen aan een etsbehandeling voor het vormen van verdiepingen en het halfgeleiderlichaam met het masker wordt onderworpen aan een thermische oxydatiebehandeling voor het vormen van een oxydepatroon dat de verdiepingen althans ten dele opvult.
NL7113561A (https=) * 1971-10-02 1973-04-04
US3860466A (en) * 1971-10-22 1975-01-14 Texas Instruments Inc Nitride composed masking for integrated circuits
US3810796A (en) * 1972-08-31 1974-05-14 Texas Instruments Inc Method of forming dielectrically isolated silicon diode array vidicon target
DE2409910C3 (de) * 1974-03-01 1979-03-15 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zum Herstellen einer Halbleiteranordnung

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0051488A3 (en) * 1980-11-06 1982-09-22 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
DE3334624A1 (de) * 1982-10-08 1984-04-12 N.V. Philips' Gloeilampenfabrieken, 5621 Eindhoven Verfahren zum herstellen einer halbleiteranordnung und nach diesem verfahren hergestellte halbleiteranordnung
GB2129213A (en) * 1982-10-08 1984-05-10 Philips Nv Semiconductor device with dielectric isolation
US5118641A (en) * 1990-09-13 1992-06-02 Micron Technology, Inc. Methods for reducing encroachment of the field oxide into the active area on a silicon integrated circuit
US5229318A (en) * 1991-02-07 1993-07-20 France Telecom Process for buried localized oxidation of a silicon substrate and corresponding integrated circuit
US5696022A (en) * 1993-12-29 1997-12-09 Hyundai Electronics Industries Co., Ltd. Method for forming field oxide isolation film
DE4447148C2 (de) * 1993-12-29 2002-06-20 Hyundai Electronics Ind Verfahren zur Bildung eines Elementisolationsfilms einer Halbleitervorrichtung
US5861339A (en) * 1995-10-27 1999-01-19 Integrated Device Technology, Inc. Recessed isolation with double oxidation
US5726093A (en) * 1995-12-06 1998-03-10 Taiwan Semiconductor Manufacturing Company Ltd. Two-step planer field oxidation method

Also Published As

Publication number Publication date
DE2441170A1 (de) 1975-03-13
JPS5065174A (https=) 1975-06-02
US3958040A (en) 1976-05-18
JPS5342635B2 (https=) 1978-11-13
FR2243523A1 (https=) 1975-04-04
DE2441170C2 (de) 1984-07-12
FR2243523B1 (https=) 1979-01-05

Similar Documents

Publication Publication Date Title
GB1437112A (en) Semiconductor device manufacture
GB1208574A (en) Methods of manufacturing semiconductor devices
GB1493212A (en) Semiconductor devices
GB1382082A (en) Methods of manufacturing semiconductor devices
GB1354425A (en) Semiconductor device
GB1517242A (en) Integrated circuits
GB1428713A (en) Method of manufactruing a semiconductor device
GB1515639A (en) Integrated circuits
GB1515184A (en) Semiconductor device manufacture
GB1205320A (en) Improvements in or relating to the production of semiconductor devices
JPS5666065A (en) Semiconductor memory unit
GB1315573A (en) Formation of openings in insulating layers in mos semiconductor devices
JPS5792858A (en) Semiconductor integrated circuit device and manufacture thereof
EP0002107A3 (en) Method of making a planar semiconductor device
JPS57204146A (en) Manufacture of semiconductor device
GB1099049A (en) A method of manufacturing transistors
JPS57176767A (en) Manufacture of semiconductor device
GB1377678A (en) Method of formation of an insulating film on a compownd semiconductor surface using electric discharge
GB1318976A (en) Semi-conductor devices
GB1374112A (en) Method of fabrication of an insulated gate field effect transistor
JPS52141580A (en) Manufacture of mos-type semiconductor device
FR2149384A1 (en) Semiconductor component prodn - with automatic precision mask location esp for fets
JPS5791538A (en) Manufacture of semiconductor device
JPS57188883A (en) Formation of recess-type micro-multilayer gate electrode
FR2081017A2 (en) Fabrication of a semiconductor device

Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
732 Registration of transactions, instruments or events in the register (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19920907