FR2149384A1 - Semiconductor component prodn - with automatic precision mask location esp for fets - Google Patents
Semiconductor component prodn - with automatic precision mask location esp for fetsInfo
- Publication number
- FR2149384A1 FR2149384A1 FR7228653A FR7228653A FR2149384A1 FR 2149384 A1 FR2149384 A1 FR 2149384A1 FR 7228653 A FR7228653 A FR 7228653A FR 7228653 A FR7228653 A FR 7228653A FR 2149384 A1 FR2149384 A1 FR 2149384A1
- Authority
- FR
- France
- Prior art keywords
- esp
- fets
- deposited
- semiconductor component
- windows
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
An insulating film of SiO or SiO2 is deposited on a Si substrate in the normal way and windows etched in it for the source and sink electrodes to be deposited on the exposed areas of the substrate, the windows having parallel adjacent edges. The contacts are then electroplated until there is an accurately controlled spread of metal over the edges of the windows. This defines the width of an exposed area of isthmus onto which the gate electrode finger is deposited, the distances from this third electrode to the source and sink regions thus being accurately defined.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CH1217971A CH529446A (en) | 1971-08-19 | 1971-08-19 | Self-aligning masking process, in particular for semiconductor surfaces |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2149384A1 true FR2149384A1 (en) | 1973-03-30 |
FR2149384B1 FR2149384B1 (en) | 1974-07-12 |
Family
ID=4380613
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7228653A Granted FR2149384A1 (en) | 1971-08-19 | 1972-08-03 | Semiconductor component prodn - with automatic precision mask location esp for fets |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPS4831878A (en) |
CH (1) | CH529446A (en) |
DE (1) | DE2234189A1 (en) |
FR (1) | FR2149384A1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1094517B (en) * | 1978-04-28 | 1985-08-02 | Componenti Elettronici Sgs Ate | PROCEDURE FOR THE MANUFACTURE OF A FILIFORM RESISTIVE ELEMENT FOR INTEGRATED CIRCUIT |
DE3426421A1 (en) * | 1984-07-18 | 1986-01-23 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Process for fabricating a semiconductor configuration |
-
1971
- 1971-08-19 CH CH1217971A patent/CH529446A/en not_active IP Right Cessation
-
1972
- 1972-07-12 DE DE19722234189 patent/DE2234189A1/en active Pending
- 1972-07-18 JP JP7136472A patent/JPS4831878A/ja active Pending
- 1972-08-03 FR FR7228653A patent/FR2149384A1/en active Granted
Also Published As
Publication number | Publication date |
---|---|
CH529446A (en) | 1972-10-15 |
FR2149384B1 (en) | 1974-07-12 |
DE2234189A1 (en) | 1973-03-01 |
JPS4831878A (en) | 1973-04-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |