CH529446A - Self-aligning masking process, in particular for semiconductor surfaces - Google Patents

Self-aligning masking process, in particular for semiconductor surfaces

Info

Publication number
CH529446A
CH529446A CH1217971A CH1217971A CH529446A CH 529446 A CH529446 A CH 529446A CH 1217971 A CH1217971 A CH 1217971A CH 1217971 A CH1217971 A CH 1217971A CH 529446 A CH529446 A CH 529446A
Authority
CH
Switzerland
Prior art keywords
self
masking process
semiconductor surfaces
aligning
aligning masking
Prior art date
Application number
CH1217971A
Other languages
German (de)
Inventor
F Dr Broom Ronald
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Priority to CH1217971A priority Critical patent/CH529446A/en
Priority to DE19722234189 priority patent/DE2234189A1/en
Priority to JP7136472A priority patent/JPS4831878A/ja
Priority to FR7228653A priority patent/FR2149384A1/en
Publication of CH529446A publication Critical patent/CH529446A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
CH1217971A 1971-08-19 1971-08-19 Self-aligning masking process, in particular for semiconductor surfaces CH529446A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CH1217971A CH529446A (en) 1971-08-19 1971-08-19 Self-aligning masking process, in particular for semiconductor surfaces
DE19722234189 DE2234189A1 (en) 1971-08-19 1972-07-12 METHOD FOR MASKING SEMICONDUCTOR SURFACES
JP7136472A JPS4831878A (en) 1971-08-19 1972-07-18
FR7228653A FR2149384A1 (en) 1971-08-19 1972-08-03 Semiconductor component prodn - with automatic precision mask location esp for fets

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH1217971A CH529446A (en) 1971-08-19 1971-08-19 Self-aligning masking process, in particular for semiconductor surfaces

Publications (1)

Publication Number Publication Date
CH529446A true CH529446A (en) 1972-10-15

Family

ID=4380613

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1217971A CH529446A (en) 1971-08-19 1971-08-19 Self-aligning masking process, in particular for semiconductor surfaces

Country Status (4)

Country Link
JP (1) JPS4831878A (en)
CH (1) CH529446A (en)
DE (1) DE2234189A1 (en)
FR (1) FR2149384A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2424629A1 (en) * 1978-04-28 1979-11-23 Ates Componenti Elettron PROCESS OF MANUFACTURING RESISTANT ELEMENTS FOR INTEGRATED CIRCUITS

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3426421A1 (en) * 1984-07-18 1986-01-23 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Process for fabricating a semiconductor configuration

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2424629A1 (en) * 1978-04-28 1979-11-23 Ates Componenti Elettron PROCESS OF MANUFACTURING RESISTANT ELEMENTS FOR INTEGRATED CIRCUITS

Also Published As

Publication number Publication date
FR2149384B1 (en) 1974-07-12
FR2149384A1 (en) 1973-03-30
JPS4831878A (en) 1973-04-26
DE2234189A1 (en) 1973-03-01

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Legal Events

Date Code Title Description
PL Patent ceased