DE3426421A1 - Process for fabricating a semiconductor configuration - Google Patents
Process for fabricating a semiconductor configurationInfo
- Publication number
- DE3426421A1 DE3426421A1 DE19843426421 DE3426421A DE3426421A1 DE 3426421 A1 DE3426421 A1 DE 3426421A1 DE 19843426421 DE19843426421 DE 19843426421 DE 3426421 A DE3426421 A DE 3426421A DE 3426421 A1 DE3426421 A1 DE 3426421A1
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- Prior art keywords
- insulating layer
- layer
- opening
- metal
- gate electrode
- Prior art date
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- Ceased
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- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 238000002513 implantation Methods 0.000 claims abstract description 7
- 230000008021 deposition Effects 0.000 claims abstract description 3
- 238000004519 manufacturing process Methods 0.000 claims description 8
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 238000004070 electrodeposition Methods 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims 2
- 239000004926 polymethyl methacrylate Substances 0.000 claims 2
- VVQNEPGJFQJSBK-UHFFFAOYSA-N Methyl methacrylate Chemical compound COC(=O)C(C)=C VVQNEPGJFQJSBK-UHFFFAOYSA-N 0.000 claims 1
- 239000004642 Polyimide Substances 0.000 claims 1
- 238000007747 plating Methods 0.000 claims 1
- 229920001721 polyimide Polymers 0.000 claims 1
- 230000005669 field effect Effects 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
- H01L29/66598—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
Licentia Patent-Verwaltungs-G.m.b.H. Theodor-Stern-Kai 1, 6000 Frankfurt 70Licentia Patent-Verwaltungs-G.m.b.H. Theodor-Stern-Kai 1, 6000 Frankfurt 70
TELEFUNKEN electronic GmbH Theresienstr. 2, 7100 HeilbronnTELEFUNKEN electronic GmbH Theresienstr. 2, 7100 Heilbronn
Heilbronn, den 04.07.1984 PTL-HN-La/sl HN 84/36Heilbronn, July 4th, 1984 PTL-HN-La / sl HN 84/36
Verfahren zum Herstellen einer HalbleiteranordnungMethod for manufacturing a semiconductor device
Die Erfindung betrifft ein Verfahren zum Herstellen einer Halbleiteranordnung, bei dem eine Implantationsmaske zum Herstellen von Halbleiterzonen mit Bereichen unterschiedlicher Dicke verwendet wird.The invention relates to a method for producing a semiconductor arrangement in which an implantation mask for the production of semiconductor zones with areas different thickness is used.
In der modernen Halbleitertechnik wird die isolierte Gateelektrode von Feldeffekt-Transistoren als Maske bei der Herstellung der Source- und der Drain-Zone verwendet. Dieses Verfahren wird als "self-aligning"-Verfahren bezeichnet. Bei einem speziellen Feldeffekttransistör weisen die Source- und die Drain-Zone unterschiedliche Dicken auf, und zwar sind diese Zonen in dem an die Gateelektrode angrenzenden Bereich dünner als im übrigen Bereich. Derartige Source- und Drain-Zonen werden mittels Ionenimplantation hergestellt, wobei eine T-förmige Gateelektrode als Implantationsmaske verwendet wird.In modern semiconductor technology, the insulated gate electrode of field effect transistors is used as a mask used in the manufacture of the source and drain regions. This process is called the "self-aligning" process designated. In the case of a special field effect transistor, the source and drain zones are different Thicknesses, namely these zones are thinner in the area adjoining the gate electrode than in the area remaining area. Such source and drain zones are produced by means of ion implantation, one T-shaped gate electrode is used as an implantation mask.
Die T-förmigen Gateelektroden werden mittels komplizierter Mehrlagenresist-Techniken hergestellt. Bei einem solchen Verfahren wird im ersten Schritt einThe T-shaped gate electrodes become more complicated by means of Multi-layer resist techniques produced. In such a procedure, the first step is a
Resistmaterial aufgebracht und mittels Fotolithografie eine schmale öffnung für die Gateelektrode hergestellt. In einem zweiten Schritt wird eine Metallschicht aufgedampft, die dicker ist als die Fotoresist-Schicht, Dann wird - wieder mittels .Fotolithografie - ein das erste Fenster konzentrisch überdeckender und einige um breiterer Bereich in der Fotoresist-Schicht stehengelassen. Die Metallschicht außerhalb dieses Bereichs wird entfernt und zuletzt auch das Resistmaterial. Auf diese Weise bleibt ein Metallstreifen stehen, der T-förmigen Querschnitt besitzt; d.h. er ist am Fuß schmaler als im Bereich des Daches. Dieses Verfahren ist aufwendig sowohl hinsichtlich der Zahl der Verfahrensschritte als auch der Justierung der Fotomasken. Resist material is applied and a narrow opening for the gate electrode is produced by means of photolithography. In a second step, a metal layer is vapor deposited, which is thicker than the photoresist layer, Then - again by means of photolithography - one concentrically overlapping the first window and some around wider area left in the photoresist layer. The metal layer outside this area is removed and finally the resist material. on In this way, a metal strip remains, which has a T-shaped cross-section; i.e. it is narrower at the foot than in the area of the roof. This process is complex both in terms of the number of process steps and the adjustment of the photomasks.
Der Erfindung liegt die Aufgabe zugrunde, ein Verfahren anzugeben, welches in einfacher Weise die Herstellung einer Implantationsmaske ermöglicht, die als Maske bei der Herstellung von Halbleiterzonen mit Bereichen unterschiedlicher Dicke durch Ionenimplantation verwendbar ist.The invention is based on the object of specifying a method which can be produced in a simple manner an implantation mask allows that as a mask in the production of semiconductor zones with areas of different Thickness is usable by ion implantation.
Diese Aufgabe wird bei einem Verfahren der eingangs erwähnten Art nach der Erfindung dadurch gelöst, daß in einer Isolierschicht die sich auf der Oberfläche, einer Halbleiteranordnung befindet, eine öffnung hergestellt wird, daß in dieser öffnung eine Metallschicht elektrolytisch abgeschieden wird und daß die Abscheidung derart erfolgt, daß sich das abgeschiedene Metall in Gestalt eines Überhanges aus der Öffnung heraus auf die Oberfläche der Isolierschicht erstreckt.This object is achieved in a method of the type mentioned according to the invention in that in an insulating layer which is located on the surface of a semiconductor device, an opening is made is that in this opening a metal layer is deposited electrolytically and that the deposition in such a way occurs that the deposited metal is in the form of an overhang from the opening out onto the surface the insulating layer extends.
Mit dem erfindungsgemäßen Verfahren können T- bzw. pilzförmige Implantationsmasken hergestellt werden, die insbesondere bei der Fertigung der Source- und der Drainzone von modernen Feldeffekttransistoren erforderlich sind. *With the method according to the invention, T-shaped or mushroom-shaped Implantation masks are produced, in particular required in the manufacture of the source and drain zones of modern field effect transistors are. *
Die Erfindung wird im folgenden an einem Ausführungsbeispiel erläutert. The invention is explained below using an exemplary embodiment.
Die Figur 1 zeigt den Aufbau eines nach der Erfindung hergestellten Feldeffekttransistors im Schnitt. In den Figuren 2 bis 13 ist die erfindungsgemäße Herstellung des Feldeffekttransistors in ihren Teilschritten erläutert. Figure 1 shows the structure of a according to the invention produced field effect transistor in section. In the Figures 2 to 13 is the production according to the invention of the field effect transistor explained in its sub-steps.
Nach der Figur 1 besteht ein nach der Erfindung hergestellter Feldeffekttransistor aus einem Halbleiterkörper 1 mit den im Halbleiterkörper befindlichen Source- und Drainzonen 2 und 3, einer auf dem Halbleiterkörper befindlichen Isolierschicht 4, einer Gateelektrode 5, einer zwischen der Isolierschicht 4 und der Gateelektrode 5 befindlichen Metallzwischenschicht 6 sowie aus der Sourceelektrode 7 und der Drainelektrode 8. Die Sourcezone 2 und die Drainzone 3 weisen in dem an die Gateelektrode 5 grenzenden Bereich dünnere Bereiche und 13 auf.According to FIG. 1, a field effect transistor produced according to the invention consists of a semiconductor body 1 with the source and drain zones 2 and 3 located in the semiconductor body, one on the semiconductor body located insulating layer 4, a gate electrode 5, a located between the insulating layer 4 and the gate electrode 5 metal intermediate layer 6 and from of the source electrode 7 and the drain electrode 8. The source zone 2 and the drain zone 3 have in the Gate electrode 5 adjoining area thinner areas and 13.
Zur Herstellung eines Feldeffekttransistors nach der Erfindung wird gemäß der Figur 2 auf einem Halbleiterkörper 1 eine SiO^-Schicht 9 hergestellt, die in der Figur 1 nicht dargestellt ist. In der SiO9-Schicht 9 wird eine öffnung 10 hergestellt.To produce a field effect transistor according to the invention, an SiO ^ layer 9, which is not shown in FIG. 1, is produced on a semiconductor body 1 in accordance with FIG. An opening 10 is produced in the SiO 9 layer 9.
Nach der Figur 3 wird die Öffnung mit einer dünnen Oxidschicht 4 bedeckt, die als Feldoxid bezeichnet wird.According to FIG. 3, the opening is covered with a thin oxide layer 4, which is referred to as field oxide.
Auf die Oxidschicht 4 wird gemäß der Figur 4 eine Metallschicht 6 aufgebracht, die beispielsweise aus Chromgold besteht. Diese Metallisierung erfolgt beispielsweise durch Elektroplattierung.According to FIG. 4, a metal layer 6, made for example of chrome gold, is applied to the oxide layer 4 consists. This metallization takes place, for example, by electroplating.
Die Metallschicht 6 wird gemäß der Figur 5 mit einer Fotolackschicht 10 beschichtet, in der eine öffnung 11 hergestellt wird, die der Struktur der Gateelektrode entspricht. Die Figur 5A zeigt die Anordnung in diesem Stadium in der Perspektive und die Figur 5B in Draufsicht. According to FIG. 5, the metal layer 6 is coated with a photoresist layer 10 in which an opening 11 is produced, which corresponds to the structure of the gate electrode. Figure 5A shows the arrangement in this Stage in perspective and FIG. 5B in plan view.
Die Figuren 6A und 6B zeigen die elektrolytische Metallabscheidung in der Öffnung 11 zur Herstellung der Gateelektrode 5 in zwei Phasen. In der Figur 6A ist die Metallabscheidung noch auf den Bereich der öffnung 11 beschränkt, während die Figur 6B ein Herauswachsen des abgeschiedenen Metalls aus der öffnung 11 zeigt, wobei sich die Metallschicht 5 in den Bereichen 15 und 16 seitlich auf die Fotolackschicht 14 erstreckt. Die Gateelektrode 5 hat im Endzustand im Schnitt eine T- bzw. pilzförmige Struktur. Die Figur 7A zeigt die Gateelektrode 5 in der Draufsicht und die Figur 7B in der Perspektive. Nach den Figuren 7A und 7B erstreckt sich die Gateelektrode 5 an ihren beiden Enden auf die dicke Oxidschicht 9. Dadurch entstehen Kontaktierungsbereiche 17 auf der Oxidschicht 9.Figures 6A and 6B show the electrodeposition process in the opening 11 for producing the gate electrode 5 in two phases. In Figure 6A is the metal deposition is still limited to the area of the opening 11, while FIG. 6B shows the outgrowth of the shows deposited metal from the opening 11, the metal layer 5 being in the regions 15 and 16 extends laterally onto the photoresist layer 14. In the final state, the gate electrode 5 has, in section, a T or mushroom-shaped structure. FIG. 7A shows the gate electrode 5 in plan view and FIG. 7B in perspective. According to FIGS. 7A and 7B, the gate electrode 5 extends at both ends of the thick one Oxide layer 9. This creates contact areas 17 on oxide layer 9.
Nach der Herstellung der Gateelektrode 5 wird gemäß der Figur 8 die Fotolackschicht 10 zusammen mit der Metallschicht 6 entfernt. Von der Metallschicht 6 verbleibt lediglich unter der abgeschiedenen Gateelektrode 5 noch ein Bereich.After the gate electrode 5 has been produced, according to FIG. 8, the photoresist layer 10 is formed together with the metal layer 6 removed. The metal layer 6 only remains under the deposited gate electrode 5 an area.
342642342642
Nach der Fertigstellung der Gateelektrode 5 und dem Entfernen der Fotolackschicht sowie der dünnen Metallschicht erfolgt gemäß der Figur 9 die Herstellung der Sourcezone 2 und der Drainzone 3 durch Ionenimplantation. Da die Gateelektrode 5 T-fOrmig ausgebildet ist mit relativ dünnen Bereichen 15 und 16, erfolgt auch unter den Bereichen 15 und 16 eine Implantation in den Halbleiterkörper, die jedoch wesentlich geringer ist als in dem angrenzenden Bereich, der nicht unter der Gatelektrode liegt. Infolgedessen hat sowohl die Sourcezone als auch die Drainzone Bereiche unterschiedlicher Dicke, und zwar sind diese Zonen in den Bereichen 12 und 13 dünner als im übrigen Bereich.After the completion of the gate electrode 5 and the removal of the photoresist layer and the thin metal layer According to FIG. 9, the source zone 2 and the drain zone 3 are produced by ion implantation. Since the gate electrode 5 is T-shaped with relatively thin areas 15 and 16, also takes place under areas 15 and 16 an implantation in the semiconductor body, which, however, is significantly less than in the adjacent one Area that is not under the gate electrode. As a result, has both the source region and the drain region Areas of different thickness, namely these zones in the areas 12 and 13 are thinner than the rest Area.
Im Anschluß an die Ionenimplantation wird gemäß der Figur 10 die Sourcezone 2 mit einer Sourceelektrode 18 und die Drainzone 3 mit einer Drainelektrode 19 versehen. Following the ion implantation, according to FIG. 10, the source zone 2 is provided with a source electrode 18 and the drain zone 3 is provided with a drain electrode 19.
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Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19843426421 DE3426421A1 (en) | 1984-07-18 | 1984-07-18 | Process for fabricating a semiconductor configuration |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19843426421 DE3426421A1 (en) | 1984-07-18 | 1984-07-18 | Process for fabricating a semiconductor configuration |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE3426421A1 true DE3426421A1 (en) | 1986-01-23 |
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ID=6240925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19843426421 Ceased DE3426421A1 (en) | 1984-07-18 | 1984-07-18 | Process for fabricating a semiconductor configuration |
Country Status (1)
| Country | Link |
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| DE (1) | DE3426421A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000060648A1 (en) * | 1999-03-31 | 2000-10-12 | Siemens Aktiengesellschaft | Method of producing an electrical contact on a semiconductor diode and diode with such a contact |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2234189A1 (en) * | 1971-08-19 | 1973-03-01 | Ibm | METHOD FOR MASKING SEMICONDUCTOR SURFACES |
| DE3000847A1 (en) * | 1979-02-05 | 1980-08-07 | Intel Corp | METHOD FOR DEVELOPING DOPED ZONES IN A SUBSTRATE |
-
1984
- 1984-07-18 DE DE19843426421 patent/DE3426421A1/en not_active Ceased
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2234189A1 (en) * | 1971-08-19 | 1973-03-01 | Ibm | METHOD FOR MASKING SEMICONDUCTOR SURFACES |
| DE3000847A1 (en) * | 1979-02-05 | 1980-08-07 | Intel Corp | METHOD FOR DEVELOPING DOPED ZONES IN A SUBSTRATE |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000060648A1 (en) * | 1999-03-31 | 2000-10-12 | Siemens Aktiengesellschaft | Method of producing an electrical contact on a semiconductor diode and diode with such a contact |
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