GB1112405A - Formation of small dimensioned apertures using photographic masking and etching techniques - Google Patents
Formation of small dimensioned apertures using photographic masking and etching techniquesInfo
- Publication number
- GB1112405A GB1112405A GB4325063A GB4325063A GB1112405A GB 1112405 A GB1112405 A GB 1112405A GB 4325063 A GB4325063 A GB 4325063A GB 4325063 A GB4325063 A GB 4325063A GB 1112405 A GB1112405 A GB 1112405A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- slot
- semi
- exposed
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005530 etching Methods 0.000 title abstract 2
- 230000000873 masking effect Effects 0.000 title abstract 2
- 238000000034 method Methods 0.000 title abstract 2
- 230000015572 biosynthetic process Effects 0.000 title 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 6
- 229920002120 photoresistant polymer Polymers 0.000 abstract 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 3
- 239000000463 material Substances 0.000 abstract 3
- 239000004065 semiconductor Substances 0.000 abstract 3
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 3
- 229910052751 metal Inorganic materials 0.000 abstract 2
- 239000002184 metal Substances 0.000 abstract 2
- 230000004888 barrier function Effects 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/02—Local etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
1,112,405. Semi-conductor devices. TEXAS INSTRUMENTS Ltd. 2 Nov., 1964 [1 Nov., 1963], No. 43250/63. Heading H1K. [Also in Division G2] Small-area diodes of the Schottky barrier type are produced by coating a metal film 64 with a heavily doped semi-conductor region 62 and a lightly doped region 52 on which is deposited an aluminium oxide layer 54. A photoresist layer is coated on the oxide layer and exposed through a photomask having an opaque strip. The material is then developed and the oxide thus exposed is etched away to form slot 66. The photoresist layer is then removed and a layer of silicon oxide 56 and a photoresist layer are deposited and the material exposed to same photomask turned through 90 degrees. The material is now developed and etched to form slot 68 and well 61 but the aluminium oxide layer 54 underlying slot 68 is not etched as its etching rate is far slower than that of silicon oxide. The remaining photoresist is now removed and a metal film deposited in slot 68 to form terminal 60 and semi-conductor junction 61, the area of the junction being 1.2 x 10<SP>-2</SP> square inches. Alternatively a point contact may be inserted in the well. The masking process may be also applied to integrated circuits. The two insulating layers may both be of silicon oxide.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB4325063A GB1112405A (en) | 1963-11-01 | 1963-11-01 | Formation of small dimensioned apertures using photographic masking and etching techniques |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB4325063A GB1112405A (en) | 1963-11-01 | 1963-11-01 | Formation of small dimensioned apertures using photographic masking and etching techniques |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1112405A true GB1112405A (en) | 1968-05-08 |
Family
ID=10427926
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB4325063A Expired GB1112405A (en) | 1963-11-01 | 1963-11-01 | Formation of small dimensioned apertures using photographic masking and etching techniques |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB1112405A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0030117A1 (en) * | 1979-11-28 | 1981-06-10 | Fujitsu Limited | Method of forming an opening in a negative resist film |
US4481263A (en) * | 1982-05-17 | 1984-11-06 | Raytheon Company | Programmable read only memory |
EP3333686A1 (en) * | 2008-04-22 | 2018-06-13 | Japan Display Inc. | Display device with touch panel |
-
1963
- 1963-11-01 GB GB4325063A patent/GB1112405A/en not_active Expired
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0030117A1 (en) * | 1979-11-28 | 1981-06-10 | Fujitsu Limited | Method of forming an opening in a negative resist film |
US4581316A (en) * | 1979-11-28 | 1986-04-08 | Fujitsu Limited | Method of forming resist patterns in negative photoresist layer using false pattern |
US4481263A (en) * | 1982-05-17 | 1984-11-06 | Raytheon Company | Programmable read only memory |
EP3333686A1 (en) * | 2008-04-22 | 2018-06-13 | Japan Display Inc. | Display device with touch panel |
US10168828B2 (en) | 2008-04-22 | 2019-01-01 | Japan Display Inc. | Display device with touch panel |
US10719166B2 (en) | 2008-04-22 | 2020-07-21 | Japan Display Inc. | Manufacturing method of touch panel |
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