GB1406207A - Method of manufacturing a metallic lead frame for a semiconductor device - Google Patents
Method of manufacturing a metallic lead frame for a semiconductor deviceInfo
- Publication number
- GB1406207A GB1406207A GB614574A GB614574A GB1406207A GB 1406207 A GB1406207 A GB 1406207A GB 614574 A GB614574 A GB 614574A GB 614574 A GB614574 A GB 614574A GB 1406207 A GB1406207 A GB 1406207A
- Authority
- GB
- United Kingdom
- Prior art keywords
- leads
- frame
- strip
- plate
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract 2
- 238000007747 plating Methods 0.000 abstract 2
- 229910017052 cobalt Inorganic materials 0.000 abstract 1
- 239000010941 cobalt Substances 0.000 abstract 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 abstract 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract 1
- 239000010931 gold Substances 0.000 abstract 1
- 229910052737 gold Inorganic materials 0.000 abstract 1
- 229910052759 nickel Inorganic materials 0.000 abstract 1
- 229920003023 plastic Polymers 0.000 abstract 1
- 239000004033 plastic Substances 0.000 abstract 1
- 239000010970 precious metal Substances 0.000 abstract 1
- 238000004080 punching Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
1406207 Making lead frames MATSUSHITA ELECTRONICS CORP 11 Feb 1974 [16 Feb 1973] 06145/74 Heading B3A [Also in Division H1] A metallic lead frame for a semiconductor is made by plating a strip 10 of precious metal, e.g. gold on a metallic plate and punching out the frame from the plate such that the tips of leads 2, 3, 4 are positioned on the strip 10. The metallic plate may be plated with nickel or cobalt before plating the precious strip 10, which may be positioned in the middle of, as shown, or at the side edge of the plate. After a frame having sets of leads, 2, 3, 4 has been punched out, transistor bodies are mounted on the leads 3 and electrodes of the transistors are connected to the leads 2, 4. The transistors are encapsulated with plastics whereupon each set of leads 2, 3, 4 is separated from the remainder of the frame.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP48019670A JPS5144385B2 (en) | 1973-02-16 | 1973-02-16 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1406207A true GB1406207A (en) | 1975-09-17 |
Family
ID=12005666
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB614574A Expired GB1406207A (en) | 1973-02-16 | 1974-02-11 | Method of manufacturing a metallic lead frame for a semiconductor device |
Country Status (6)
Country | Link |
---|---|
JP (1) | JPS5144385B2 (en) |
DE (1) | DE2406086A1 (en) |
FR (1) | FR2218654A1 (en) |
GB (1) | GB1406207A (en) |
IT (1) | IT1008848B (en) |
NL (1) | NL7402112A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2236062A (en) * | 1989-05-10 | 1991-03-27 | Peter Moran | Integrated circuit package |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5519001Y2 (en) * | 1975-08-15 | 1980-05-06 | ||
JPS5299069A (en) * | 1976-02-16 | 1977-08-19 | Hitachi Ltd | Production of lead frame |
JPS5322660U (en) * | 1976-08-05 | 1978-02-25 | ||
DE3040676A1 (en) * | 1980-10-29 | 1982-05-27 | Philips Patentverwaltung Gmbh, 2000 Hamburg | Semiconductor devices made using metal lead frame strip - where leads are coated with tin prior to assembling semiconductor chips into strip |
JPS5832439A (en) * | 1982-03-01 | 1983-02-25 | Nec Corp | Lead frame |
US5038453A (en) * | 1988-07-22 | 1991-08-13 | Rohm Co., Ltd. | Method of manufacturing semiconductor devices, and leadframe and differential overlapping apparatus therefor |
-
1973
- 1973-02-16 JP JP48019670A patent/JPS5144385B2/ja not_active Expired
-
1974
- 1974-02-08 DE DE19742406086 patent/DE2406086A1/en active Pending
- 1974-02-11 GB GB614574A patent/GB1406207A/en not_active Expired
- 1974-02-15 FR FR7405267A patent/FR2218654A1/fr not_active Withdrawn
- 1974-02-15 NL NL7402112A patent/NL7402112A/xx unknown
- 1974-02-15 IT IT48410/74A patent/IT1008848B/en active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2236062A (en) * | 1989-05-10 | 1991-03-27 | Peter Moran | Integrated circuit package |
GB2236062B (en) * | 1989-05-10 | 1993-05-26 | Peter Moran | Integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
NL7402112A (en) | 1974-08-20 |
FR2218654A1 (en) | 1974-09-13 |
IT1008848B (en) | 1976-11-30 |
DE2406086A1 (en) | 1974-09-05 |
JPS49107674A (en) | 1974-10-12 |
JPS5144385B2 (en) | 1976-11-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
746 | Register noted 'licences of right' (sect. 46/1977) | ||
PCNP | Patent ceased through non-payment of renewal fee |