GB1402585A - Data processing control apparatus - Google Patents

Data processing control apparatus

Info

Publication number
GB1402585A
GB1402585A GB4428772A GB4428772A GB1402585A GB 1402585 A GB1402585 A GB 1402585A GB 4428772 A GB4428772 A GB 4428772A GB 4428772 A GB4428772 A GB 4428772A GB 1402585 A GB1402585 A GB 1402585A
Authority
GB
United Kingdom
Prior art keywords
instruction
address
register
execution
loaded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4428772A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lockheed Martin Corp
Original Assignee
Sanders Associates Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanders Associates Inc filed Critical Sanders Associates Inc
Publication of GB1402585A publication Critical patent/GB1402585A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/2803—Home automation networks
    • H04L12/2807—Exchanging configuration information on appliance services in a home automation network

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
GB4428772A 1971-10-01 1972-09-25 Data processing control apparatus Expired GB1402585A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US18564971A 1971-10-01 1971-10-01

Publications (1)

Publication Number Publication Date
GB1402585A true GB1402585A (en) 1975-08-13

Family

ID=22681876

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4428772A Expired GB1402585A (en) 1971-10-01 1972-09-25 Data processing control apparatus

Country Status (13)

Country Link
US (1) US3766527A (en:Method)
JP (1) JPS4844063A (en:Method)
AU (1) AU464291B2 (en:Method)
BE (1) BE789583A (en:Method)
CA (1) CA954229A (en:Method)
CH (1) CH560933A5 (en:Method)
DE (1) DE2248296A1 (en:Method)
FR (1) FR2158833A5 (en:Method)
GB (1) GB1402585A (en:Method)
IL (1) IL40388A (en:Method)
IT (1) IT967959B (en:Method)
NL (1) NL7213248A (en:Method)
SE (1) SE393200B (en:Method)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2475763A1 (fr) * 1980-02-11 1981-08-14 Western Electric Co Processeur numerique a structure pipeline

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4040031A (en) * 1973-04-13 1977-08-02 Compagnie Honeywell Bull (Societe Anonyme) Computer instruction control apparatus and method
FR2226079A5 (en:Method) * 1973-04-13 1974-11-08 Honeywell Bull Soc Ind
JPS605978B2 (ja) * 1974-09-12 1985-02-15 富士通株式会社 記憶装置のアクセス制御方式
US3961313A (en) * 1974-12-04 1976-06-01 International Business Machines Corporation Computer control apparatus
CA1059639A (en) * 1975-03-26 1979-07-31 Garvin W. Patterson Instruction look ahead having prefetch concurrency and pipe line features
US3969724A (en) * 1975-04-04 1976-07-13 The Warner & Swasey Company Central processing unit for use in a microprocessor
SU613401A1 (ru) * 1976-07-07 1978-06-30 Предприятие П/Я В-2892 Запоминающее устройство
US4159520A (en) * 1977-01-03 1979-06-26 Motorola, Inc. Memory address control device with extender bus
SE403322B (sv) * 1977-02-28 1978-08-07 Ellemtel Utvecklings Ab Anordning i en styrdator for forkortning av exekveringstiden for instruktioner vid indirekt adressering av ett dataminne
US4287561A (en) * 1978-03-16 1981-09-01 International Business Machines Corporation Address formulation interlock mechanism
US4255785A (en) * 1978-09-25 1981-03-10 Motorola, Inc. Microprocessor having instruction fetch and execution overlap
US4298927A (en) * 1978-10-23 1981-11-03 International Business Machines Corporation Computer instruction prefetch circuit
US4521858A (en) * 1980-05-20 1985-06-04 Technology Marketing, Inc. Flexible addressing and sequencing system for operand memory and control store using dedicated micro-address registers loaded solely from alu
JPS58151655A (ja) * 1982-03-03 1983-09-08 Fujitsu Ltd 情報処理装置
JPH0776917B2 (ja) * 1984-12-29 1995-08-16 ソニー株式会社 マイクロコンピユ−タ
EP0211487A1 (en) * 1985-06-28 1987-02-25 Hewlett-Packard Company Conditional operations in computers
US4755966A (en) * 1985-06-28 1988-07-05 Hewlett-Packard Company Bidirectional branch prediction and optimization
JPS6341932A (ja) * 1985-08-22 1988-02-23 Nec Corp 分岐命令処理装置
US5101341A (en) * 1988-08-25 1992-03-31 Edgcore Technology, Inc. Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
US5163139A (en) * 1990-08-29 1992-11-10 Hitachi America, Ltd. Instruction preprocessor for conditionally combining short memory instructions into virtual long instructions
GB2282245B (en) * 1993-09-23 1998-04-15 Advanced Risc Mach Ltd Execution of data processing instructions
JPH0863355A (ja) * 1994-08-18 1996-03-08 Mitsubishi Electric Corp プログラム制御装置及びプログラム制御方法
JP3452989B2 (ja) * 1994-09-26 2003-10-06 三菱電機株式会社 中央処理装置
JP4791909B2 (ja) * 2006-08-21 2011-10-12 株式会社東芝 高速入出力機能を備える制御装置、及びその制御データの制御方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3058658A (en) * 1957-12-16 1962-10-16 Electronique Soc Nouv Control unit for digital computing systems
US3058659A (en) * 1958-12-31 1962-10-16 Ibm Add address to memory instruction
GB888732A (en:Method) * 1959-12-30
NL276236A (en:Method) * 1961-03-24
US3242464A (en) * 1961-07-31 1966-03-22 Rca Corp Data processing system
NL287533A (en:Method) * 1962-01-22
US3387278A (en) * 1965-10-20 1968-06-04 Bell Telephone Labor Inc Data processor with simultaneous testing and indexing on conditional transfer operations
US3401376A (en) * 1965-11-26 1968-09-10 Burroughs Corp Central processor
US3533075A (en) * 1967-10-19 1970-10-06 Ibm Dynamic address translation unit with look-ahead
US3551895A (en) * 1968-01-15 1970-12-29 Ibm Look-ahead branch detection system
US3544974A (en) * 1968-04-01 1970-12-01 Ibm Data processing system including buffered operands and means for controlling the sequence of processing of same
US3573852A (en) * 1968-08-30 1971-04-06 Texas Instruments Inc Variable time slot assignment of virtual processors
US3573854A (en) * 1968-12-04 1971-04-06 Texas Instruments Inc Look-ahead control for operation of program loops
US3609700A (en) * 1970-02-24 1971-09-28 Burroughs Corp Data processing system having an improved fetch overlap feature
US3651475A (en) * 1970-04-16 1972-03-21 Ibm Address modification by main/control store boundary register in a microprogrammed processor
US3717850A (en) * 1972-03-17 1973-02-20 Bell Telephone Labor Inc Programmed data processing with facilitated transfers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2475763A1 (fr) * 1980-02-11 1981-08-14 Western Electric Co Processeur numerique a structure pipeline

Also Published As

Publication number Publication date
AU464291B2 (en) 1975-08-21
US3766527A (en) 1973-10-16
JPS4844063A (en:Method) 1973-06-25
SE393200B (sv) 1977-05-02
NL7213248A (en:Method) 1973-04-03
AU4699272A (en) 1974-03-28
FR2158833A5 (en:Method) 1973-06-15
CA954229A (en) 1974-09-03
IL40388A (en) 1975-11-25
BE789583A (fr) 1973-02-01
DE2248296A1 (de) 1973-04-05
IT967959B (it) 1974-03-11
CH560933A5 (en:Method) 1975-04-15
IL40388A0 (en) 1972-11-28

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee