JPS5668848A - Memory control unit - Google Patents

Memory control unit

Info

Publication number
JPS5668848A
JPS5668848A JP14504979A JP14504979A JPS5668848A JP S5668848 A JPS5668848 A JP S5668848A JP 14504979 A JP14504979 A JP 14504979A JP 14504979 A JP14504979 A JP 14504979A JP S5668848 A JPS5668848 A JP S5668848A
Authority
JP
Japan
Prior art keywords
address
registers
register
contents
designation signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14504979A
Other languages
Japanese (ja)
Inventor
Kunihiko Hirashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP14504979A priority Critical patent/JPS5668848A/en
Publication of JPS5668848A publication Critical patent/JPS5668848A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To increase the throughput with a simple constitution, by installing the address incrementer which converts the storage contents of the address register into the subsequent address designation signal in response to the address designation output of the register.
CONSTITUTION: A successive and parallel process is carried out for four types of programs, the corresponding program address registers 11W14 are provided in order to read an instruction of the program in correspondence to each of the registers 11W14. The selection for these registers is carried out by means of the contents of the counter 15 provided separately. According to the count contents, the selection signal to select one of the address registers is decoded 16. Then the address incrementer 18 is provided to convert the memory contents of the address register into the subsequent address designation signal in response to the address designation signal output of the register. As a result, the throughput can be increased with a simple constitution.
COPYRIGHT: (C)1981,JPO&Japio
JP14504979A 1979-11-09 1979-11-09 Memory control unit Pending JPS5668848A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14504979A JPS5668848A (en) 1979-11-09 1979-11-09 Memory control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14504979A JPS5668848A (en) 1979-11-09 1979-11-09 Memory control unit

Publications (1)

Publication Number Publication Date
JPS5668848A true JPS5668848A (en) 1981-06-09

Family

ID=15376194

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14504979A Pending JPS5668848A (en) 1979-11-09 1979-11-09 Memory control unit

Country Status (1)

Country Link
JP (1) JPS5668848A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5919290A (en) * 1982-07-21 1984-01-31 スペリ・コ−ポレ−シヨン Common memory system
JPS5984228A (en) * 1982-11-05 1984-05-15 Minolta Camera Co Ltd Interchangeable lens
JPS623353A (en) * 1985-06-28 1987-01-09 Toshiba Corp Address space expanding device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5919290A (en) * 1982-07-21 1984-01-31 スペリ・コ−ポレ−シヨン Common memory system
JPS5984228A (en) * 1982-11-05 1984-05-15 Minolta Camera Co Ltd Interchangeable lens
JPS6247287B2 (en) * 1982-11-05 1987-10-07 Minolta Camera Kk
JPS623353A (en) * 1985-06-28 1987-01-09 Toshiba Corp Address space expanding device

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