JPS5497342A - Microprogram control system - Google Patents

Microprogram control system

Info

Publication number
JPS5497342A
JPS5497342A JP459878A JP459878A JPS5497342A JP S5497342 A JPS5497342 A JP S5497342A JP 459878 A JP459878 A JP 459878A JP 459878 A JP459878 A JP 459878A JP S5497342 A JPS5497342 A JP S5497342A
Authority
JP
Japan
Prior art keywords
memory
control
decoder
information
commands
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP459878A
Other languages
Japanese (ja)
Inventor
Koki Toyosawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP459878A priority Critical patent/JPS5497342A/en
Publication of JPS5497342A publication Critical patent/JPS5497342A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To shorten a memory-access latency time by starting access to a control memory for obtaining next-step information nearly at the same time as the execution start of a control step.
CONSTITUTION: Decoder 15 is for general control commands of the kind such as arithmetic control commands among pieces of information read out from control memory 12, and decoder 16 for memory actuation commands of the kinds. Namely, general control commands are decided on one machine cycle by being generated with the decoded output of decoder 15 set to control data register CDR13. On the other hand, some of control information relating to main-memory actuation is generated by directly using the output of decoder 16. Consequently, access to memory 12 for obtaining control information in the next step starts at nearly the same time as the execution start of one control step and the information is sent right after being read out from memory 12, so that the memory-access latency time can be shortened as long as that.
COPYRIGHT: (C)1979,JPO&Japio
JP459878A 1978-01-19 1978-01-19 Microprogram control system Pending JPS5497342A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP459878A JPS5497342A (en) 1978-01-19 1978-01-19 Microprogram control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP459878A JPS5497342A (en) 1978-01-19 1978-01-19 Microprogram control system

Publications (1)

Publication Number Publication Date
JPS5497342A true JPS5497342A (en) 1979-08-01

Family

ID=11588474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP459878A Pending JPS5497342A (en) 1978-01-19 1978-01-19 Microprogram control system

Country Status (1)

Country Link
JP (1) JPS5497342A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59100256U (en) * 1982-12-24 1984-07-06 株式会社小松製作所 Automatic flaw detection equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59100256U (en) * 1982-12-24 1984-07-06 株式会社小松製作所 Automatic flaw detection equipment

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